ATxmega128A3U-MHR - E-LAB Computers

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Figure 37-331. SDA hold time vs. supply voltage.Hold time [ns]5004504003350300225020015010050102.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6V CC [V]37.4.12 PDI characteristicsFigure 37-332. Maximum PDI frequency vs. V CC .36-40°C3125°C85°Cf MAX [MHz]262116112.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6V CC [V]XMEGA A3U [DATASHEET]8386C–AVR–02/2013322
38. Errata38.1 ATxmega64A3U, <strong>ATxmega128A3U</strong>, ATxmega192A3U, ATxmega256A3U38.1.1 Rev. G• AWeX fault protection restore is not done correct in Pattern Generation ModeWhen a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN isrestored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM),this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM),OUTOVEN should instead have been restored according to the DTILSBUF register.For CWCM no workaround is required.For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correctOUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correctoutputs again.38.1.2 Rev. A-FNot sampled.XMEGA A3U [DATASHEET]8386C–AVR–02/2013323
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Features8/16-bit Atmel XMEGA A3U Mi
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3. OverviewThe Atmel AVR XMEGA is a
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4. ResourcesA comprehensive set of
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The arithmetic logic unit (ALU) sup
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Six of the 32 registers can be used
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7.3.4 Production Signature RowThe p
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7.8 Data Memory and Bus Arbitration
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8. DMAC - Direct Memory Access Cont
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Figure 9-1.Event system overview an
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Figure 10-1. The clock system, cloc
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11. Power Management and Sleep Mode
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12. System Control and Reset12.1 Fe
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13. WDT - Watchdog Timer13.1 Featur
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Program address(base address) Sourc
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15.3.1 Push-pullFigure 15-1. I/O co
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15.4 Input sensingInput sensing is
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Only Timer/Counter 0 has the split
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18. AWeX - Advanced Waveform Extens
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20. RTC - 16-bit Real-Time Counter2
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Multipacket transfer enables a data
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23. SPI - Serial Peripheral Interfa
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25. IRCOM - IR Communication Module
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28. ADC - 12-bit Analog to Digital
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29. DAC - 12-bit Digital to Analog
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30. AC - Analog Comparator30.1 Feat
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31. Programming and Debugging31.1 F
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TXDnSSMOSIMISOSCKTransmitter Data f
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Table 32-3.Port C - alternate funct
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33. Peripheral Module Address MapTh
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34. Instruction Set SummaryMnemonic
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Mnemonics Operands Description Oper
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35. Packaging information35.1 64API
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36. Electrical CharacteristicsAll t
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36.1.3 Current consumptionTable 36-
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36.1.4 Wake-up time from sleep mode
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Symbol Parameter Condition Min. Typ
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Table 36-21. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.1.14.6 Ext
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36.1.15 SPI CharacteristicsFigure 3
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36.1.16 Two-Wire Interface Characte
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36.2 ATxmega128A3U36.2.1 Absolute M
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36.2.6 ADC characteristicsTable 36-
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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37.2.10 Oscillator Characteristics3
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Figure 37-159. 32MHz internal oscil
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Figure 37-163. 48MHz internal oscil
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37.3 ATxmega192A3U37.3.1 Current co
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-179. Idle mode supply cur
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Figure 37-187. I/O pin pull-up resi
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Figure 37-199. I/O pin input thresh
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Figure 37-203. INL error vs. input
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Figure 37-211. Offset error vs. V C
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Figure 37-215. DNL error vs. V REF
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Figure 37-219. Analog comparator hy
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Figure 37-223. Voltage scaler INL v
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Page 271 and 272: Figure 37-231. Reset pin input thre
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Page 277 and 278: Figure 37-242. 32MHz internal oscil
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Page 283 and 284: Figure 37-254. Active mode supply c
Page 285 and 286: Figure 37-258. Idle mode supply cur
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Page 291 and 292: Figure 37-270. I/O pin pull-up resi
Page 293 and 294: Figure 37-274. I/O pin output volta
Page 295 and 296: Figure 37-278. I/O pin output volta
Page 297 and 298: Figure 37-282. I/O pin input thresh
Page 299 and 300: Figure 37-286. INL error vs. input
Page 301 and 302: Figure 37-290. Gain error vs. V REF
Page 303 and 304: Figure 37-294. Offset error vs. V C
Page 305 and 306: Figure 37-298. DNL error vs. V REF
Page 307 and 308: Figure 37-302. Analog comparator hy
Page 309 and 310: Figure 37-306. Voltage scaler INL v
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Page 313 and 314: Figure 37-314. Reset pin input thre
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Page 317 and 318: Figure 37-321. 2MHz internal oscill
Page 321: Figure 37-329. 48MHz internal oscil
Page 325 and 326: 39.3 8386A - 07/20111. Initial revi
Page 327 and 328: 11. Power Management and Sleep Mode
Page 329: 36.4 ATxmega256A3U . . . . . . . .
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