ATxmega128A3U-MHR - E-LAB Computers

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37.2.10.5 32MHz internal oscillator calibrated to 48MHzFigure 37-161. 48MHz internal oscillator frequency vs. temperature.DFLL disabled.Frequency [MHz]52.552.051.551.050.550.049.549.048.548.047.5-45 -30 -15 0 15 30 45 60 75 90Temperature [°C]3.6 V3.0 V2.7 V2.2 V1.8 V1.6 VFigure 37-162. 48MHz internal oscillator frequency vs. temperature.DFLL enabled, from the 32.768kHz internal oscillator.Frequency [MHz]48.248.14847.947.847.747.647.51.6 V1.8 V2.2 2.7 V3.0 V3.6 V47.4-45 -30 -15 0 15 30 45 60 75 90Temperature [°C]XMEGA A3U [DATASHEET]8386C–AVR–02/2013236
Figure 37-163. 48MHz internal oscillator CALA calibration step size.V CC = 3.0V.0.34 %0.31 %Frequency Step Size [%]0.28 %0.25 %0.22 %0.19 %0.16 %0.13 %0.10 %0.07 %-40°C25°C85°C0 16 32 48 64 80 96 112 128CALA37.2.11 Two-Wire Interface characteristicsFigure 37-164. SDA hold time vs. temperature.500Hold time [ns]450340035023002502001501005010-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90Temperature [°C]XMEGA A3U [DATASHEET]8386C–AVR–02/2013237
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Features8/16-bit Atmel XMEGA A3U Mi
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3. OverviewThe Atmel AVR XMEGA is a
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4. ResourcesA comprehensive set of
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The arithmetic logic unit (ALU) sup
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Six of the 32 registers can be used
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7.3.4 Production Signature RowThe p
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7.8 Data Memory and Bus Arbitration
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8. DMAC - Direct Memory Access Cont
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Figure 9-1.Event system overview an
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Figure 10-1. The clock system, cloc
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11. Power Management and Sleep Mode
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12. System Control and Reset12.1 Fe
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13. WDT - Watchdog Timer13.1 Featur
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Program address(base address) Sourc
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15.3.1 Push-pullFigure 15-1. I/O co
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15.4 Input sensingInput sensing is
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Only Timer/Counter 0 has the split
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18. AWeX - Advanced Waveform Extens
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20. RTC - 16-bit Real-Time Counter2
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Multipacket transfer enables a data
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23. SPI - Serial Peripheral Interfa
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25. IRCOM - IR Communication Module
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28. ADC - 12-bit Analog to Digital
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29. DAC - 12-bit Digital to Analog
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30. AC - Analog Comparator30.1 Feat
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31. Programming and Debugging31.1 F
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TXDnSSMOSIMISOSCKTransmitter Data f
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Table 32-3.Port C - alternate funct
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33. Peripheral Module Address MapTh
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34. Instruction Set SummaryMnemonic
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Mnemonics Operands Description Oper
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35. Packaging information35.1 64API
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36. Electrical CharacteristicsAll t
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36.1.3 Current consumptionTable 36-
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36.1.4 Wake-up time from sleep mode
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Symbol Parameter Condition Min. Typ
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Table 36-21. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.1.14.6 Ext
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36.1.15 SPI CharacteristicsFigure 3
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36.1.16 Two-Wire Interface Characte
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36.2 ATxmega128A3U36.2.1 Absolute M
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36.2.6 ADC characteristicsTable 36-
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
Page 185 and 186: 37.1.8 External Reset Characteristi
Page 187 and 188: Figure 37-65. Reset pin input thres
Page 189 and 190: 37.1.10 Oscillator Characteristics3
Page 191 and 192: Figure 37-72. 2MHz internal oscilla
Page 193 and 194: Figure 37-76. 32MHz internal oscill
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Page 199 and 200: Figure 37-88. Active mode supply cu
Page 201 and 202: Figure 37-92. Idle mode supply curr
Page 203 and 204: Figure 37-96. Idle mode supply curr
Page 205 and 206: 37.2.1.4 Power-save mode supply cur
Page 207 and 208: Figure 37-104. I/O pin pull-up resi
Page 209 and 210: Figure 37-108. I/O pin output volta
Page 213 and 214: Figure 37-116. I/O pin input thresh
Page 215 and 216: Figure 37-120. INL error vs. input
Page 217 and 218: Figure 37-124. Gain error vs. V REF
Page 219 and 220: Figure 37-128. Offset error vs. V C
Page 221 and 222: Figure 37-132. DNL error vs. V REF
Page 223 and 224: Figure 37-136. Analog comparator hy
Page 225 and 226: Figure 37-140. Voltage scaler INL v
Page 229 and 230: Figure 37-148. Reset pin input thre
Page 235: Figure 37-159. 32MHz internal oscil
Page 241 and 242: Figure 37-171. Active mode supply c
Page 243 and 244: Figure 37-175. Idle mode supply cur
Page 247 and 248: 37.3.1.4 Power-save mode supply cur
Page 249 and 250: Figure 37-187. I/O pin pull-up resi
Page 255 and 256: Figure 37-199. I/O pin input thresh
Page 257 and 258: Figure 37-203. INL error vs. input
Page 259 and 260: Figure 37-207. Gain error vs. V REF
Page 261 and 262: Figure 37-211. Offset error vs. V C
Page 263 and 264: Figure 37-215. DNL error vs. V REF
Page 265 and 266: Figure 37-219. Analog comparator hy
Page 267 and 268: Figure 37-223. Voltage scaler INL v
Page 271 and 272: Figure 37-231. Reset pin input thre
Page 277 and 278: Figure 37-242. 32MHz internal oscil
Page 279 and 280: Figure 37-246. 48MHz internal oscil
Page 283 and 284: Figure 37-254. Active mode supply c
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Figure 37-262. Idle mode supply cur
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37.4.1.4 Power-save mode supply cur
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Figure 37-270. I/O pin pull-up resi
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Figure 37-274. I/O pin output volta
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Figure 37-278. I/O pin output volta
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Figure 37-282. I/O pin input thresh
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Figure 37-286. INL error vs. input
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Figure 37-290. Gain error vs. V REF
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Figure 37-294. Offset error vs. V C
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Figure 37-298. DNL error vs. V REF
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Figure 37-302. Analog comparator hy
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Figure 37-306. Voltage scaler INL v
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37.4.8 External Reset Characteristi
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Figure 37-314. Reset pin input thre
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37.4.10 Oscillator Characteristics3
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Figure 37-321. 2MHz internal oscill
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Figure 37-325. 32MHz internal oscil
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Figure 37-329. 48MHz internal oscil
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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