ATxmega128A3U-MHR - E-LAB Computers

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11. Power Management and Sleep Modes11.1 Features• Power management for adjusting power consumption and functions• Five sleep modes• Idle• Power down• Power save• Standby• Extended standby• Power reduction register to disable clock and turn off unused peripherals in active and idle modes11.2 OverviewVarious sleep modes and clock gating are provided in order to tailor power consumption to application requirements.This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing applicationcode. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake thedevice again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripheralsand all enabled reset sources can restore the microcontroller from sleep to active mode.In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. Whenthis is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. Thisreduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned powermanagement than sleep modes alone.11.3 Sleep ModesSleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGAmicrocontrollers have five different sleep modes tuned to match the typical functional stages during applicationexecution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake thedevice from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When anenabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normalprogram execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pendingwhen the wake-up occurs, their interrupt service routines will be executed according to their priority before the interruptservice routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before executionstarts.The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device willreset, start up, and execute from the reset vector.11.3.1 Idle ModeIn idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), butall peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabledinterrupt will wake the device.11.3.2 Power-down ModeIn power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only ofasynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowireinterface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.XMEGA A3U [DATASHEET]8386C–AVR–02/201322
11.3.3 Power-save ModePower-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keeprunning during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.11.3.4 Standby ModeStandby mode is identical to power down, with the exception that the enabled system clock sources are kept runningwhile the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.11.3.5 Extended Standby ModeExtended standby mode is identical to power-save mode, with the exception that the enabled system clock sources arekept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.XMEGA A3U [DATASHEET]8386C–AVR–02/201323
Page 1 and 2: Features8/16-bit Atmel XMEGA A3U Mi
Page 4 and 5: 3. OverviewThe Atmel AVR XMEGA is a
Page 6 and 7: 4. ResourcesA comprehensive set of
Page 8 and 9: The arithmetic logic unit (ALU) sup
Page 10 and 11: Six of the 32 registers can be used
Page 12 and 13: 7.3.4 Production Signature RowThe p
Page 14 and 15: 7.8 Data Memory and Bus Arbitration
Page 16 and 17: 8. DMAC - Direct Memory Access Cont
Page 18 and 19: Figure 9-1.Event system overview an
Page 20 and 21: Figure 10-1. The clock system, cloc
Page 24 and 25: 12. System Control and Reset12.1 Fe
Page 26 and 27: 13. WDT - Watchdog Timer13.1 Featur
Page 28 and 29: Program address(base address) Sourc
Page 30 and 31: 15.3.1 Push-pullFigure 15-1. I/O co
Page 32 and 33: 15.4 Input sensingInput sensing is
Page 34 and 35: Only Timer/Counter 0 has the split
Page 36 and 37: 18. AWeX - Advanced Waveform Extens
Page 38 and 39: 20. RTC - 16-bit Real-Time Counter2
Page 40 and 41: Multipacket transfer enables a data
Page 42 and 43: 23. SPI - Serial Peripheral Interfa
Page 44 and 45: 25. IRCOM - IR Communication Module
Page 46 and 47: 28. ADC - 12-bit Analog to Digital
Page 48 and 49: 29. DAC - 12-bit Digital to Analog
Page 50 and 51: 30. AC - Analog Comparator30.1 Feat
Page 52 and 53: 31. Programming and Debugging31.1 F
Page 54 and 55: TXDnSSMOSIMISOSCKTransmitter Data f
Page 56 and 57: Table 32-3.Port C - alternate funct
Page 58 and 59: 33. Peripheral Module Address MapTh
Page 60 and 61: 34. Instruction Set SummaryMnemonic
Page 63 and 64: Mnemonics Operands Description Oper
Page 65 and 66: 35. Packaging information35.1 64API
Page 67 and 68: 36. Electrical CharacteristicsAll t
Page 69 and 70: 36.1.3 Current consumptionTable 36-
Page 71 and 72: 36.1.4 Wake-up time from sleep mode
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Symbol Parameter Condition Min. Typ
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Table 36-21. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.1.14.6 Ext
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36.1.15 SPI CharacteristicsFigure 3
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36.1.16 Two-Wire Interface Characte
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36.2 ATxmega128A3U36.2.1 Absolute M
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36.2.3 Current consumptionTable 36-
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36.2.4 Wake-up time from sleep mode
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36.2.6 ADC characteristicsTable 36-
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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Figure 37-159. 32MHz internal oscil
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-254. Active mode supply c
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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