ATxmega128A3U-MHR - E-LAB Computers

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Figure 9-1.Event system overview and connected peripherals.CPU /SoftwareDMAControllerADCACDACEvent Routing NetworkEventSystemControllerclk PERPrescalerReal TimeCounterTimer /CountersUSBPort pinsIRCOMThe event routing network consists of eight software-configurable multiplexers that control how events are routed andused. These are called event channels, and allow for up to eight parallel event routing configurations. The maximumrouting latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.XMEGA A3U [DATASHEET]8386C–AVR–02/201318
10. System Clock and Clock options10.1 Features• Fast start-up time• Safe run-time clock switching• Internal oscillators:• 32MHz run-time calibrated and tuneable oscillator• 2MHz run-time calibrated oscillator• 32.768kHz calibrated oscillator• 32kHz ultra low power (ULP) oscillator with 1kHz output• External clock options• 0.4MHz - 16MHz crystal oscillator• 32.768kHz crystal oscillator• External clock• PLL with 20MHz - 128MHz output frequency• Internal and external clock options and 1x to 31x multiplication• Lock detector• Clock prescalers with 1x to 2048x division• Fast peripheral clocks running at two and four times the CPU clock• Automatic run-time calibration of internal oscillators• External oscillator and PLL lock failure detection with optional non-maskable interrupt10.2 OverviewAtmel AVR XMEGA A3U devices have a flexible clock system supporting a large number of clock sources. Itincorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequencyphase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibrationfeature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to removefrequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskableinterrupt and switch to the internal oscillator if the external oscillator or PLL fails.When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the devicewill always start up running from the 2MHz internal oscillator. During normal operation, the system clock source andprescalers can be changed from software at any time.Figure 10-1 on page 20 presents the principal clock system in the XMEGA A3U family of devices. Not all of the clocksneed to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and powerreduction registers, as described in “Power Management and Sleep Modes” on page 22.XMEGA A3U [DATASHEET]8386C–AVR–02/201319
Page 1 and 2: Features8/16-bit Atmel XMEGA A3U Mi
Page 4 and 5: 3. OverviewThe Atmel AVR XMEGA is a
Page 6 and 7: 4. ResourcesA comprehensive set of
Page 8 and 9: The arithmetic logic unit (ALU) sup
Page 10 and 11: Six of the 32 registers can be used
Page 12 and 13: 7.3.4 Production Signature RowThe p
Page 14 and 15: 7.8 Data Memory and Bus Arbitration
Page 16 and 17: 8. DMAC - Direct Memory Access Cont
Page 20 and 21: Figure 10-1. The clock system, cloc
Page 22 and 23: 11. Power Management and Sleep Mode
Page 24 and 25: 12. System Control and Reset12.1 Fe
Page 26 and 27: 13. WDT - Watchdog Timer13.1 Featur
Page 28 and 29: Program address(base address) Sourc
Page 30 and 31: 15.3.1 Push-pullFigure 15-1. I/O co
Page 32 and 33: 15.4 Input sensingInput sensing is
Page 34 and 35: Only Timer/Counter 0 has the split
Page 36 and 37: 18. AWeX - Advanced Waveform Extens
Page 38 and 39: 20. RTC - 16-bit Real-Time Counter2
Page 40 and 41: Multipacket transfer enables a data
Page 42 and 43: 23. SPI - Serial Peripheral Interfa
Page 44 and 45: 25. IRCOM - IR Communication Module
Page 46 and 47: 28. ADC - 12-bit Analog to Digital
Page 48 and 49: 29. DAC - 12-bit Digital to Analog
Page 50 and 51: 30. AC - Analog Comparator30.1 Feat
Page 52 and 53: 31. Programming and Debugging31.1 F
Page 54 and 55: TXDnSSMOSIMISOSCKTransmitter Data f
Page 56 and 57: Table 32-3.Port C - alternate funct
Page 58 and 59: 33. Peripheral Module Address MapTh
Page 60 and 61: 34. Instruction Set SummaryMnemonic
Page 63 and 64: Mnemonics Operands Description Oper
Page 65 and 66: 35. Packaging information35.1 64API
Page 67 and 68: 36. Electrical CharacteristicsAll t
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36.1.3 Current consumptionTable 36-
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36.1.4 Wake-up time from sleep mode
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Symbol Parameter Condition Min. Typ
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Table 36-21. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.1.14.6 Ext
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36.1.15 SPI CharacteristicsFigure 3
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36.1.16 Two-Wire Interface Characte
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36.2 ATxmega128A3U36.2.1 Absolute M
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36.2.6 ADC characteristicsTable 36-
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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Figure 37-159. 32MHz internal oscil
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-254. Active mode supply c
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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