DMDECIMAL MULTIPLY(Byte index alignment, continue after interrupt)Condition code settings:2 3 4 Result in DECAIf no illegal digit or sign is detected in the effective decimaloperand or decimal accumulator, DECIMAL MULTIPLYmultiplies the effective decimal operand (multiplicand) bythe contents of the decimal accumulator registers R14 andR15 (multiplier) and then loads the product into the entiredecimal accumulator. If the result in the decimal accumulatoris zero, the resulting sign is forced to the positive form.Affected: {DECA}, CC(DECA) x EDO -DECACondition code settings:2 3 4 Result in DECAoTrap: Decimal arithmeticIllegal di git or sign detected, instructionabortedo 0 0 0 Zero J N ·,1 I d· . t .o I ega Igl or signo 0 0 Negative detected, instruction.. completedo 0 O P oSltlveDDDECIMAL DIVIDE(Byte index alignment, continue after interrupt)0 - Illegal digit orsign detected0 Overflow0 0 0 0 Zero quotientJ0 0 0 Negative quotient0 0 0 Positive quotientDCDECIMAL COMPARE(Byte index alignment)Instruction abortedNo illegal digit orsign detected, nooverflow, i nstructioncompletedIf there is no illegal digit or sign in the effective decimaloperand or in the decimal accumulator, DECIMAL COMPAREexpands the effective decimal operand to 16 bytes (31 digitsplus sign) by appending high-order O's, algebraically comparesthe expanded decimal number to the contents of theentire decimal accumulator, and sets CC3 and CC4 accordingto the result of the comparison (a positive zero comparesequal to a negative zero).Affected: CCTrap: Decimal arithmetic(DECA) : EDOIf there is no illegal digit or sign in the effective decimaloperand and if there is at least one decimal sign in thedecimal accumulator, DECIMAL DIVIDE divides the contentsof the decimal accumulator (dividend) by the effectivedecimal operand (divisor). <strong>The</strong>n, if no overflow hasoccurred, the basic processor loads the quotient (15 decimaldigits plus sign) into the eight low-order bytes of thedecimal accumulator (registers 14 and 15), and loads theremainder (also 15 decimal digits plus sign) into the eighthigh-order bytes of the decimal accumulator (registers 12and 13). <strong>The</strong> sign of the remainder is the same as that ofthe original dividend. If the quotient is zero, the sign ofthe quotient is forced to the positive form.Condition code settings:2 3 4 Result of comparisonoIllegal digit or sign detected, instructionaborted0 0 0 0 (DECA) equals EDO1 No i! lega! digit0 0 0 (DECA) less than EDO or sign detected,instruction0 0 0 (DECA) greater than ) completedEDOOverflow occurs if any of the following conditions are notsatisfied before the initial execution of DECIMAL DIVIDE:<strong>1.</strong> <strong>The</strong> divisor must not be zero.DSADECIMAL SHIFT ARITHMETIC(Byte index alignment)2. If the length of the dividend is greater than 15 decimaldigits, the absolute value of the significant digits tothe left of the 15th digit position (i. e., those digits inregisters 12 and 13) must be less than the absolute valueof the divisor.Affected: (DECA), CC(DECA) .;- EDO -DECATrap: Decimal arithmeticIf no illegal digit or sign is detected in the decimal accumulator,DECIMAL SHIFT ARITHMETIC arithmetically shiftsthe contents of the decimal accumulator (excluding thedecimal sign), with the direction and amount of the shiftdetermined by the effective virtual address of the instruction.If the result in the decimal accumulator is zero, theresulting sign remains unchanged.84 Decimal Instructions
If no indirect addressing or indexing is used with DSA, theshift count C is the confents of bit positions 16-31 of theinstruction word. If on Iy indirect addressing is used withDSA, the shift count is the contents of bit positions 16-31of the word pointed to by the indirect address in the instructionword. If indexing only is used with DSA, theshift count is the contents of bit positions 16-31 of theinstruction word plus the contents of bit positions 14-29of the designated index register (bits 0-13, 30, and 31 ofthe index are ignored). If indirect addressing and indexingare both used with DSA, the shift count is the sum of thecontents of bit positions 16-31 of the word pointed to by theindirect address and the contents of bit positions 14-29 ofthe designated index register.<strong>The</strong> shift count, C, is treated as a 16-bit signed binaryinteger, with negative integers in two·s complement form.If the shift count is positive, the contents of the decimalaccumulator are shifted left C decimal digit positions; ifthe shift count is negative, the contents of the decimalaccumulator are shifted right -C decimal digit positions.In either case, the decimal sign is not shifted, vacateddecimal digit positions are fi lied with O·s, and any digitsshifted out of the decimal accumulator are lost. Althoughthe range of possible values for C is 2-15 $ C $ 215-<strong>1.</strong>a shift count greater than +31 or less than -31 is interpretedas a shift count of exactly +31 or -3<strong>1.</strong>PACKPACK DECIMAL DIGITS(Byte index alignment)PACK DECIMAL DIGITS converts the effective decimaloperand (assumed to be in zoned format) into a packeddecimal number and, if necessary, appends sufficient highorderO·s to produce a decimal number that is 16 bytes(31 decimal digits plus sign) in length. <strong>The</strong> zone (bits 0-3)of the low-order digit of the effective deci mal operand isused to select the sign code for the packed decimal number;all other zones are ignored in formatting the packed decimalnumber. If no i /legal digit or sign appears in the packeddecimal number, it is then loaded into the decimal accumulator.If the result in the decimal accumulator is zero,the resulting sign remains unchanged.<strong>The</strong> L field of this instruction specifies the length, in bytes,of the resultant packed decimal number in the decimal accumulator;therefore, the length of the effective decimaloperand is 2L-1 bytes (where L = 0 implies a length of31 bytes for the effecti ve deci ma I operand).Affected: (DECA), CCTrap: Decimal arithmeticIf any nonzero decimal digit is shifted out of the decimalaccumulator during a left shift, CC2 is set to 1; otherwise,CC2 is reset to O. CC2 is unconditionally reset to 0 at the •completion of a right shift.packed (EBL to EBL + 2L - 2) -DECACondition code settings:Affected: (DECA), CCCondition code settings:Trap: Decimal arithmetic2 3 4 Result in DECAo - - Illegal digit or sign detected, instructionaborted2 3 4 Result in DECAoo - 0 0 ZeroIllegal digit or sign detected, instructionabortedo 0 0 0 ZeroNo i /legal digit or sign0 0 0 Negative detected, instructioncompleted0 0 0 Positiveo - 0NegativeExample 1, L = 6:o - 0 Positiveo 0oRight shift or no nonzerodigit shifted outof DECA on left shiftOne or more nonzerodigit(s) shifted out ofDECA on left shiftNo illegal digitor sign detected,i nstructi oncompletedBefore executionAfter executionEDO X·FOF1F2F3 X·FOF1F2F3F4F5F6F7F4F5F6F7F8F9FO·F8F9FO·(DECA) xxxxxxxx X·OOOOOOOOxxxxxxxx 00000000xxxxxxxx 00000123xxxxxxxx 4567890C·CC xxxx 0010Decimal Instructions 85
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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- Page 41 and 42: is assumed to contain an XPSD or a
- Page 43 and 44: Table 3. Summary of Trap LocationsL
- Page 45 and 46: TRAP MASKSThe programmer may mask t
- Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
- Page 49 and 50: Instruction Name Mnemonic FaultDeci
- Page 51 and 52: subroutine. However, with certain c
- Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
- Page 55 and 56: CC1 is unchanged by the instruction
- Page 57 and 58: Condition code settings:2 3 4 Resul
- Page 59 and 60: Example 2, odd R field value:Before
- Page 61 and 62: significance (FS), floating zero (F
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- Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
- Page 67 and 68: Condition code settings:2 3 4 Resul
- Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
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- Page 73 and 74: Instruction NameCompare HalfwordMne
- Page 75 and 76: Condition code settings:2 3 4 Resul
- Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
- Page 79 and 80: 4. At the completion of the left sh
- Page 81 and 82: Instruction NameFloating Subtract L
- Page 83 and 84: The following table shows the possi
- Page 85 and 86: Table 8.Condition Code Settings for
- Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
- Page 89: DSTDECIMAL STORE(Byte index alignme
- Page 93 and 94: Instruction NameMnemonicDesignation
- Page 95 and 96: Both byte strings are C bytes in le
- Page 97 and 98: of the destination byte that caused
- Page 99 and 100: again present, unti I a positive or
- Page 101 and 102: The new contents of register 7 are:
- Page 103 and 104: traps to location X'42 1 as a resul
- Page 105 and 106: If there is sufficient space in the
- Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
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- Page 111 and 112: II, EI) are generated by II ORing"
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- Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
- Page 117 and 118: The XPSD instruction' is used for t
- Page 119 and 120: If (I)1O = 0, trap or interrupt ins
- Page 121 and 122: For either memory map format and ei
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- Page 125 and 126: Table 9. Status Word 0Field Bits Co
- Page 127 and 128: READ INTERRUPT INHIBITSThe followin
- Page 129 and 130: Table 11.Read Direct Mode 9 Status
- Page 131 and 132: SET ALARM INDICATORThe following co
- Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
- Page 135 and 136: Table 13.Description of I/o Instruc
- Page 137 and 138: Table 15.Device Status Byte (Regist
- Page 139 and 140: Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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