ANDAND WORD0Nord index alignment)amount of the shift are determined by bits 25-31 of theindirect word plus bits 25-31 of the specified index register.AND WORD logically ANDs the effective word into registerR. If corresponding bits of register R and the effectiveword are both 1, a 1 remains in register R; otherwise,a 0 is placed in the corresponding bit position of register R.<strong>The</strong> effective word is not affected.Affected: (R), CC3, CC4(R) n EW-RCondition code settings:2 3 4 Result in R- 0 0 Zero.- 0 Bit 0 of register R is a <strong>1.</strong>OBit 0 of register R is a 0 and bit positions 1-31of register R contain at least one <strong>1.</strong>SHIFT INSTRUCTIONS<strong>The</strong> instruction format for logical, circular, arithmetic,and searching shift operations is:SSHIFT0Nord index alignment)If neither indirect addressing nor indexing is called for inthe instruction SHIFT, bit positions 21-23 of the referenceaddress field determine the type, and bit positions 25-31determine the direction and amount of the shift.If on Iy indirect addressing is called for in the instruction,bits 15-31 of the instruction are used to access the indirectword and then bits 21-23 and 25-31 of the indirect worddetermine the type, direction, and amount of the shift.If only indexing is called for in the instruction, bits 21-23of the instruction word determine the type of shift; thedirection and amount of shift are determined by bits 25-31of the instruction plus bits 25-31 of the specified indexregister.If both indirect addressing and indexing are called for inthe instruction, bits 15-31 of the instruction are used toaccess the indirect word and then bits 21-23 of the indirectword determine the type of shift; the direction and<strong>The</strong> effective address does not reference memory. Bitpositions 15-20 and 24 of the effective virtual address areignored. Bit positions 21, 22, and 23 of the effectivevirtual address determine the type of shift, as follows:21 22 23 Shift Type0 0 0 Logical, single register0 0 Logical, double register0 0 Circular, single register0 Circular, double register0 0 Arithmetic, single register0 Arithmetic, double register0 Searching, single registerSearching, double registerBit positions 25 through 31 of the effective virtual addressare a shift count that determines the direction and amountof the shift. <strong>The</strong> shift count (C) is treated as a 7-bitsigned binary integer, with the high-order bit (bit position25) as the sign (negative integers are represented intwo's complement form). A positive shift count causes aleft shift of C bit positions. A negative shift count causesa right shift of Ici bit positions. <strong>The</strong> value of C is withinthe range: -64 ~ C ~ +63.All double-register shift operations require an even valuefor the R field of the instruction, and treat registers RandRul as a 64-bit register with the high-order bit (bit position0 of register R) as the sign for the entire register. Ifthe R field of SHIFT is an odd value and a double-registershift operation is specified, a register doubleword is formedby duplicating the contents of register R for both the32 high-order bits and the 32 !ov/-order b!ts of the doub!cword.<strong>The</strong> shift operation is then performed and the32 high-order bits of the result are loaded into register R.Overflow occurs (on left shifts only) whenever the value ofthe sign bit (bit position 0 of register R) changes. At thecompletion of logical left, circular left, arithmetic left, andsearching left shifts, the condition code is set as follows:2 3 4 Result of Shifto - Even number of l's shifted off left end ofregister R.Odd number of l's shifted off left end ofregister Rt.t Not appli cable for searching shift.70 Shift Instructions
2 3 4 Result of ShiftCircular Shift, Double Register- a No overflow on left shift.- Overflow on left shift.Searching shift terminated with Ra equal to <strong>1.</strong>At the completion of right shifts, the condition code is setas follows:a a2 3 4If the shift count, C, is positive, the contents of registers Rand Rul are shifted left C places. Bits shifted past bitposition a of register R are copied into bit position 31of reg i ster Ru <strong>1.</strong> (No bi ts are lost.) If Cis negati ve, thecontents of registers Rand Rul are shifted right lei places.Bits shifted past bit position 31 of register Ru1 are copiedinto bit position 0 of register R. (No bits are lost.)Affected: (R), (Rul), CC1, CC2Logical Shift, Single RegisterArithmetic Shift, Single RegisterIf the shift count, C, is positive, the contents of register Rare shifted left C places, the O's copied into vacated bitpositions on the right. (Bits shifted past RO are lost.) If Cis negative, the contents of register R are shifted right Iciplaces, with O's copied into vacated bit positions on theleft. (Bits shifted past R31 are lost.)Affected: (R), CC1, CC2Logical Shift, Double RegisterIf the shift count, C, is positive, the contents of register Rare shifted left C places, with O's copied into vacated bitpositions on the right. (Bits shifted past RO are lost.) If Cis negative, the contents of register R are shifted right leiplaces, with the contents of bit position a copied into vacatedbit positions on the left. (Bits shifted past R31are lost.)Affected: (R), CC1, CC2Arithmetic Shift, Double Registernr£.,Jo 1 2If the shift count, C, is positive, the contents of registersRand Ru1 are shifted left C places, with O's copied intovacated bit positions on the right. Bits shifted past bitposition a of register Ru1 are copied into bit position 31of register R. (Bits shifted past RO are lost.) If C is negative,the contents of registers Rand Ru1 are shifted rightIci places with O's copied into vacated bit positions on theleft. Bits shifted past bit position 31 of register Rarecopied into bit position a of register Ru <strong>1.</strong> (Bits shiftedpast Ru 131 are lost.)Affected: (R), (Ru1), CC1, CC2Circular Shift, Single RegisterIf the shift count, C, is positive, the contents of register Rand Rul are shifted left C places, with O's copied into vacatedbit positions on the right. Bits shifted past bit positiona of register Ru1 are copied into bit position 31 ofregister R. (Bits shifted past RO are lost.) If C is negative,the contents of registers Rand Ru1 are shifted right Iciplaces, with the contents of bit position a of register Rcopied into vacated bit positions on the left. Bits shiftedpast bit position 31 of register R are copied into bit positiona of register Ru<strong>1.</strong> (Bits shifted past Ru131 are lost.)Affected: (R), (Rul), CC1, CC2Searching Shift, Single RegisterIf the shift count, C, is positive, the contents of register Rare shifted left C places. Bits shifted 'past bit position 0are copied into bit position 3<strong>1.</strong> (No bits are lost.) If Cis negative, the contents of register R are shifted rightlei places. Bits shifted past bit position 31 are copiedinto bit position O. (No bits are lost.)Affected: (R), CC1, CC2<strong>The</strong> searching shift is circular in either direction. If theshift count, C, is positive, the contents of register Rareshifted left C bit positions or unti I a 1 appears in bit positionO. If C is negative, the contents are shifted right Icipositions or unti I a 1 appears in bit position O. When theshift is terminated, the remaining count is stored in register1, which is dedicated to the searching shift instruction.Shift Instructions 71
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
- Page 25 and 26: eference address field of the instr
- Page 27 and 28: Instruction in memory:Instruction i
- Page 29 and 30: Real-extended addressing is specifi
- Page 31: Table 1. Basic Processor Operating
- Page 35 and 36: DesignationFunctionDesignationFunct
- Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
- Page 39 and 40: AddressTable 2. Interrupt Locations
- Page 41 and 42: is assumed to contain an XPSD or a
- Page 43 and 44: Table 3. Summary of Trap LocationsL
- Page 45 and 46: TRAP MASKSThe programmer may mask t
- Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
- Page 49 and 50: Instruction Name Mnemonic FaultDeci
- Page 51 and 52: subroutine. However, with certain c
- Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
- Page 55 and 56: CC1 is unchanged by the instruction
- Page 57 and 58: Condition code settings:2 3 4 Resul
- Page 59 and 60: Example 2, odd R field value:Before
- Page 61 and 62: significance (FS), floating zero (F
- Page 63 and 64: next sequential register after regi
- Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
- Page 67 and 68: Condition code settings:2 3 4 Resul
- Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
- Page 71 and 72: original contents of register R, re
- Page 73 and 74: Instruction NameCompare HalfwordMne
- Page 75: Condition code settings:2 3 4 Resul
- Page 79 and 80: 4. At the completion of the left sh
- Page 81 and 82: Instruction NameFloating Subtract L
- Page 83 and 84: The following table shows the possi
- Page 85 and 86: Table 8.Condition Code Settings for
- Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
- Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
- Page 91 and 92: If no indirect addressing or indexi
- Page 93 and 94: Instruction NameMnemonicDesignation
- Page 95 and 96: Both byte strings are C bytes in le
- Page 97 and 98: of the destination byte that caused
- Page 99 and 100: again present, unti I a positive or
- Page 101 and 102: The new contents of register 7 are:
- Page 103 and 104: traps to location X'42 1 as a resul
- Page 105 and 106: If there is sufficient space in the
- Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
- Page 109 and 110: appropriate memory stack locations
- Page 111 and 112: II, EI) are generated by II ORing"
- Page 113 and 114: In the real extended addressing mod
- Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
- Page 117 and 118: The XPSD instruction' is used for t
- Page 119 and 120: If (I)1O = 0, trap or interrupt ins
- Page 121 and 122: For either memory map format and ei
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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