1. xerox 560 computer system - The UK Mirror Service

Instruction Name Mnemonic FaultDecimal Divide DD Overflow, i lIega IdigitDecimal Compare DC Illegal digitDecimal Shift DSA Illegal digitArithmeticPack Decimal Digits PACK Illegal digitUnpack Decimal Digits UNPK Illegal digitEdit Byte String EBS Illegal digitThe execution of XPSD or PSS in trap location X'45 1 is asfollows:1 • Store the current PSWs. (Store genera I registers ifPSS.) The stored condition code is interpreted asfollows:CC 1 CC2 CC3 CC4 MeaningooAll digits legal and overflow.Illegal digit detected.2. Load the new PSWs. The condition code and instructionaddress portions of the PSWs remain at the valuesloaded from memory.CALL INSTRUCTION TRAPThe four CALL instructions (CAll, CAL2, CAL3, and CAL4)cause the basic processor to trap to location X'48 1 (forCAll), X'49 1 (for CAL2), X'4A' (for CAL3), or X'4B ' (forCAL4). Execution of the XPSD or PSS instruction in thetrap location is as follows:1. Store the current PSWs. The stored condition code bitsare those that existed prior to the CA LL instruction.2. Store the general registers in PSS.3. Load the new PSWs.4. Modify the new PSWs.a. The R Field of the CALL instruction is logicallyORed with the condition code register as loadedfrom memory.b. If bit 9 (AI) of X PSD or PSS contains a 1, the Rfield of the CALL instruction is added to the programcounter. If AI contains a 0, the programcounter remains unchanged from the value loadedfrom memory.Note: Return from a CALL trap wi" be to the trappinginstruction + 1 •HARDWARE ERROR TRAPWATCHDOG TIMER RUNOUT TRAPThe watchdog timer monitors and controls the maximumamount of basic processor time each instruction can take.The timer is normally in operation at all times and is initializedat the beginning of each instruction. If the instructionis not completed by the time the watchdog timer has completedits count, the instruction is aborted, TCC 1 is set to 0,and a trap occurs immediately to location X'46 I • Additionalinformation as to probable cause of delay is provided:TCC2 is set if the basic processor was using the processorbus, TCC3 is set if the basic processor was using the memorybus, TCC4 is set if the basic processor was using the DIObus. The register altered flag of the PSWs is also set if anyregister or main memory location has been changed whenthe trap occurred.A watchdog timer runout is considered a basic processorfault and the PDF is set. (See "Processor Detected FaultFlag", later in this chapter.)PROGRAMMED TRAPThe programmed trap occurs at instruction interruptiblepoint. It is set by a WRITE DIRECT (WD). See Chapter 3.The basic processor traps to location X 147'.A hardware error trap occurs when either a parity or a sequencecheck fault error is detected by a memory unit, basicprocessor, or any processor communicating with the basicprocessor, resulting in a basic processor trap to locationX'4C. The Trap Condition Code bits (TCCs) are set toX'0001 ' for all hardware fault conditions except generalregister and control register parity errors, where the TCCsare set to X 10000 1 .To determine which of the possible detectable errors is responsiblefor the hardware error trap, the fault status registersof the various processors in the system must be polledwith either the POLP or POLR instruction; the memory'sstatus register must be read with the LMS instruction. Thefault status register bit settings for processors and interfacesare given in Appendix C, Table C-1. The fault status registerbit settings for the memory unit are given in AppendixC, Table C-2.If the basic processor detects or receives a report of a hardwareerror, it attempts automatic retry of the current instruction.If retry is unsuccessful, the basic processor trapsto location X '4C. If retry is successful, the basic processorresumes execution of the next instruction in the program,the Processor Fault Interrupt (PFI) and the "successful instructionretryll bit (bit position 11) in the Basic Processor FaultStatus Register are set to 1. There is automatic instructionTrap System 43