1. xerox 560 computer system - The UK Mirror Service

TRANSLA TE AND TEST BYTE STRING (TTBS)EDIT BYTE STRING (EBS)DECIMAL MULTIPLY (OM)DECIMAL DIVIDE (DO)MOVE TO MEMORY CONTROL (MMC)The control and immediate results of these instructions residein registers and memory; thus, the instruction can beinterrupted between the completion of one iteration (operandexecution cycle) and that time (during the next iteration)when a memory location or register is modified. If aninterrupt occurs during this time, the current iteration isaborted and the instruction address portion of the programstatus words (PSWs) remains pointing to the interrupted instruction.After the interrupt-servicing routine is completed,the instruction continues from the point at which itwas interrupted and does not begin anew.SINGLE-INSTRUCTION INTERRUPTSA single-instruction interrupt occurs in this situation: aninterrupt level is activated, the current program is interrupted,the single instruction in the interrupt location isexecuted, the interrupt level is automatically cleared andarmed, and the interrupted program continues without beingdisturbed or delayed (except for the time required to executethe single instruction).If any of the following instructions is executed in any interruptlocation, then the corresponding interrupt is automaticallyasingle-instruction interrupt:MODIFY AND TEST BYTE (MTB)MODIFY AND TEST HALFWORD (MTH)MODIFY AND TEST WORD (MTW)A modify and test instruction modifies the effective byte,halfword, or word (as described in Chapter 3, "Fixed-PointArithmetic Instructions") but the current condition code remainsunchanged (even if overflow occurs). The effectiveaddress of a modify and test instruction in an interrupt location(except counter 4) is always treated as an actual address,regardless of whether the memory map is currentlybeing used. Counter 4 uses the mapped location if mappingis currentiy invoked (as specified in the PSWs). I he executionof a modify and test instruction in an interruptlocation, including mapped and unmapped counter 4, is independentof the virtual memory access-protection codeand the real memory write lock; thus, a memory protectionviolation trap cannot occur as the result of overflow causedby executing MTH or MTW in an interrupt location.The execution of a modify and test instruction in an interruptlocation automatically clears and arms the corresponding interruptlevel, allowing the interrupted program to continue.When a modify and test instruction is executed in a countpulseinterrupt location, all of the above conditions applyas well as the following: If the resultant value in the effectivelocation is zero, the corresponding counter-equalszerointerrupt is triggered.TRAP SYSTEMA trap is similar to an interrupt in that when a trap conditionoccurs, program execution automatically branches to apredesignated location. A trap differs from an interrupt inthat a trap location must contain an XPSD or PSS instruction.The time of trap occurrence can vary: The instructionin the trap location can be executed immediately (i .e.,the current instruction in the program being executed isaborted), or when the current instruction has been partiallyexecuted (i.e., in the case of a long byte-string operation),or upon completion of the current instruction. The trap instructionis not held in abeyance by higher priority traps,whereas interrupts possibly may not be processed before anentire sequence of instructions is executed.TRAP ENTRY SEQUENCEA trap entry sequence begins when the basic processor detectsthe trap condition and ends when the new program statuswords (PSWs) have successfully replaced the old PSWs.Detection of any condition (function) listed in Table 3,which summarizes the trap system, results in a trap to aunique location in memory. When a trap condition occurs,the basic processor sets the trap state. The operation thebasic processor is currently performing mayor may not becarried to compietion, depending on the type of trap andthe operation being performed. In any event, the programinstruction is terminated with a trap sequence (branch to theappropriate trap location). During this sequence the programcounter is not advanced; instead, the X PSD instructionin the trap location is executed. If any interrupt level isready to move to the active state at the same time an X PSDtrap instruction is in process, the interrupt acknowledgmentwill not occur until the XPSD trap instruction is completed.Should a trap location not contain an XPSD or PSS instruction,a second trap sequence is immediately invoked (see"Instruction Exception Trap" later in this chapter).TRAP ADDRESSINGTrap addressing is described under "Interrupt and Trap EntryAddressing",36 Trap System