1. xerox 560 computer system - The UK Mirror Service

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8. Real addressing is allowed in master mode and in slavemode, and is specified when bit positions 9 and 61 ofthe PSWs both contain zero.VIRTUAL ADDRESSINGVirtual addressing uses the memory map to determine theactual address to be associated with a particular referenceaddress of each instruction. Virtual addressing differs fromreal addressing in that there is normally no exact relationshipbetween the effective virtual address and the actualaddress. These are the characteristics of virtual addressing:1. Each reference address is a 17-bit address.2. The reference address may be direct or indirect, withor without postindexing.3. Displacements associated with indexing are automaticallyaligned, as required, using the full 32-bitcontents of the index register. The final result istruncated to the left of the high-order bit of theoriginal 17-bit reference address, and the effectivevirtual address is a 16-bit doubleword address, 17-bitword address, 18-bit halfword address, or a 19-bit byteaddress.ADDRESS MODIFICA nON EXAMPLE: INDEXING(REAL AND VIRTUAL ADDRESSING)Figure 6 shows how the indexing operation takes place duringreal and virtual addressing operations. The instructionis brought from memory and loaded into a 34-bit instructionregister that initially contains zeros in the two low-orderbit positions (32 and 33). The displacement value from theindex register is then aligned with the instruction register(as an integer) according to the address type of the instruction;that is, if it is a byte operation, the low-order bit ofthe displacement is aligned with the least significant bit ofthe 34-bit instruction register (bit position 34). The displacementis then shifted one bit to the left of this positionfor a halfword operation, two bits to the left for a wordoperation, and three bits to the left for a doubleword operation.An addition process then takes place to develop a19-bit address, referred to as the effective address of theinstruction. High-order bits of the 32-bit displacement areignored in the development of this effective address (i .e.,the 15 high-order bits are ignored for word operations, the25 high-order bits are ignored for shift operations, and the16 high-order bits are ignored for doubleword operations).The displacement value, however, can cause the effectiveaddress to be less than the initial reference address (withinthe instruction) if the displacement value contains a sufficientnumber of high-order 12's (i .e., if the displacementvalue is a negative integer in two's complement form).4. Virtua I memory access protection is always invoked.If the access protection code is invalid, the instructionaborts and traps to location X'40'. (See "Trap System",later in this chapter.)5. Memory mapping translates the 8 most significant bitsof the effective virtual address (the page portion) intoan l1-bit page address. This page address is concatenatedwith the 9 least significant bits of the referenceaddress. The resultant 20-bit word address is the actualaddress used to access memory. This feature permitsanyone user at any given time to have a virtual memoryof as many as 128K words (256 pages) locatedthroughout real (actual) memory comprising as manyas 256K words (512 pages). Although virtual memorymay be physically fragmented, it is logically contiguous.Note that Sigma 6/7 programs may run on this computersystem without requiring change to the mapping structure.The memory map is loaded with 8-bit page addresses(the 3 high-order bits of the ll-bit real pageaddress are reset to zeros). The most significant 8 bitsof the effective virtual add.-ess are then translated intothe designated 8-bit page address.The effective virtual address of an instruction is always a19-bit byte address value. This value, however, is automaticallyadjusted to the information boundary conventions.Thus, for halfword operations the low-order bit of the effectivehalfword address is zero; for word operations the twolow-order bits of the effective word address are zeros; andfor doubleword operations the three low-order bits of theeffective doubleword address are zeros.In a byte operation with no indexing, the effective byteis the first byte (byte 0 in bit positions 0-7) of a word location;in a halfword operation with no indexing, the effectivehalfword is the first halfword (halfword 0 in bitpositions 0-15) of a word location. A doubleword operationalways involves a word at an even numbered addressand the word at the next sequential (which is odd numbered)word address. Thus, if an odd numbered word locationis specified for a doubleword operation, the low-order bit ofthe effective address field (bit position 31) is automaticallyforced to zero. This means that in a doubleword operationan odd numbered word (reference) address designates thesame doubleword as the next lower even numbered wordaddress.6. The memory writp.-protedion fp.otlJre is invokp.rl for thE?actual address in real memory.7. Virtual addressing may be used in all modes (master,master-protected, and slave) and is specified whenbit 9 of the PSWs contains a one.In the real addressing mode, the 19-bit effective virtualaddress is concatenated with 3 leading zeros to form a22-bit actual address. In the virtual addressing mode,the 8 most significant bits of the 19-bit virtual addressare mapped (using the memory map) into the ll-bit actualpage address, thus forming a 22-bit actual address.20 Main Memory
Instruction in memory:Instruction in instruction register:Byte operation indexing 01 ignment:I IIIIHalfword operation indexing 01 ignment:Word operation indexing 01 ignment:Shift operation indexing alignment:Doubleword operation indexing 01 ignment:Effect i ve vi rtua I address:Figure 5. Index Displacement AI ignment (Real and Virtual Addressing Modes)ADDRESS MODIFICA nON EXAMPLE: INDIRECT,INDEXED HALFWORD (VIRTUAL ADDRESSING)Figure 7 illustrates the address modification and mappingprocess for an indirectly addressed t indexed, halfword operation.As shown, reference address 1 is the content ofthe reference address field in the instruction stored in memory.The instruction is brought into the instruction register,and if the value of the reference address field is greaterthan 15, the memory map converts the 19-bit effective virtualaddress into a 22-bit actual address. The 17 low-orderbits of the main memory location pointed to by the actualaddress, labeled reference address 2, then replaces referenceaddress 1 in the instruction register. The index registerdesignated by the X field of the instruction is subsequentlyaligned for incrementing at the halfword-address level. Thefinal effective virtual address is formed by the address generator,and if the value of the reference address is greaterthan 15, the effective virtual address is transformed throughthe memory map into an actual address. The resultant 22-bitactual (main memory) address, which automatically containsa low-order 0, is then used to access the halfword to beused as the operand for the instruction.Note that for the real addressing mode, the modificationsrequired for indirect, indexed halfword operation are thesame with one exception: reference address 1 and the finaleffective address are concatenated with three leading zeros(as opposed, to being transformed by the memory map).REAL-EXTENDED ADDRESSINGReal-extended addressing is similar to real addressing in thata direct relationship exists between the effective virtual addressof each instruction and the actual address. The functionof real-extended addressing is to foci litate operationsin a memory system larger than 128K words.Note: Instructions and indirect addresses that involvereal-extended address calculations must themselvesreside in the first 128K words of memory (or in thegeneral registers), although they in turn may ultimatelyaccess operands in locations beyond the first128K words of memory.Main Memory 21
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23 and 24: 3. Diagnostic logic. Each memory dr
Page 25: eference address field of the instr
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78:
2 3 4 Result of ShiftCircular Shift
Page 79 and 80:
4. At the completion of the left sh
Page 81 and 82:
Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
Page 173 and 174:
6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
Page 177:
Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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701 South Aviation BoulevardEI Segu
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