1. xerox 560 computer system - The UK Mirror Service

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Fetch contents of register.yesAdd 16-19 bit index to17-bit reference address;17-19 bit arithmetic.Add 20-22 bit index to17-bit direct referenceaddress or 20-bit indirectreference address; 20-22bit arithmetic.Fetch contents of 20-bitreal address. If writeoperation, trap on writeprotectviolation.Map to 20-bit real address.Trap on accessprotect violation if inslave or master-protectedmodes.Figure 5. Addressing Logic18 Main Memory
eference address field of the instruction is used toobtain a word, and the 17 or 20 low-order bits of theword thus obtained effectively replace the initial referenceaddress field; then indexing is carried out accordingto the operation code of the instruction. SeeFigures 7 and 9, later in this chapter.6. Index Reference Address. If indexing is called for inthe instruction (a value other than zero in bits 12-14of the instruction), the direct or indirect reference addressis modified by addition of the displacement valuein the general register (index) called for by the instruction(after scaling the displacement according to theinstruction type). This final reference address value(after indirect addressing, indexing, or both) is definedas the effective virtual address of the instruction. Indexingafter indirect addressing is ,ca lied postindexing.See also Figures 7 and 9, later in this chapter.7. Displacements. Displacements are the 16- to 22-bitvalues used in index registers and by byte-string instructionsto generate effective addresses of the appropriatesize (byte, halfword, word, or doubleword).8. Register Address. If any instruction provides a virtualaddress that is a memory reference (i .e., a direct,indirect, or indexed reference address) in the range 0through 15, the basic processor does not attempt to readfrom or write into main memory locations 0 through 15.Instead, the four low-order bits of the reference addressare used as a general register address and the generaI reg ister correspond i ng to th is address is used as theoperand location or result destination. Thus, the instructioncan use any of the first 16 registers in the currenTregisTer biocK as Tne source or an operand, thelocation of a direct address, or the destination of a result.Such usage is called a "register-to-register"operation.9. Actual Address. This is the address value actually usedby the basic processor to access main memory via thememory address register (see Figure 5). If the effectivevirtual address is in the range 0 through 15 (X10 throughX'F '), one of the first 16 general registers in the currentregister block is being addressed. If the basic processoris operating in the virtual addressing mode, alladdresses grea ter than 15 (X 1 F I) are transformed (usua IIyinto addresses in a different memory page) by the memorymap into actual addresses. Contrarily, if the basicprocessor is operating in either real or real extendedmode, no transformation via the memory map takes place.10. Effective Address. The effective address is defined asthe final virtual address computed for an instruction.Note, however, that some instructions do not use theeffective address as a location reference; instead, theeffective address is used to control the operation ofthe instruction (as in a shift instruction), to designatethe address of an input/output device (as in an input/output instruction), or to designate a specific elementof the system (as in a READ DIRECT or WRITE DIRECTinstruction) •11. Effective Location. An effective location is definedas the actual location (in main memory or in the currentregister block) that is to receive the result of a memoryreferencinginstruction, and is referenced by means ofan effective address. Because an effective addressmay be either an actual address or a virtual address,when applicable, this definition of an effective locationassumes the transformation of a virtual address intoan actual address.12. Effective Operand. An effective operand is definedas the contents of an actual location (in main memoryor in the current register block) that is to be used asan operand by a memory-referencing instruction, andis referred to by means of an effective address. Thisalso presupposes the transformation of a virtual addressinto an actual address.TYPES OF ADDRESSINGExcept for the special type of addressing performed by someinterrupt and trap instructi ons, all addressing within thecomputer system is real, real extended, or virtual.REAL ADDRESSINGIn real addressing, a one-to-one relationship prevails betweenthe effective virtual address of each instructionand the actual address used to access main memory. Realaddressing has these characteristics:1. Each reference address is a 17-bit word address.2. The reference address may be direct or indirect, withor without postindexing.3. Displacements associated with indexing are automaticallyaligned, as required, using the full 32-bit contentsof the index register. The final result is truncated tothe left of the high-order bit of the original 17-bit referenceaddress, and the effective real address is a16-bit doubleword address, 17-bit word address, 18-bithalfword address, or a 19-bit byte address.4. If indirect addressing is invoked, the 17-bit referenceaddress in the instruction word is used to access the indirectaddress word in memory. The low-order 17 bitsof this word then replace the reference address of theinstruction word in the calculations described in (3),above.5. Memory mapping and memory access protection arenever invoked.6. Memory write protection is automatically invoked.7. Leading zeros are automatically appended to the effectiveaddress to generate an actual word address as requiredby the main memory.Main Memory 19
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23: 3. Diagnostic logic. Each memory dr
Page 27 and 28: Instruction in memory:Instruction i
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 67 and 68: Condition code settings:2 3 4 Resul
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 75 and 76:
Condition code settings:2 3 4 Resul
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
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Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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701 South Aviation BoulevardEI Segu
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