1. xerox 560 computer system - The UK Mirror Service

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o 2 3 4 5 6 78 9 10 11 12 13 '4'5 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31MnemonicSIOTIOTDVHIORIOPOlP111* I Operation Code R X t&o~~ I/o Address I ~~~~~~;:~~:!;;-~. ~--------------~--------~------~-~~-----~~----------------------------~-ing and/orOperation Code(Hexadecimal)444444CDEFFFRRRRRRXxxxxxoo 0)15 (2) 17 18 20 21 23 24 27 28 31o 000 DCACA UA 1 DCA DAo 000 DCACA UA1 DCA DAo 000 DCACA UA1 DCA DAo 000 DCA000 CA UA1 DCA DA001 CA010 CAindexingPOlRAlO46FERRXxo 1 1CA00 000o Portions of a word format that are shaded represent bits that are reserved (after the I/o address is generated) andmust be coded with zeros to ensure program compatibility with possible enhancements to software and/or hardware.o OCE = operation code field extension; CA = cluster address; UA = unit address; DCA = device controller address;DA = device address.o To address a single-unit device controller, bit 24 must be a 0; to address a multiunit device controller, bit 24must be a 1.Figure 13. Formats of I/O InstructionsTable 13.Description of I/o InstructionsBit Applicable InstructionsPosition (Mnemonics) Function and/or Description0 A!! I/O instructions If this bit is a 1; bits 15-31 of the initla! Vo instruction are modified by indirectaddressing.1-7 SIO, no, TDY, and AIO For these four instructions, the operation code uniquely defines the I/O operationthat is to be performed.HIO, RIO, POLP, and Within bit positions 1-7, these four instructions all have the same operationPOLR code (X I 4F'). The instructions are differentiated by using bits 15, 16, and 17as an extension of the operation code field.8-11 SIO, no, TDY, and HIO The value of the R field specifies how much status information is requestedfrom the addressed I/O subsystem (lOP, device controller, and device) andinto which general register{s) the status information is to be loaded. If thevalue of the R field is even and not 0, two words of status infol'rTIution OlE: IE:-quested to be loaded into registers Rand Rul. If the value of the R field is odd,one word of status information is requested to be loaded into register R.RIOAlthough the R field is not used by the RIO instruction, the R field may becoded with any value as required by the program.128 Input/Output Instructions
Table 13.Description of I/o Instructions (cont.)BitPositionApplicable Instructions(Mnemonics)Function and/or Description8-11 POLP and POLR(cont. )This field specifies which general register (including register 0) is to receiveprocessor(MIOP, RMP, BP, MI, PI, or System Control Processor) fault information.AIOIf the R field is 0, no status information is requested. If the R field is not 0, thedesignated general register is to be loaded with the requested status information.12-14All I/O instructionsThe X field may be used to specify indexing.15-17510, TIO, TDY, and AlOAfter the I/O address is generated, these bits are reserved and must be codedwith zeros.HIO, RIO, POLP, andPOLRThese bits are an extension to the operation code field (bits 1-7) and permiteach of these instructions to be uniquely defined.Note that these bits are subject to modifications due to indirect addressing orindexing. The final configuration of these bits must be as shown below:HIO = 000RIO = 001POLP = 010POLR = 01118-31All I/o instructions(except AIO)The I/O address (after any indirect addressing and/or indexing) is containedwithin these bits. Depending upon the I/O instruction, the required I/oaddress may be comprised of (1) a cluster address; (2) a cluster address and auni t addressi (3) a cluster address, a uni t address, and a devi ce controll eraddressi or (4) a cluster address, a unit address, a device controller address,and a device address.Subfields of the final I/o address field are described below.----- - -------- - - - - -1-- - - - - - - - - - - - - - - - - - - - - - - - - - --1823All I/o instructions(except Ala)These bits constitute the cluster address (CA) and the unit address (UA) fieldof an I/O instruction. Cluster and unit addresses may be assigned in thefollowing manner:1. The assignment of addresses is mutually exclusive, that is, no two unitsmay have the same address.2. Bits 18-20 represent a cluster address.3. Bits 21-23 represent a unique unit within that cluster. Since all processorclusters contain as a minimum a Processor Interface (PI) unit and a memoryinterface (MI) unit, the address (110) 21-23 and (111) 21-23 have beenpreassigned to these units.- - - - - - -- - - - - - - - - - - - - - - - - - - -AlOAfter the I/o address is generated, these bits are reserved and must be codedwith zeros.24510, TIO, TDY , and HIOIf the I/O instruction is addressed to a single-unit device controller, this bitmust be coded as a O. If the I/O instruction is addressed to a multiunit devicecontroller, this bit must be coded as a 1. Note that bit 24 is not consideredas part of the device controller address.Input/Output Instructions 129
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
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CC1 is unchanged by the instruction
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Condition code settings:2 3 4 Resul
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Example 2, odd R field value:Before
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significance (FS), floating zero (F
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next sequential register after regi
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R 1 R2 R3 MeaningoThe effective vir
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MIMULTIPLY IMMEDIATE(Immediate oper
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original contents of register R, re
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Instruction NameCompare HalfwordMne
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
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Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99 and 100: again present, unti I a positive or
Page 101 and 102: The new contents of register 7 are:
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
Page 109 and 110: appropriate memory stack locations
Page 111 and 112: II, EI) are generated by II ORing"
Page 113 and 114: In the real extended addressing mod
Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
Page 117 and 118: The XPSD instruction' is used for t
Page 119 and 120: If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131 and 132: SET ALARM INDICATORThe following co
Page 133: INPUT jOUTPUT INSTRUCTIONSThe I/o i
Page 137 and 138: Table 15.Device Status Byte (Regist
Page 139 and 140: Table 16. Operational Status Byte (
Page 141 and 142: Table 19.Status Response Bits for A
Page 143 and 144: If CC4 = 0, the MIOP is in a normal
Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
Page 147 and 148: The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
Page 151 and 152: Interrupt at Channel End (Bit Posit
Page 153 and 154: Transfer in Channel. A control lOCO
Page 155 and 156: Otherwise, the first word of the ne
Page 157 and 158: Depending upon the characteristics
Page 159 and 160: change the rate on the primary cons
Page 161 and 162: Location(hex) (dec)20 3221 3322 342
Page 163 and 164: Table 22.Diagnostic Control (P-Mode
Page 165 and 166: at its normal rate (e. g., fixed du
Page 167 and 168: SET LOW CLOCK MARGINSThis command c
Page 169 and 170: BP STATUS AND NO.Th i s group of i
Page 171 and 172: Input5MPri ntout5MFunctionStore X 1
Page 173 and 174: 6. SYSTEM CONFIGURATION CONTROLPool
Page 175 and 176: Table 25. Functions of Processor Cl
Page 177: Table 26. Functions of Memory Unit
Page 180 and 181: STANDARD 8-BIT COMPUTER CODES (EBCD
Page 182 and 183: STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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