1. xerox 560 computer system - The UK Mirror Service

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WRITE INTO INTERNAL CONTROL REGISTERThe following configuration of WD is used to write into theinternal control (or O) registers:If the R field is nonzero, the contents of register Rareloaded in the control register, as specified by the 110 Addressll field (bit positions 27-31) of the WD instruction.Except for the four 0 addresses listed below, all other addressesare reserved:The R field of the WD instruction specifies a general registerthat contains the selection bits for the individual interruptlevels within the specified group. For external interruptgroups, bit 16 of register R contains the selection bit forthe highest-priority (lowest-numbered) interrupt level withinthe group, and bit 31 of register R contains the selection bitfor the lowest-priority (highest-numbered) interrupt levelwithin the group. For assignments in Group X'O', see Table 11.Except for Power on/Power off interrupt levels, which cannot be disabled, disarmed, or inhibited, each level in thedesignated group is operated on according to the functioncode specified by bits 21-23 of the effective address of WD.The codes and their associated functions are as follows:o AddressSignificanceCodeFunctionX'lD'X'lE'{{(Bits 00-13) - Reserved.(Bits 14-31) - Write into the IIBranch From IIprogram counter.(Bits 00 through 07) - Reserved.(Bits 08 through 3l) - Write into the IILoadDevice Address ll register.If the R field is zero, the specified register is loaded withall zeros.Affected: (EL)(R) -(EL)000 Setactive all selected levels currently in the armedor waiting states.001 t Disarm all levels selected by a 1; all levels selectedby a 0 are not affected.o lOt011 t100Arm and enable all levels selected by a 1; alllevels selected by a 0 are not affected.Arm and disable all levels selected by a 1; alllevels selected by a 0 are not affected.Enable all levels selected by a 1; all levels selectedby a 0 are not affected.WRITE DIRECT, INTERRUPT CONTROL (MODE 1)101Disable all levels selected by a 1; all levels selectedby a 0 are not affected.The following configuration of WD is used to set and resetthe various states of the individual interrupt levels withinthe basi c processor interrupt system:110Enable all levels selected by a 1 and disable alllevels selected by a O.111 Trigger all levels selected by a 1. All such levelsthat are currently armed advance to waiting state.Bits 28-31 of the effective address specify the identifi cationnumber (see Table 11) of the group of interrupt levels to becontrolled by the WD instruction.tThese codes clear the current interrupts! i. e.! remove fromthe active or waiting state all levels selected by a 1 (seeFigure 12).126 Control Instructions
INPUT jOUTPUT INSTRUCTIONSThe I/o instruction set is comprised of eight instructions,as listed below.Instruction NameStart Input/OutputTest Input/OutputTest DeviceMnemonicSIOTIOTDYI/O STATUS INFORMATIONSIO, TIO, TDY, AND HIO INSTRUCTIONSIf the R field is coded with a 0, no status information is requestednor loaded. If the R field is odd, one word of statusinformation is requested to be loaded into register R as specifiedby the R field. If the R field is even (not zero), twowords of status information are requested to be loaded intoregisters Rand Ru 1 .The following I/O status information may be loaded intoregister R only when the R field is coded with an even(nonzero) value.Halt Input/OutputReset Input/OutputPoll ProcessorPoll and Reset ProcessorAcknowledge Input/Output InterruptOVERALL CHARACTERISTICSHIORIOPOLPPOLRAIOThe significance of each bit within register R is describedin Table 14.The following I/O status information may be loaded intoregister R if the R field is odd, or into register Ru 1 if theR fi e I dis even and not zero.The format of information within the specified general register(R or Ru1) is shown below.All I/o instructions are privi leged and can be performedonly when the basic processor (BP) is in either the masteror master-protected mode. If the BP attempts to executean I/o instruction when it is in the slave mode (bit 8 ofthe current PSW is a 1), the instructi on is aborted at thetiml'> thl'> nnl'>rntinn c-nrll'> is rlpc-nrlprl nnrl thp RP trnns to 10-. - - - - - - - - 1- - - -- - - - - - - - - - - - - - - Ication X1401. Programs operating in the slave mode mustrequest I/O services from the System Monitor.At the end of every I/O instruction, the condition codebits represent a summary descri pti on of the resu I ts of theI/O operation and conditions within the addressed I/Osubsystem. Specific condition code settings and meanings(unique for each I/O instruction) are contained in the detaileddescription for each I/O instruction.All I/O instructions, except RIO, may request detailedI/O status information. The type and amount of I/o statusinformation that may be requested is determined by the operationcode and the R field of the I/O instruction. TheR field also designates which general register(s) is to beloaded with the requested information. (Refer to I/o StatusInformati on for further detai Is. )I/O instructions are similar to other word-addressing instructionsin that bits 15-31 may be modified by indirectaddressing and/or indexing. However, the final value ofthese bits is not used as an effective virtual address formemory reference. Instead, depending upon the I/o instruction,these bits are used as an extension to the operationcode field, as an I/O address to select a particularI/o subsystem, or they may be reserved. Further detai Isof I/o instructions are illustrated in Figure 13 and describedin Table 13.Device Status Byte. These eight bits (0-7) when loadedinto the specified general register provide status informationpertaining to the addressed device and device controller orlOP. The significance of each bit when requested by anSIO, TIO, and HIO instruction is described in Table 15.The significance of these bits when requested by a TDY instructionis different and is described in the applicableperipheral device reference manual.Operational Status Byte. Bits 8-15 of the specified generalregister (R or Ru1) indicate either the presence (1) orabsence (0) of various errors which may have occurredduring an I/O operation. The significance of the individualbits within the operational status byte are describedin Table 16.Table 17 is the summary description of the Device StatusByte and the Operational Status Byte.Byte Count. Bits 16-31 of register Ru1 indicate the numberof bytes that have to be transmitted to or from memoryin the operation called for by the current I/o commanddoubleword.RIO INSTRUCTIONNo status information is returned to the general registersfor an RIO instruction (the R field is ignored). Only conditioncode bits (CC 1 - CC3) are set to reflect the I/Oconditions.Input/Output Instructions 127
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
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CC1 is unchanged by the instruction
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Condition code settings:2 3 4 Resul
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Example 2, odd R field value:Before
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significance (FS), floating zero (F
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next sequential register after regi
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R 1 R2 R3 MeaningoThe effective vir
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MIMULTIPLY IMMEDIATE(Immediate oper
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original contents of register R, re
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Instruction NameCompare HalfwordMne
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99 and 100: again present, unti I a positive or
Page 101 and 102: The new contents of register 7 are:
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
Page 109 and 110: appropriate memory stack locations
Page 111 and 112: II, EI) are generated by II ORing"
Page 113 and 114: In the real extended addressing mod
Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
Page 117 and 118: The XPSD instruction' is used for t
Page 119 and 120: If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131: SET ALARM INDICATORThe following co
Page 135 and 136: Table 13.Description of I/o Instruc
Page 137 and 138: Table 15.Device Status Byte (Regist
Page 139 and 140: Table 16. Operational Status Byte (
Page 141 and 142: Table 19.Status Response Bits for A
Page 143 and 144: If CC4 = 0, the MIOP is in a normal
Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
Page 147 and 148: The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
Page 151 and 152: Interrupt at Channel End (Bit Posit
Page 153 and 154: Transfer in Channel. A control lOCO
Page 155 and 156: Otherwise, the first word of the ne
Page 157 and 158: Depending upon the characteristics
Page 159 and 160: change the rate on the primary cons
Page 161 and 162: Location(hex) (dec)20 3221 3322 342
Page 163 and 164: Table 22.Diagnostic Control (P-Mode
Page 165 and 166: at its normal rate (e. g., fixed du
Page 167 and 168: SET LOW CLOCK MARGINSThis command c
Page 169 and 170: BP STATUS AND NO.Th i s group of i
Page 171 and 172: Input5MPri ntout5MFunctionStore X 1
Page 173 and 174: 6. SYSTEM CONFIGURATION CONTROLPool
Page 175 and 176: Table 25. Functions of Processor Cl
Page 177: Table 26. Functions of Memory Unit
Page 180 and 181: STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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