1. xerox 560 computer system - The UK Mirror Service

memory control feature, CC2 and CC4 are bothset to 1 IS; if bit 9 of XPSD is a 1, the instructionaddress of the new program status words is incrementedby 5.2. CALL instructions - the following additional functionsare performed when XPSD is being executed as a resultof a trap to location X'48', X'49' i X'4A', orX'4B'.a. The R field of the CA LL instruction causing thetrap is logica"y inclusively ORed into bit positions0-3 (CC) of the new PSWs.b. If bit position 9 of XPSD contains a 1, the R fieldof the CALL instruction causing the trap is addedto the instruction address portion of the new PSWs.3. Watchdog timer, parity error, or instruction exceptiontrap - the following additional functions are performedwhen XPSD is being executed a~ a result of a trap tolocation X'46', X'4C', or X'4D', respectively.a. The contents of TCC 1-4 are logically inclusivelyORed into bit positions 0-3 (CC) of the new PSWs.b. If bit position 9 of XPSD contains a 1, the contentsof TCC 1-4 are added to the instruction addressportion of the new PSWs.If bit position 9 of XPSD contains a 0, the instruction addressportion of the new PSWs always remains at the valueestablished by the second effective doubleword. Bit position9 of XPSD is effective only if the instruction is beingexecuted as the result of a nonallowed operation, CALLinstruction watchdog timer, parity error, or instruction exceptiontrap. Bit position 9 of XPSD must be coded with ao in all other cases; otherwise, the results of the XPSDinstruction are undefined.2. Bits 0-35, 60, and 61 of the current program statuswords are unconditionally replaced by bits 0-35, 60,and610f the secondeffectivedoubleword. The affectedportions of the program status words are:BitPosition Designation Function0-3 CC Condition code4-7 FR,FS,FZ, Floating controlFN8 MS Master/slave mode control9 MM Mapping mode control10 DM Decimal arithmetic trap mask11 AM Fixed-point arithmetic trap mask15-31 IA Instruction address (real or virtual)32-35 WK Write key60 RA Register altered61 MA Mode altered3. A logical inclusive OR is performed between bits 37through 39 of the current program status words andbits 37 through 390f the second effective doubleword.BitPosition Designation Function37 CI Counter interrupt inhibit38 II I/O interrupt inhibit39 EI External interrupt inhibitThe current program status words are stored in the doubl e­word location pointed to by the effective address of XPSDin the following form:Program Status WordsIf any (or all) of bits 37, 38, or 39 of the second effectivedoubleword are O's, the corresponding bits inthe current program status words remain unchanged; ifany (or all) of bits 37, 38, or 39 of the second effectivedoubl eword are 1 IS, the corresponding bits in thecurrent program status words are set to 1 'so See "InterruptSystem", Chapter 2, for a detailed discussionof the interrupt inhibits.The current program status WOrds (as iI hjs~ra~ed above) arE:replaced by new program status words as described below.1. The effective address of XPSD is incremented by 2 sothat it points to the next doubleword location. Thecontents of the next doubl eword location are referredto as the second effective doubleword, or ED2.4. If bit position 8 (LP) of XPSD contains a 1, bits 58and 59 (register pointer) of the current program statuswords are replaced by bits 58 and 59 of the secondeffective doubieword; if bit 8 of XPSD is a 0, the currentregister pointer value remains unchanged.Affected: (EDL), (PSWs)If (1)10 = 1, trap or interrupt instructions only, effectiveaddress is subject to current active addressing mode.112 Control Instructions