1. xerox 560 computer system - The UK Mirror Service

appropriate memory stack locations as specified by theTSAi however, subsequent values of the Space Count areindeterminate.PSSPUSH STATUS(Doubleword index alignment, privi leged)During a PLS instruction, the Space Count is incrementedby 1 for each word pulled from the memory stack. If theSpace Count is incremented beyond a value of 32,767, bitposition 32 is set to 1 (signifying an overflow condition);however, the PLS instruction continues (i. e., no trappingoccurs).!xlaDNote: Once bit position 32 has been set to a 1, it can bereset to a 0 only by executing a Mode 0, WRITEDIRECT instruction. That is, bit position 32 cannot be reset to a 0 by the decrementing process performedduring a PSS instruction.WORD COUNTThe Word Count field (bit positions 49-63) of the StatusStack Pointer Doubleword is a lS-bit counter that may containa value of 0 through 32,767. Depending upon programmingconsiderations, the initial Word Count is aspecific value either as the result of executing a Mode 0,WRITE DIRECT instruction or as the result of executing aPSS or PLS instruction.During a PSS instruction, the Word Count is incrementedLy 1 [V 1- ~uch yvvi"d pu~hcd il.tv th~ iii\:i;;Gr'j ~t~~k. Th~~,the terminal Word Count for a PSS instruction exceeds theinitial Word Count by 28. If the Word Count valueexceeds 32,767, bit position 48 is set to a 1 (signifyingthat an overflow condition has occurred); however, thePSS instruction continues the stacking operation (i. e., notrapping occurs).If the initial Word Count for a PLS instruction is equal toor greater than 28, the Word Count is decremented by 1 foreach word pulled from the memory stack and the terminalWord Count will be 28 less than the initial Word Count.Note that if bit position 48 was set to a 1 by a PSS instructionpreviously, it can not be reset to a 0 by the decrementingperformed during a PLS instruction.PUSH STATUS loads new Program Status Words from an effectivedoubleword location and stores the current environment(current Program Status Words and contents of all16 general registers) into a memory stack, as defined by theStatus Stack Pointer Doubleword. Note that the referen~eaddress points to the memory location of the new PSWs.The PSS instruction is used for three types of operations:as a normal instruction in an ongoing program; as an interruptinstruction; and as a trap instruction. The effectiveaddress of a PSS instruction is generated in one of thefollowing ways:PSS - normal instruction (see first instruction diagram)When a PSS instruction is encountered in the course ofexecution of normal programs, the effective address isgenerated according to the rules for addressing then ineffect as described by the currently active PSWs; that is, thebasic processor is operating in real, real extended, or virtualaddressing mode. The flags in bit positions 9 and 10 haveno effect and must be coded as zeros.PSS - interrupt instruction (see second instruction diagram)A PSS instruction (in an interrupt location) executed as aresult of an interrupt is called an interrupt instruction. Inthe interrupt execution sequence, the 20-bit referenceaddress is always real, independent of the map invokingbit in the PSWs. There is no indexing possible since thedesi gnator fi e ld is preempted by the reference address.Indirect addressing is permitted with precisely the sameconstraints. The indirect address word contains a 20-bitreal address with the same properties as the reference addressdescribed above. The flags in bit positions 9 and 10have no effect and must be coded as zeros.If the initial Word Count for a PLS instruction is equal tozero, the parameters within the Status Stack Pointer Doublewordare neither effective nor affected by the PLS instruction.However, default PSWs are loaded from real memorylocations 2 and 3.If the initial Word Count for a PLS instruction is less than 28and not equal to zero, the other parameters of the StatusStack Pointer Doubleword are not effective and none of theparameters are affected by the PLS instruction. Instead theBP traps to location X'4D ' (instruction exception trap) andTCC2 is set.PSS - trap instruction (see second instruction diagram)A PSS instruction (in a trap location) executed as a resu Itof a trap entry operation is called a trap instruction. In atrap execution sequence, the 20-bit reference address may beeither a real address or a virtual address according to themap invoking bit in the PSWs. There is no indexing possiblesince the index field is used for addressing. If indirectaddressing is specified, the effective address is generatedaccording to the rules for addressing then in effect as describedby the currently active PSWs. Bit positions 9 and 10must be coded as zeros.Push-Down Instructions (Privileged) 103