Section 4. Program Memory - Microchip Taiwan

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dsPIC33E/PIC24E Family Reference Manual4.2 CONTROL REGISTERSRegister 4-1:TBLPAG: Table Page RegisterU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0TBLPAGbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-8 Unimplemented: Read as ‘0’bit 7-0 TBLPAG: Table Address Page bitsThe 8-bit Table Address Page bits are concatenated with the W register to form a 23-bit effectiveprogram memory address plus a Byte Select bit.Register 4-2: DSRPAG: Data Space Read Page Register (1,2)U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — DSRPAGbit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1DSRPAGbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-10 Unimplemented: Read as ‘0’bit 9-0 DSRPAG: Data Space Read Page Pointer bitsNote 1: When DSRPAG = 0x000, attempts to read from the paged DS window will cause an address error trap.2: DSRPAG is reset to 0x001.DS70613B-page 4-4© 2010 Microchip Technology Inc.
Section 4. Program Memory4.3 PROGRAM COUNTERThe PC increments by two with the Least Significant bit (LSb) set to ‘0’ to provide compatibilitywith data space addressing. Sequential instruction words are addressed in the 4M programmemory space by PC. Each instruction word is 24 bits wide.The LSb of the program memory address (PC) is reserved as a Byte Select bit for programmemory accesses from data space, that use Program Space Visibility (PSV) or table instructions.For instruction fetches via the PC, the Byte Select bit is not required, so PC is always set to‘0’. For more information on the PSV mode of operation, see 4.5 “Program Space Visibilityfrom Data Space”.Figure 4-2 illustrates an instruction fetch example. Note that incrementing PC by ‘1’ isequivalent to adding 2 to PC.Figure 4-2:Instruction Fetch Example24 bits23 User+1 (1)Space23Instruction0x00000024InstructionLatchProgram Counter 022 00x7FFFFENote 1:An increment of ‘1’ to PC is equivalent to PC+2.4Program Memory© 2010 Microchip Technology Inc. DS70613B-page 4-5
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