Section 4. Program Memory - Microchip Taiwan

dsPIC33E/PIC24E Family Reference Manual4.5 PROGRAM SPACE VISIBILITY FROM DATA SPACEThe upper 32 Kbytes of the dsPIC33E/PIC24E data memory address space can optionally bemapped into any 16K word program space page. The PSV mode of operation providestransparent access of stored constant data from X data space without the need to use specialinstructions (i.e., TBLRD, TBLWT instructions).4.5.1 PSV ConfigurationThe dsPIC33E/PIC24E core extends the available data space through a paging scheme to makeit appear linear for pre- and post-modified effective addresses.The upper half of the base data space address (0x8000 to 0xFFFF) is used with the 10-bit DataSpace Read Page register (DSRPAG) to form a PSV address, and can address 8 Mbytes of PSVaddress space.The paged memory scheme provides access to multiple 32-Kbyte windows in the PSV memory.The PSV in the paged data memory space is illustrated in Figure 4-8.Program space (PS) can be read with a DSRPAG register of 0x200 or greater.Reads from PS are supported using the DSRPAG register. Writes to PS are not supported;therefore, the Data Space Write Page register (DSWPAG) is dedicated exclusively to data space(DS), including extended data space (EDS).For more information on the paged memory scheme refer to Section 3. “Data Memory”(DS70595).Note:The DSRPAG register can be written using the MOVPAG #lit10, DSRPAG instructionor the MOVPAG Wn, DSRPAG instruction. Refer to the “16-bit MCU and DSCProgrammer’s Reference Manual” (DS70157) for details.DS70613B-page 4-12© 2010 Microchip Technology Inc.