TDA8358J Full bridge vertical deflection output circuit in ... - Laro

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JCHARACTERISTICSV P = 12 V; V FB = 45 V; f vert = 50 Hz; V I(bias) = 880 mV; T amb =25°C; measured in test circuit of Fig.3; unless otherwisespecified.SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITSuppliesV P operating supply voltage 7.5 12 18 VV FB flyback supply voltage note 1 2 × V P 45 66 VI q(P)(av) average quiescent supply current during scan − 10 15 mAI q(P) quiescent supply current no signal; no load − 45 75 mAI q(FB)(av) average quiescent flyback supply during scan − − 10 mAcurrentInputs A and BV i(p-p) input voltage (peak-to-peak value) note 2 − 1000 1500 mVV I(bias) input bias voltage note 2 100 880 1600 mVI I(bias) input bias current − 25 35 µAOutputs A and BV loss(1) voltage loss first scan part note 3I o = 1.1 A − − 4.5 VI o = 1.6 A − − 6.6 VV loss(2) voltage loss second scan part note 4I o = −1.1 A − − 3.3 VI o = −1.6 A − − 4.8 VI o(p-p) output current− − 3.2 A(peak-to-peak value)LE linearity error I o(p-p) = 3.2 A; notes 5 and 6adjacent blocks − 1 2 %non-adjacent blocks − 1 3 %V offset offset voltage across R M ; V i(dif) =0VV I(bias) = 200 mV − − ±15 mVV I(bias) =1V − − ±20 mV∆V offset(T)offset voltage variation with across R M ; V i(dif) =0V − − 40 µV/KtemperatureV O DC output voltage V i(dif) =0V − 0.5 × V P − VG v(ol) open-loop voltage gain notes 7 and 8 − 60 − dBf −3dB(h) high −3 dB cut-off frequency open-loop − 1 − kHzG v voltage gain note 9 − 1 −∆G v(T)voltage gain variation withtemperature− − 10 −4 K −1PSRR power supply rejection ratio note 10 80 90 − dB2002 Sep 25 7