TDA8358J Full bridge vertical deflection output circuit in ... - Laro

INTEGRATED CIRCUITSDATA SHEETTDA8358JFull bridge vertical deflection outputcircuit in LVDMOS with east-westamplifierProduct specificationSupersedes data of 1999 Dec 222002 Sep 25

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JFEATURES• Few external components required• High efficiency fully DC-coupled vertical bridge outputcircuit• Vertical flyback switch with short rise and fall times• Built-in guard circuit• Thermal protection circuit• Improved EMC performance due to differential inputs• East-west output stage.GENERAL DESCRIPTIONThe TDA8358J is a power circuit for use in 90° and 110°colour deflection systems for 25 to 200 Hz fieldfrequencies, and for 4 : 3 and 16 : 9 picture tubes. The ICcontains a vertical deflection output circuit, operating as ahigh efficiency class G system. The full bridge outputcircuit allows DC coupling of the deflection coil incombination with single positive supply voltages.The east-west output stage is able to supply the sinkcurrent for a diode modulator circuit.The IC is constructed in a Low Voltage DMOS (LVDMOS)process that combines bipolar, CMOS and DMOSdevices. DMOS transistors are used in the output stagebecause of absence of second breakdown.QUICK REFERENCE DATASYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITSuppliesV P supply voltage 7.5 12 18 VV FB flyback supply voltage 2 × V P 45 66 VI q(P)(av) average quiescent supply current during scan − 10 15 mAI q(FB)(av) average quiescent flyback supply current during scan − − 10 mAP tot total power dissipation − − 15 WInputs and outputsV i(p-p) input voltage (peak-to-peak value) − 1000 1500 mVI o(p-p) output current (peak-to-peak value) − − 3.2 AFlyback switchI o(peak) maximum (peak) output current t ≤ 1.5 ms − − ±1.8 AEast-west amplifierV o output voltage − − 68 VV I(bias) input bias voltage 2 − 3.2 VI o output current − − 750 mAThermal data; in accordance with IEC 747-1T stg storage temperature −55 − +150 °CT amb ambient temperature −25 − +85 °CT j junction temperature − − +150 °C2002 Sep 25 2

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JPINNINGSYMBOL PIN DESCRIPTIONINA 1 positive vertical inputINB 2 negative vertical inputV P 3 supply voltageOUTB 4 vertical output voltage BINEW 5 east-west input voltageVGND 6 vertical groundEWGND 7 east-west groundOUTEW 8 east-west output voltageV FB 9 flyback supply voltageOUTA 10 vertical output voltage AGUARD 11 guard output voltageFEEDB 12 input measuring resistorCOMP 13 input compensation currenthandbook, halfpageINAINBV POUTBINEWVGNDEWGNDOUTEWV FBOUTAGUARDFEEDBCOMP12345678910111213TDA8358JMGL867The die has been glued to the metal block of the package. If the metalblock is not insulated from the heatsink, the heatsink shall only beconnected directly to pin VGND.FUNCTIONAL DESCRIPTIONVertical output stageThe vertical driver circuit has a bridge configuration. Thedeflection coil is connected between the complimentarydriven output amplifiers. The differential input circuit isvoltage driven. The input circuit is specially designed fordirect connection to driver circuits delivering a differentialsignal but it is also suitable for single-ended applications.For processors with output currents, the currents areconverted to voltages by the conversion resistorsR CV1 and R CV2 (see Fig.3) connected to pins INAand INB. The differential input voltage is compared withthe voltage across the measuring resistor R M , thusproviding feedback information. The voltage across R M isproportional with the output current. The relationshipbetween the differential input voltage and the outputcurrent is defined by:V i(dif)(p-p) = I o(p-p) × R M ; V i(dif)(p-p) = V INA − V INBThe output current should not exceed 3.2 A (p-p) and isdetermined by the value of R M and R CV . The allowableinput voltage range is 100 mV to 1.6 V for each input. Theformula given does not include internal bondwireresistances. Depending on the value of R M and the internalbondwire resistance (typical value 50 mΩ) the actual valueof the current in the deflection coil will be about 5% lowerthan calculated.Flyback supplyThe flyback voltage is determined by the flyback supplyvoltage V FB . The principle of two supply voltages (class G)allows to use an optimum supply voltage V P for scan andan optimum flyback supply voltage V FB for flyback, thusvery high efficiency is achieved. The available flybackoutput voltage across the coil is almost equal to V FB , dueto the absence of a coupling capacitor which is notrequired in a bridge configuration. The very short rise andfall times of the flyback switch are determined mainly bythe slew rate value of more than 300 V/µs.ProtectionThe output circuit contains protection circuits for:• Too high die temperature• Overvoltage of output A.Fig.2 Pin configuration.2002 Sep 25 4

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JGuard circuitA guard circuit with output pin GUARD is provided.The guard circuit generates a HIGH-level during theflyback period. The guard circuit is also activated for oneof the following conditions:• During thermal protection (T j ≈ 170 °C)• During an open-loop condition.The guard signal can be used for blanking the picture tubeand signalling fault conditions. The verticalsynchronization pulses of the guard signal can be used byan On Screen Display (OSD) microcontroller.Damping resistor compensationHF loop stability is achieved by connecting a dampingresistor R D1 (see Fig.4) across the deflection coil. Thecurrent values in R D1 during scan and flyback aresignificantly different. Both the resistor current and thedeflection coil current flow into measuring resistor R M ,resulting in a too low deflection coil current at the start ofthe scan.The difference in the damping resistor current valuesduring scan and flyback have to be externallycompensated in order to achieve a short settling time.For that purpose a compensation resistor R CMP isconnected between pins OUTA and COMP. The value ofR CMP is calculated by:( VR FB – V loss( FB)– V P ) × R D1 ×( R S + 300)CMP = -------------------------------------------------------------------------------------------------------------( V FB– V loss( FB)– I coil( peak)× R coil) × R Mwhere:• R coil is the coil resistance• V loss(FB) is the voltage loss between pins V FB and OUTAat flyback.East-west amplifierThe east-west amplifier is current driven. The output canonly sink currents of the diode modulator circuit.A feedback resistor (see Fig.4) has to be connectedbetween the input and output of the inverting east-westamplifier in order to convert the east-west correction inputcurrent into an output voltage. The output voltage of theeast-west circuit at pin OUTEW is given by:V OUTEW ≈ I INEW × R EWF +V INEWThe maximum output voltage is V o(max) = 68 V, while themaximum output current of the circuit is I o(max) = 750 mA.2002 Sep 25 5

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITV P supply voltage − 18 VV FB flyback supply voltage − 68 V∆V VGND-EWGNDvoltage difference between− 0.3 Vpins VGND and EWGNDV nDC voltagepins OUTA and OUTEW note 1 − 68 Vpin OUTB − V P Vpins INA, INB, INEW, GUARD,−0.5 V P VFEEDB, and COMPI nDC currentpins OUTA and OUTB during scan (p-p) − 3.2 Apins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms − ±1.8 Apins INA, INB, INEW, GUARD,−20 +20 mAFEEDB, and COMPpin OUTEW − 750 mAI lu latch-up current input current into any pin;− +200 mApin voltage is 1.5 × V P ; T j = 150 °Cinput current out of any pin; −200 − mApin voltage is −1.5 × V P ; T j = 150 °CV es electrostatic handling voltage machine model; note 2 −350 +350 Vhuman body model; note 3 −4000 +4000 VP EW east-west power dissipation note 4 − 4 WP tot total power dissipation − 15 WT stg storage temperature −55 +150 °CT amb ambient temperature −25 +85 °CT j junction temperature note 5 − +150 °CNotes1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.2. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.3. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.4. For repetitive time durations of t < 0.1 ms or a non-repetitive time duration of t

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JCHARACTERISTICSV P = 12 V; V FB = 45 V; f vert = 50 Hz; V I(bias) = 880 mV; T amb =25°C; measured in test circuit of Fig.3; unless otherwisespecified.SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITSuppliesV P operating supply voltage 7.5 12 18 VV FB flyback supply voltage note 1 2 × V P 45 66 VI q(P)(av) average quiescent supply current during scan − 10 15 mAI q(P) quiescent supply current no signal; no load − 45 75 mAI q(FB)(av) average quiescent flyback supply during scan − − 10 mAcurrentInputs A and BV i(p-p) input voltage (peak-to-peak value) note 2 − 1000 1500 mVV I(bias) input bias voltage note 2 100 880 1600 mVI I(bias) input bias current − 25 35 µAOutputs A and BV loss(1) voltage loss first scan part note 3I o = 1.1 A − − 4.5 VI o = 1.6 A − − 6.6 VV loss(2) voltage loss second scan part note 4I o = −1.1 A − − 3.3 VI o = −1.6 A − − 4.8 VI o(p-p) output current− − 3.2 A(peak-to-peak value)LE linearity error I o(p-p) = 3.2 A; notes 5 and 6adjacent blocks − 1 2 %non-adjacent blocks − 1 3 %V offset offset voltage across R M ; V i(dif) =0VV I(bias) = 200 mV − − ±15 mVV I(bias) =1V − − ±20 mV∆V offset(T)offset voltage variation with across R M ; V i(dif) =0V − − 40 µV/KtemperatureV O DC output voltage V i(dif) =0V − 0.5 × V P − VG v(ol) open-loop voltage gain notes 7 and 8 − 60 − dBf −3dB(h) high −3 dB cut-off frequency open-loop − 1 − kHzG v voltage gain note 9 − 1 −∆G v(T)voltage gain variation withtemperature− − 10 −4 K −1PSRR power supply rejection ratio note 10 80 90 − dB2002 Sep 25 7

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JSYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITFlyback switchI o(peak) maximum (peak) output current t ≤ 1.5 ms − − ±1.8 AV loss(FB) voltage loss at flyback note 11I o = 1.1 A − 7.5 8.5 VI o = 1.6 A − 8 9 VGuard circuitV O(grd) guard output voltage I O(grd) = 100 µA 5 6 7 VV O(grd)(max) allowable guard voltage maximum leakage current − − 18 VI L(max) =10µAI O(grd) output current V O(grd) = 0 V; not active − − 10 µAV O(grd) = 4.5 V; active 1 − 2.5 mAEast-west amplifierV o output voltage at pin OUTEW − − 68 VV loss voltage loss I o = 750 mA; note 12 − − 5 VV I(bias) input bias voltage 2 2.5 3.2 VI I(bias) input bias current into pin INEW; note 13I o = 100 mA − 2.5 − µAI o = 500 mA − 11.5 − µAG v(ol) open-loop voltage gain − 30 − dBTHD harmonic distortion − 0.5 1 %f −3dB(h) high −3 dB cut-off frequency − − 1 MHz2002 Sep 25 8

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JNotes1. To limit V OUTA to 68 V, V FB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTAand V FB at the first part of the flyback.2. Allowable input range for both inputs: V I(bias) +V i < 1600 mV and V I(bias) − V i > 100 mV.3. This value specifies the sum of the voltage losses of the internal current paths between pins V P and OUTA, andbetween pins OUTB and GND. Specified for T j = 125 °C. The temperature coefficient for V loss(1) is a positive value.4. This value specifies the sum of the voltage losses of the internal current paths between pins V P and OUTB, andbetween pins OUTA and GND. Specified for T j = 125 °C. The temperature coefficient for V loss(2) is a positive value.5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal timeparts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consistsof two successive parts. The voltage amplitudes are measured across R M , starting at k = 1 and ending at k = 10,where V k and V k+1 are the measured voltages of two successive blocks. V min , V max and V avg are the minimum,maximum and average voltages respectively. The linearity errors are defined as:a) LE =V k – V k + 1------------------------- × 100% (adjacent blocks)V max – V minb) LE = ------------------------------ × 100% (non adjacent blocks)6. The linearity errors are specified for a minimum input voltage at pin 1 or pin 2 of 300 mV. Lower input voltages leadto voltage dependent S-distortion in the input stage.7.8. Pin FEEDB not connected.9.G volV avgV avgV OUTA – V OUTB( ) = -------------------------------------------–V FEEDBV OUTBVG FEEDB – V OUTBV= -------------------------------------------–V INAV INB10. V P(ripple) = 500 mV (RMS value); 50 Hz < f P(ripple) < 1 kHz; measured across R M .11. This value specifies the internal voltage loss of the current path between pins V FB and OUTA.12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.13. Measured for R EWF =10kΩ; R EWL =30Ω; V o =6V.a) For I o = 100 mA and a voltage of 9 V at R EWL connected to the line output transformer, the east-west amplifierinput current (see Fig.4) is I i = 300 µA.b) For I o = 500 mA and a voltage of 21 V at R EWL connected to the line output transformer, the east-west amplifierinput current (see Fig.4) is I i = 350 µA.2002 Sep 25 9

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JAPPLICATION INFORMATIONhandbook, full pagewidthV i(p-p)V I(bias)0I I(bias)I i(dif)I I(bias)V i(p-p)V I(bias)0R GRD4.7 kΩV P V FB11 9I iCOMP GUARD133I i INEW 5M6 8 OUTEWCOMP. GUARDCIRCUIT CIRCUITM5D2D3M2D1INA 110 OUTAR CV1M42.2 kΩ(1%)INPUT12 FEEDBANDFEEDBACKCIRCUITINB 2M1R CV24 OUTB2.2 kΩ(1%)M3TDA8358JC1100 nFR S2.7 kΩC M10 nFV PV FBC2100 nFR L3.2 ΩR M0.5 ΩI I(av)0I i(p-p)R EWF10 kΩVGND67EWGNDR EWL30 ΩMGL873Fig.3 Test diagram.2002 Sep 25 10

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here inwhite to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...2002 Sep 25 11V I(bias)0TV SIGNALPROCESSORV I(bias)0I I(av)0V i(p-p)V i(p-p)I i(p-p)C52.2 nFC62.2 nFR GRD12 kΩdbook, full pagewidthP V FB9COMP GUARD V1311 3C3 C1I i 6712 Ω100 47 µFCOMP. GUARDnF (100 V)CIRCUIT CIRCUITM5D2D3M2R CMPINA 1500 kΩD110 OUTAM4R D1270 ΩRINPUT12 FEEDB SANDFEEDBACK2.7 kΩINB 2 CIRCUITM14 OUTBM3TDA8358JINEW 5M6 8 OUTEW to line outputR EWLtransformerR CV12.2 kΩR CV22.2 kΩf vert = 50 Hz; t FB = 640 µs; I I(bias) = 400 µA; I i(p-p) = 475 µA; I o(p-p) = 2.4 A.R EWF82 kΩVGNDFig.4 Application diagram.EWGNDMGL874C4100 nFdeflectioncoil5 mH6 ΩW66ESFR M0.87 ΩV P = 14 VV FB = 30 VC2220 µFC D47 nFR D21.5 ΩFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierTDA8358JPhilips Semiconductors Product specification

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JR M calculationBefore calculating the measuring resistor (R M ), thedifferential input voltage [V i(dif) ] has to be known. Thisvoltage can be measured between pins INA and INB. TheVcalculation is as follows: R M= i(dif)(p-p)---------------------I o(p-p)Most of the TV signal processors from Philips have acurrent output. This current has to be converted byresistors at the input of the TDA8358J (R CV1 and R CV2 ).The voltage across these resistors can be calculated. Thedifferential input voltage is given in the following equation(see also Fig 5):V i(dif)(p-p) =I i1(p-p) × R CV1 − [−I i2(p-p) ] × R CV2I I(bias)0TV SIGNALPROCESSORI I(bias)0I i1(p-p)I i2(p-p)C52.2 nFC62.2 nFR CV12.2 kΩR CV22.2 kΩFig.5 Differential input voltage.Values for these currents are, for instance:I i(bias) = 400 µA; I i1(p-p) =I i2(p-p) = 475 µA.Therefore the differential input voltage be as follows:V i(dif)(p-p) = 475 µA × 2.2 kΩ −(−475 µA × 2.2 kΩ)= 2.09 V12MBL520Supply voltage calculationFor calculating the minimum required supply voltage,several specific application parameter values have to beknown. These parameters are the required maximum(peak) deflection coil current I coil(peak) , the coil impedanceR coil and L coil and the measuring resistance of R M . Therequired maximum (peak) deflection coil current shouldalso include the overscan.The deflection coil resistance has to be multiplied by 1.2 inorder to take account of hot conditions.Chapter “Characteristics” supplies values for the voltagelosses of the vertical output stage. For the first part of thescan the voltage loss is given by V loss(1) . For the secondpart of the scan the voltage loss is given by V loss(2) .The voltage drop across the deflection coil during scan isdetermined by the coil impedance. For the first part of thescan the inductive contribution and the ohmic contributionto the total coil voltage drop are of opposite sign, while forthe second part of the scan the inductive part and theohmic part have the same sign.For the vertical frequency the maximum frequencyoccurring must be applied to the calculations.The required power supply voltage V P for the first part ofthe scan is given by:V P1 ( ) I coil( peak)( R coil + R M )– L coil × 2I coil( peak)× f vert( max)+ V loss( 1)The required power supply voltage V P for the second partof the scan is given by:The minimum required supply voltage V P shall be thehighest of the two values V P(1) and V P(2) . Spread in supplyvoltage and component values also has to be taken intoaccount.Flyback supply voltage calculationIf the flyback time is known, the required flyback supplyvoltage can be calculated by the simplified formula:where:=×V P2 ( ) = I coil( peak)×( R coil + R M )+ L coil × 2I coil( peak)× f vert( max)+ V loss( 2)V FB=× R -------------------------- coil + R M( )1 e – t FB–⁄ xI coil p–pL coilR coilR Mx = --------------------------+2002 Sep 25 12

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JThe flyback supply voltage calculated this way isapproximately 5% to 10% higher than required.Calculation of the power dissipation of the verticaloutput stageThe power dissipation of the vertical output stage is givenby the formula:P V =P sup − P LThe power to be supplied is given by the formula:IP sup = V coil( peak)P × ----------------------- + V2 P × 0.015 [A] + 0.3 [W]In this formula 0.3 [W] represents the average value of thelosses in the flyback supply.The average external load power dissipation in thedeflection coil and the measuring resistor is given by theformula:P L( I coil( peak)) 2= ------------------------------- × ( R3coil + R M )ExampleTable 1Table 2Application valuesSYMBOL VALUE UNITI coil(peak) 1.2 AI coil(p-p) 2.4 AL coil 5 mHR coil 6 ΩR M 0.6 Ωf vert 50 Hzt FB 640 µsCalculated valuesSYMBOL VALUE UNITV P 14 VR M +R coil (hot) 7.8 Ωt vert 0.02 sx 0.000641V FB 30 VP sup 8.91 WP L 3.74 WP V 5.17 WPower dissipation calculation for the east-west stageIn general the shape of the east-west output wave form isa parabola. The output voltage will be higher at thebeginning and end of the vertical scan compared to thevoltage at the scan middle, while the output current will behigher at the scan middle. This results in an almost uniformpower dissipation distribution during scan. Therefore thepower dissipation can be calculated by multiplying theaverage values of the output voltage and the outputcurrent of pin OUTEW.When verifying the dissipation the switch-on and switch-offdissipation should also be taken into account. Powerdissipation during start-up can be 3 to 5 times higher thanduring normal operation.Heatsink calculationThe value of the heatsink can be calculated in a standardway with a method based on average temperatures. Therequired thermal resistance of the heatsink is determinedby the maximum die temperature of 150 °C. In general werecommend a design for an average die temperaturenot exceeding 130 °C. It should be noted that theheatsink thermal resistance R th(h-a) found by performing astandard calculation will be lower then normally found fora vertical deflection stand alone device, due to thecontribution of the EW power dissipation to this value.EXAMPLEMeasured or known values:P EW = 3 W; P V = 6 W; T amb =40°C; T j = 130 °C;R th(j-c) = 4 K/W; R th(c-h) = 1 K/W.The required heatsink thermal resistance is given by:T j – T amb( ) = ------------------------ –( R+th( j – c)+ R th c – hR th h – aP EWP VWhen we use the values known we find:130 – 40( ) = --------------------- – (3+64 + 1 ) = 5 K/WR th h – aThe heatsink temperature will be:( ) )T h =T amb +R th(h-a) × P tot =40+5×9=85°C2002 Sep 25 13

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JEquivalent thermal resistance networkThe TDA8358J has two independent power dissipatingsystems, the vertical output circuit and the east-westcircuit.It is recommended to verify the individual maximum (peak)junction temperatures of both circuits. Therefore themaximum (peak) power dissipations of the circuits andalso the heatsink temperature should be measured. Themaximum (peak) junction temperatures can be calculatedby using an equivalent thermal network (see Fig.6).The network only includes the contribution of themaximum (peak) power dissipation P TRv(peak) , being thedissipation of the most critical transistor internallyconnected to pins OUTA and VGND. The model assumesequivalent maximum (peak) power dissipations during thedifferent vertical scan stages for all the functionally pairedtransistors. The calculated maximum (peak) junctiontemperatures should not exceed T j = 150 °C.EXAMPLEMeasured or known values:• The east-west power dissipation: P EW =3W• The vertical power dissipation: P V =6W• The maximum (peak) power dissipation of the mostcritical transistor: P TRv(peak) =5W• The case temperature: T c =85°C.The IC total power dissipation is:P tot =P EW +P V =6+3=9WIt should be noted that the allowed IC total powerdissipation is P tot = 15 W (maximum value).The maximum (peak) temperature T P1(peak) is given by:• T P1(peak) =T c +(P EW +P TRv(peak) ) × R th(P1-c)=85+(3+5)×2.2 = 102.6 °CThe maximum (peak) junction temperatures for the outputcircuits are given by:• T j(EW)(peak) =T P1(peak) +R th(EW-P1) × P EW= 102.6 + 10.5 × 3 = 134.1 °C• T j(TRv)(peak) =T P1(peak) +R th(TRv-P1) × P TRv(peak)= 102.6 + 5.2 × 5 = 128.6 °Chandbook, halfpageT EW(M)T TRv(M)R th(EW-P1)10.5 K/WP EWT P1(M)R th(TRv-P1)5.2 K/WP TRv(M)R th(P1-c)2.2 K/WP totT cMGL872Fig.6 Equivalent thermal resistance network.2002 Sep 25 14

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JINTERNAL PIN CONFIGURATIONPIN SYMBOL EQUIVALENT CIRCUIT1 INA1300 ΩMBL1002 INB2300 ΩMBL1023 V P4 OUTB6 VGND9 V FB10 OUTA93104MGL86965 INEW7 EWGND8 OUTEW300 Ω57MGL86882002 Sep 25 15

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JPIN SYMBOL EQUIVALENT CIRCUIT11 GUARD300 Ω11MGL87012 FEEDB300 Ω12MGL87113 COMP300 Ω13MGL8752002 Sep 25 16

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JPACKAGE OUTLINEDBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)SOT141-6non-concavexDhDE hview B: mounting base sidedA 2BjEAL 3LQcv M1 13Z e1w Mm e2b pe0 5 10 mmscaleDIMENSIONS (mm are the original dimensions)UNIT A A 2 b p c D (1) d D E (1) e e 1Z (1)h e 2 E h j L L 3 m Q v w xmm 17.015.54.64.40.750.600.480.3824.023.620.019.612.210 3.411.81.75.0863.43.112.411.02.41.64.32.11.80.80.250.032.001.45Note1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.OUTLINEVERSIONREFERENCESIEC JEDEC EIAJEUROPEANPROJECTIONISSUE DATESOT141-697-12-1699-12-172002 Sep 25 17

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JSOLDERINGIntroduction to soldering through-hole mountpackagesThis text gives a brief insight to wave, dip and manualsoldering. A more in-depth account of soldering ICs can befound in our “Data Handbook IC26; Integrated CircuitPackages” (document order number 9398 652 90011).Wave soldering is the preferred method for mounting ofthrough-hole mount IC packages on a printed-circuitboard.Soldering by dipping or by solder waveThe maximum permissible temperature of the solder is260 °C; solder at this temperature must not be in contactwith the joints for more than 5 seconds.The total contact time of successive solder waves must notexceed 5 seconds.The device may be mounted up to the seating plane, butthe temperature of the plastic body must not exceed thespecified maximum storage temperature (T stg(max) ). If theprinted-circuit board has been pre-heated, forced coolingmay be necessary immediately after soldering to keep thetemperature within the permissible limit.Manual solderingApply the soldering iron (24 V or less) to the lead(s) of thepackage, either below the seating plane or not more than2 mm above it. If the temperature of the soldering iron bitis less than 300 °C it may remain in contact for up to10 seconds. If the bit temperature is between300 and 400 °C, contact may be up to 5 seconds.Suitability of through-hole mount IC packages for dipping and wave soldering methodsSOLDERING METHODPACKAGEDIPPINGDBS, DIP, HDIP, SDIP, SIL suitable suitable (1)WAVENote1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.2002 Sep 25 18

Philips SemiconductorsFull bridge vertical deflection output circuitin LVDMOS with east-west amplifierProduct specificationTDA8358JDATA SHEET STATUSDATA SHEET STATUS (1) PRODUCTSTATUS (2)DEFINITIONSObjective data Development This data sheet contains data from the objective specification for productdevelopment. Philips Semiconductors reserves the right to change thespecification in any manner without notice.Preliminary data Qualification This data sheet contains data from the preliminary specification.Supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to change the specification withoutnotice, in order to improve the design and supply the best possibleproduct.Product data Production This data sheet contains data from the product specification. PhilipsSemiconductors reserves the right to make changes at any time in orderto improve the design, manufacturing and supply. Changes will becommunicated according to the Customer Product/Process ChangeNotification (CPCN) procedure SNW-SQ-650A.Notes1. Please consult the most recently issued data sheet before initiating or completing a design.2. The product status of the device(s) described in this data sheet may have changed since this data sheet waspublished. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.DEFINITIONSShort-form specification ⎯ The data in a short-formspecification is extracted from a full data sheet with thesame type number and title. For detailed information seethe relevant data sheet or data handbook.Limiting values definition ⎯ Limiting values given are inaccordance with the Absolute Maximum Rating System(IEC 60134). Stress above one or more of the limitingvalues may cause permanent damage to the device.These are stress ratings only and operation of the deviceat these or at any other conditions above those given in theCharacteristics sections of the specification is not implied.Exposure to limiting values for extended periods mayaffect device reliability.Application information ⎯ Applications that aredescribed herein for any of these products are forillustrative purposes only. Philips Semiconductors makeno representation or warranty that such applications will besuitable for the specified use without further testing ormodification.DISCLAIMERSLife support applications ⎯ These products are notdesigned for use in life support appliances, devices, orsystems where malfunction of these products canreasonably be expected to result in personal injury. PhilipsSemiconductors customers using or selling these productsfor use in such applications do so at their own risk andagree to fully indemnify Philips Semiconductors for anydamages resulting from such application.Right to make changes ⎯ Philips Semiconductorsreserves the right to make changes, without notice, in theproducts, including circuits, standard cells, and/orsoftware, described or contained herein in order toimprove design and/or performance. PhilipsSemiconductors assumes no responsibility or liability forthe use of any of these products, conveys no licence or titleunder any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties thatthese products are free from patent, copyright, or maskwork right infringement, unless otherwise specified.2002 Sep 25 19

Philips Semiconductors – a worldwide companyContact informationFor additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.© Koninklijke Philips Electronics N.V. 2002 SCA74All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.Printed in The Netherlands 753504/02/pp20 Date of release: 2002 Sep 25 Document order number: 9397 750 09635