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adVanCed paCkaging Single WaFeR Wet pRoCeSSingtSV ReSiSt StRip and CleanSolid State Equipment LLCadvanced packagingS ingL e W a F e RW e T p ROceSSingAs received – post DRIE After SSEC Cleaning As received – post DRIE After SSEC Cleaning As received – post DRIE After SSEC CleaningSi etCh to ReVeal Cu tSVdRy Film StRipOptical SEM ISIS 3DFlux CleaninguBm and Rdl metal etChUndercut vs Etch TimeUndercut (µ)1.7µ1.5µ0µ(non-measurable)WaferChek +15 sec +30 secOver-etch Over-etchEtch TimeUBM Post EtchUBM Post Strip2Chip Scale Review March/April 2012 [ChipScaleReview.com]ssecusa.com© 2012 Solid State equipment llC

Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]3

educe soft errorsDeliver more density on your IC packages withoutsoft errors.Honeywell RadLo low alpha packaging materials help eliminate softerrors and single event upsets by reducing alpha emissions, a significantsource of these problems. This is becoming increasingly importantas chip dimensions and designs continue to miniaturize. Our leadershipand expertise in low alpha refining and metrology mean that Honeywell can help you meet criticalalpha emission levels.Honeywell reliability. Reliable low alpha. Make sure to ask your suppliers if they are usingHoneywell RadLo low alpha materials for their chip packaging processes.Find out more by visiting us at www.honeywell-radlo.comAlthough all statements and information contained herein are believed to be accurate and reliable, they are presented without guarantee or warranty of any kind, express or implied. Information provided herein does not relievethe user from the responsibility of carrying out its own tests and experiments, and the user assumes all risks and liability for use of the information and results obtained. Statements or suggestions concerning the use of materialsand processes are made without representation or warranty that any such use is free of patent infringement and are not recommendations to infringe any patent. The user should not assume that all toxicity data and safetymeasures4are indicatedChip Scaleherein orReviewthat other measuresJan/Febmay2013not be[ChipScaleReview.com]required. ©2012 Honeywell International Inc. All rights reserved.

CONTENTSFEATURE ARTICLESPackage-Level Circuit Modifications Using Plasma-FIB to Create Functional PrototypesPeter Carleson, Brian Routh Jr., Trevan Landin, Kenny Mani, FEI CompanyFunctional Testing of 0.3mm-pitch Wafer-Level Packages to Multi-GHz SpeedIla Pal, Ironwood Electronics4448DEPARTMENTSFrom the PublisherKim Newman, Chip Scale ReviewMarket Trends Global Economy Drives the IC Industry’s CycleBill McClean, IC Insights, Inc.Guest Editorial Requirements: Aren’t They Obvious?David Barnum, Sensata TechnologiesMEMS Guest Editorial Robust Process Solutions for MEMS Flip-Chip Applications With Medium Density Lead-FreeSolder InterconnectsDave DiPaola, DiPaola ConsultingIndustry NewsChip Scale Review StaffInterview Growing Up in Tough TimesChip Scale Review StaffProduct NewsChip Scale Review StaffAdvertiser Index, Advertising Sales68131519505256CONTACT-LESSVORTEXWANDPICKS FROM BOTHSIDES OF WAFER.PICKS INTERLEAF TOO!* For 6”~12”, 50 µm thin to standard wafers; warped, bumped or perforated* Compatible with standard cassette, FOUP & horizontal shipping box* Side supporting rails maintain stability and permit safe wafer flippingFor datasheet, please contact info@wafer-handling.com | Also visit www.wafer-handling.comto see our complete line of products for wafer handling automationP +1.408.200.8345 | F +1.408.200.8341 | 2343 Bering Drive, San Jose, CA 95131, USAWAFER-HANDLINGCOMa Division of Quartet Mechanics Inc.Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]5

Volume 17, Number 1The International Magazine for Device and Wafer-levelTest, Assembly, and Packaging AddressingHigh-density Interconnection of Microelectronic IC'sincluding 3D packages, MEMS, MOEMS,RF/Wireless, Optoelectronic and OtherWafer-fabricated Devices for the 21st Century.STAFFKim Newman Publisherknewman@chipscalereview.comLawrence Michaels Managing Directorlxm@chipscalereview.comDebra Vogler Senior Technical Editordvogler@chipscalereview.comDr. Thomas Di Stefano Contributing Editortom@centipedesystems.comJason Mirabito Contributing Legal Editormirabito@mintz.comPaul M. Sakamoto Contributing Editor Testpaul.sakamoto@comcast.netSandra Winkler Contributing Editorslwinkler@newventureresearch.comEDITORIAL ADVISORSDr. Andy Mackie (Chair) Indium CorporationRolf Aschenbrenner Fraunhofer InstituteDr. Thomas Di Stefano Centipede SystemsJoseph Fjelstad Verdant ElectronicsDr. Arun Gowda GE Global ResearchDr. John Lau Industrial Tech Research Institute (ITRI)Nick Leonardi Premier Semiconductor ServicesDr. Alan Rae Alfred Technology ResourcesDr. Ephraim Suhir ERS CompanyDr. Venky Sundaram Georgia Institute of Technology-3D Systems Packaging Research CenterFred Taber BiTS WorkshopFrancoise von Trapp 3D InCitesDr. C.P. Wong Georgia Institute of TechnologySUBSCRIPTION--INQUIRIESChip Scale ReviewT 408-429-8585F 408-429-8605subs@chipscalereview.comAdvertising Production Inquiries:Kim Newmanknewman@chipscalereview.comCopyright © 2013 Haley Publishing Inc.Chip Scale Review (ISSN 1526-1344) is a registered trademark ofHaley Publishing Inc. All rights reserved.Subscriptions in the U.S. are available without charge to qualifiedindividuals in the electronics industry. Subscriptions outside of theU.S. (6 issues) by airmail are $100 per year to Canada or $115 peryear to other countries. In the U.S. subscriptions by first class mailare $95 per year.Chip Scale Review, (ISSN 1526-1344), is published six times ayear with issues in January-February, March-April, May-June, July-August, September-October and November-December. Periodicalpostage paid at Los Angeles, Calif., and additional offices.POSTMASTER: Send address changes to Chip Scale Reviewmagazine, P.O. Box 9522, San Jose, CA 95157-0522Printed in the United StatesFROM THE PUBLISHERHappy New Year to all! As we closed out 2012 with a U.S. presidentialelection and having avoided sailing over the fiscal cliff and yet surviving theend of times per the Mayan Calendar, we speculate what the New Year hasin store. What I see and hear from economic forecasters and industry expertsreflect the standard debate between the optimistic and pessimistic perspectives that wereconsistent with the prognostications of last year and indeed every year!All industrial sectors will be looking to take advantage of interest rates by makingcapital investments in new equipment and facilities, as well as looking for strategicacquisitions and joint development opportunities and initiatives including 22nm and450mm technologies. These were evidenced recently by Intel, Samsung and TaiwanSemiconductor‘s significant equity investments that range in the billions of Euros (€)with ASML for development of next-generation lithography systems and technologiesthat will be suitable for patterning 450 mm silicon wafers. The downstream effect willresult with supply chains requiring adaptations to accommodate demands. Companieswill increasingly make investments in additional technical staff, support and seniormanagement hires.At the start of the New Year, CSR announced a new Chair of the magazine’s EditorialAdvisory Board, Dr. Andy C. Mackie, Senior Product Manager at Indium Corporation.Andy sees 2013 as the year when large-scale implementation of 2.5D into the two maindriving applications (mobile devices and lower-power servers) will occur with 3D(memory plus logic) finally also emerging in a prototype form. His company, like many,continues expansion into the Asia-Pacific markets with semiconductor and advancedassembly materials, especially in fluxes and similar materials for flip-chip and 2.5D/3Dmanufacturing and assembly and several offerings into the high-temperature lead-freepower semiconductor market space.With a new editorial board of advisors and a commitment to editorial excellence, Iasked the staff at CSR “What does it take to continue CSR’s excellence?” The unequivocalanswer remains, tons of PhDs, scientists, engineers and technologists from manydisciplines that contribute insightful research articles and the continuing support of oursubscribers and advertisers. I completely agree!This edition of CSR is packed with terrific articles by our industry’s top authors. Wecover BVA PoP, MEMS process solutions, Plasma FIB circuit modifications, cost efficientWLP stacking, WLP functional testing and HVM of 3D, IC packaging economic trendsand the obvious requirements of burn-in & test sockets. It is a cover to cover read.CSR is firmly in the positive-outlook camp for 2013. Jeanne Beacham of DelphonIndustries concludes with a great outlook as well: “I am a true optimist and believe thatdespite today’s economic uncertainty, there are plenty of opportunities for growth.”So as an industry, let’s spend 2013 investing in the future. We’re still here and you,our readers deserve nothing less than the best of the industry, by the industry and for theindustry.Kim NewmanPublisherOf the Industry, By the Industry, &For the Industry6Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

“Panasonic equipmentdelivers best-in-classaccuracy and PanaCIM ®drives operational efficiency”“ Panasonic equipment delivers the best-in-classaccuracy, repeatability, and dependability neededto manufacture the high-quality products ourcustomers expect.PanaCIM software drives operational effi ciencythroughout our high-mix, low-to-medium-volumeprocess—from quick changeovers to real-timeproduction monitoring and reduced rework.Selecting Panasonic has helped us to keepoverall manufacturing costs down, maintainour competitiveness, and allow us to passcost savings to our customers.”Dave SpeharDirector of OperationsAs a manufacturer, Panasonic understands the evolvingdemands of today’s electronics assembly manufacturingenvironment. And that uniquely enables us to provide scalable,integrated, and effi cient solutions that help our customersremain viable in a competitive market.No matter if you’re high mix/low volume, low mix/high volume,or anything in between, Panasonic equipment, MES software,and other services can help improve throughput and effi ciencywhile keeping quality reliably high.Add value, add sustainability, add Panasonic.For more information, visit www.panasonicfa.com/pennatronicsChip Scale Review © Jan/Feb 2013 Panasonic 2013 Corporation [ChipScaleReview.com]of North America. All rights reserved. 7

MARKET TRENDSGlobal Economy Drives the ICIndustry’s CycleBy Bill McClean [IC Insights, Inc.]Throughout 2012, theexpectations for globaleconomic growthconsistently deteriorated. Global GDP isestimated to have expanded by only 2.6%in 2012. It should be noted that 2.5% orless worldwide GDP growth is typicallyconsidered a global recession (annualized3Q12 worldwide GDP growth was only2.5%, equal to the global recessionthreshold figure). Moreover, IC Insights’forecast for 2013 worldwide GDPgrowth is 3.2%. Although this figureis higher than the 2.6% growth rate of2012, it would still be 0.3 points belowthe 3.5% long-term average.One of the primary reasons for weak2012 worldwide GDP growth was thenegative GDP growth registered bythe Eurozone and U.K. economies.Moreover, the Eurozone is not expectedto display a strong rebound, with 0.0%GDP growth forecast for the Eurozoneeconomy in 2013.China’s GDP growth is estimatedto have dropped to only 7.7% in2012 with a modest rebound to 8.1%growth forecast for 2013. While manydeveloped countries would welcome7% or higher GDP growth rates, forChina, this figure is significantly belowthe 10% and greater annual GDPincreases logged from 2002-2009. Inan attempt to address its economic“slowdown,” the Chinese governmentwas quick to inject stimulus into itseconomy starting in the second half of2012 by aggressively lowering interestrates as well as enacting $156 billion inconstruction project programs. Whilethis stimulus was too late to have hada significant positive affect on its 2012GDP growth, China’s GDP is likely toget at least a modest boost from thisstimulus activity in 2013.While the correlation betweenworldwide GDP growth and IC industrygrowth has historically been good (notgreat), IC Insights believes that thecorrelation in 2013 will be very good, asit was in 2012. Using a worldwide GDPforecast of 3.2%, the most likely rangefor IC market growth in 2013 is 3-7%.Including the U.S. presidentialelection year of 2012, over the past11 U.S. election years since 1972,worldwide GDP growth averaged3.9%, while semiconductor industrygrowth averaged 22%. Moreover, thesemiconductor industry grew 10% orbetter in 8 of the past 11 U.S. electionyears. The three election years whenthe semiconductor industry did not grow10% or better (1996, 2008, and 2012), itregistered single-digit declines (with a1% decline occurring in 2012).The election-year cycle is onereason why IC Insights has identified2013 as a possible “slow” year in theworldwide economy and semiconductorindustry. Over the past 10 post-U.S.-election years, worldwide GDP growthaveraged a below-average 3.1% withworldwide semiconductor industrygrowth averaging only 4%. Moreover,worldwide semiconductor industrygrowth exceeded 8% in only three ofthese 10 post-election years (1973,1977, and 1993), and only once sincethe late 1970s.Oftentimes the “problem” withpost-U.S.-election years is that manyof the subsidies and stimulus measuresenacted during an election year arewithdrawn or allowed to expire afterthe election is over. In the case of theU.S., there is likely to be continuingdebate and consternation in Congressover whether to keep the payroll taxcuts (unlikely to be extended) andhow much to raise existing tax levelsin 2013. Although the exact outcomeregarding the future U.S. tax structureand budget is unclear, the large amountof uncertainty created by these issuesis expected to be a “headwind” oneconomic growth in 2013. Becauseof this, the U.S. economy is forecast toshow only a modest rebound in 2013before picking up momentum in 2014.As mentioned earlier, the correlationbetween global economic growth andsemiconductor industry growth has beenrelatively good (see Figure). In somecases, when the semiconductor marketand worldwide economy are moving inopposite directions, the semiconductorindustry is usually encountering aninventory “burn” (e.g., 1985), significantovercapacity (e.g., 1996 and 1997), orsignificant under-capacity (e.g., 1993).IC Insights believes that thesemiconductor industry cycles arebecoming increasingly tied to thehealth of the worldwide economy.While poor semiconductor industrygrowth has occurred during periods ofstrong worldwide economic growth,primarily due to semiconductorindustry overcapacity and the resultingIC price declines, it is rare to havestrong semiconductor industry growthwithout at least a “good” worldwideeconomy to support it. Thus, throughthe forecast period of 2016, annualglobal semiconductor market growthrates are expected to closely mirror theperformance of worldwide GDP growth.8Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

JF MICROTECHNOLOGY SDN BHDBring Possibilities .\WeExplore thesenew exciting andoutstanding solutions onour website or with our nearestsales channel partner today.Find out more at:Or e-mail us at:Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]9

Figure. 1990-2016 Semiconductor Industry Growth vs. Worldwide GDP Growth. SOURCE: IC InsightsIC Packaging TrendsTotal IC unit shipments enjoyedseven consecutive years of growth(2002-2008) before they dropped 7%in the recession year of 2009. Unitsthen rebounded with 29% growth in2010 and another 2% growth in 2011.IC unit shipments were flat in 2012 butare forecast to display average annualgrowth of 5% from 2011 to 2016.IC packaging has evolved from the“old” DIPs (dual in-line packages) to avariety of packages ranging from ultrathinSO (small-outline) packages andCSPs (chip-scale packages) for lowpin-countapplications to BGAs (ballgrid arrays) and MCPs (multi-chippackages) with thousands of solder ball(or bump) connections.It is within the newest packagecategories that the real diversity startsto show. For example, there are BGAdesigns to meet nearly any packagingneed. BGAs can be plastic, tape, orceramic, wire bonded or flip-chipped,cavity-up or cavity-down, overmolded orencapsulated, single-chip or multi-chip.They can have lead counts ranging fromless than 100 to thousands. They maybe made very small and thin for portableelectronics, or thermally and electricallyenhanced for high-speed systems.The options for mounting multiplechips in a single package solutionhave become very diverse. Dice canbe placed side-by-side in MCM- orBGA-type packages, numerous dicecan be stacked on top of each other inpackages the same size as single-chippackages, packages can be stacked atopother packages, bare dice can be bondedtogether to create a 3D integratedcircuit. Additionally, some combinationof any or all these technologies can beused to meet the space requirementsand/or performance needs of eachparticular system application.Shown in the Table is IC Insights’IC unit shipment forecast by packagetype, which has been updated to reflectthe latest expectations for unit growthover the next several years. Advancedpackages such as bare die and waferleveldevices continue to grab marketshare from older package types, but themainstay of package types—SO andFP/CC-type packages—were the mostwidely used in 2012 and are expectedto be the most popular throughout theforecast period. Low-lead-count SOpackages are used primarily in thepackaging of analog and standard logicICs but can also be found in most otherIC categories.For larger chips, with lead countsthat exceed the capability of SOs, LCCs(leaded chip carriers) and QFPs (quadflat packages) are the most widelyused package types. Like the SOs,these peripherally leaded packagescan be found in just about every ICcategory. However, the lead countsof LCCs and QFPs are limited to amaximum of about 80 and 400 pins,respectively. BGA-type packages havedisplaced QFPs, as well as through-holemounted PGAs, in most applications.BGAs offer the advantages of theextensive use of existing surface-mounttechnology infrastructure, high boardlevelassembly yields, superior electricalIC Package Shipment Trends (Billions of Units)11-­‐16 Package Type 10 11 12E 13F 14F 15F 16FExamplesCAGRTSOP, SSOP, SOJ, LOC, SO 65.4 62.0 62.5 64.1 67.0 70.8 76.3 4%SOT, SCQFP, QFN/MLF, Flatpack, FP/CC 44.2 44.8 45.5 48.1 51.0 54.8 59.7 6%PLCC, LCCC, CerpackPBGA, FPBGA/µBGA, TBGA, LGA, BGA (incl. MCP) 32.1 34.6 37.3 40.3 43.6 47.3 51.9 8%CGA, SiP, S-­‐CSP, MCM-­‐BGABare Die 10.1 11.5 12.9 13.6 15.0 16.7 18.8 10% FCOB, COB, COG, COF, TCPUltra CSP, microSMD,Wafer-­‐Level 8.7 9.6 10.5 11.3 12.7 14.7 16.5 11%eWLBMCM 1.1 1.1 1.3 1.3 1.4 1.6 1.8 9% Multichip ModulesThrough-­‐Hole 7.9 7.7 7.7 7.6 7.5 7.6 8.0 1% PDIP, CERDIP, ZIP/SIP, TO, PGATotal 169.6 171.3 177.6 186.3 198.4 213.5 232.9 6%Note: CSPs are included but not considered a distinct package category.Source: IC Insights, TechSearch International, Inc.Table. Package Shipment Trends (Billions of Units). SOURCE: IC Insights10Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

A New Singapore LocationExpanding Our TerritoryWe’re excited to celebrate thisLunar New Year with the launchof our new office in Singapore,serving clients in SE Asia,Taiwan and China.About PlastronicsPlastronics offers complete,reliable burn-in test socketsolutions for the latestpackaged devices. We arecommitted to meeting thechallenges of our clientstoday…and tomorrow.Reliable Sockets and High Performance PinsPLASTRONICS GLOBAL HEADQUARTERS2601 Texas DriveIrving, Texas 75062PHONE 972-258-2580FAX 972-258-6771sales@plastronics.comwww.plastronics.comPLASTRONICS ASIA PTE LTD33 Ubi Avenue 3, # 05-22The VertexSingapore 408868PHONE +65 6570 6882FAX +65 6570 6880asia@plastronics.comChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]11

performance, and higher I/O capability.Over the next five years, some of theIC packages that will enjoy the strongestgrowth in demand will be standard andfine-pitch BGAs, multi-chip packageslike stacked CSPs, package-on-packageDL Trade Ad 4_9:Layout 1 5/1/09 3:49 PM Page 1assemblies, quad flat no-lead (QFN)packages such as bumped chip carriersTHEREARENOSHORTCUTSTOA5-MILDOTSmall, repeatable volumes area challenge. But not impossibleif you have been creating them aslong as we have. However, to doit well, you need three things:Dispensing Expertisein a variety of applications:micro-attach, precision fill,highly-repeatable patterns;Micro ValveFeasibility Testing andprocess verification based on yearsof product engineering, material flowtesting, and software control;Product Development for patented valves,dispensing cartridges, needles, and accessories.For Micro Dispensing, there is oneproduct line that is proven and trustedby manufacturers in semiconductorpackaging, electronics assembly,medical device, and electro-mechanicalassembly the world over.Ror micro-lead frame devices, andwafer-level packages (WLPs). ThreedimensionalICs built using throughsiliconvia (TSV) technology are allthe rage in the news, but 3D ICs willlikely remain a niche technology untilafter 2013 because there are still severalchallenges to overcome with thisHY-FLO Valvewith Thermal ControlsDispenseLink ® for MicroVolume Dispensingwww.dltechnology.comDL Technology is a registered trademark of DL Technology LLC. DispenseLink is a registered trademark of DL Technology LLC.HY-FLO is a trademark of DL Technology LLC.relatively new technology includingthermal management issues and testaccess for individual wafer/die.The group of packages that areconsidered “advanced,” includingBGAs, CSPs, WLPs, and flip-chip-onboard(FCOB) solutions, representedabout 40% of total IC packageshipments in 2012. That share isexpected to grow to 43% by 2016.Overall, there are a multitude ofIC packages currently in use or underdevelopment. The wide variety ofpackages is driven by the fact thatsystem manufacturers increasingly wantpersonalized packages at commodityprices. These are packages with anoptimal balance of thermal and electricalperformance, real estate constraint, andlow cost, mixed and matched to meetthe needs of each particular systemapplication—all in standard outlines orat least built with standard processes.The integrated circuit industry willcontinue to enable more powerfulmachines at lower prices and thepackaging industry will play anincreasingly important role in making ithappen. Developments in wafer-levelpackaging, system-in-package, and theimminent 3D revolution will enablescaling advances in packaging through2016. To date, the packaging industryhas done a good job of overcomingtechnology hurdles, but more challengesare in store. Fortunately, globalcooperation has so far been goodand roadmaps are fairly well-alignedthat help address demands for newpackage architectures, new materials,new processes, and new equipment.All of these will be needed as ICmanufacturers begin to move theirmanufacturing processes to 14nm andsmaller line widths.BiographyBill McClean received his BSin business administration and anAssociate Degree in aviation from the U.of Illinois; he is President of IC Insights,Inc.; email info@icinsights.com12Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

GUEST EDITORIALRequirements: Aren’t They Obvious?By David Barnum [Sensata Technologies]Our business is veryexciting because weactually turn rawmaterials into finishedgoods that are validating building blocksto other higher level electronic systemsthat improve and touch our lives in somany ways, every day. The business ofdesigning a burn-in socket, constructingit, delivering it on time, and at a valuethat meets the customer’s expectation,is in itself, a significant accomplishmentrequiring a lot of information, withno one application exactly the sameas another.Burn-in sockets are subject to thermaland electrical stress, in a controlledenvironment, for the purposes ofinducing the failure of "marginal”semiconductor devices, or those thathave inherent defects resulting frommanufacturing excursions that causetime- and stress-dependent failures.Translation: burn-in sockets try toinduce a failure to prevent marginalsemiconductor devices from getting intomission critical, or high-value systems.Burn-in sockets have a number ofsensitivities associated with them.Because we are trying to force failures,they are presented with many types oftemperature, humidity and durationprofiles, and many types of manual,automatic, and semi-automaticoperations are used to present the chipto the burn-in sockets, which are usuallymounted on a multi-site burn-in board.In addition, there are many types ofchambers and stacking geometries thatcome into play to process all of thedevices needed to be burned-in, in atimely manner.If we start to list the number ofconsiderations, given the dimensionsof the challenge, the list of items iscomprehensive, but crucial in attainingthe goal of getting the right productfor the right customer application.As engineers, we usually leverageour background and make manyassumptions that sometimes lead toa win, but sometimes miss the markconsiderably. To better approach thechallenge, a list of requirements alongwith the particular package drawings arekeys to presenting a winning solution.Listed below are descriptions of someof the more critical requirements andkey factors enabling winning burn-insocket designs.1. Mechanical outline of thepackage (including final thickness)with the pad or ball dimensions, andthe package’s material composition.As long as the package mechanicalsstay stable throughout the developmentthere are usually minimal issues here.If the package thickness or materialcomposition changes between initialdefinition and final state, then real issueswill occur to the point where the socketwill not work initially.2. Burn-in equipment’s orburn-in test condition’s electricalrequirements: resistance, capacitance,inductance, power requirements.Usually, these are well defined, butsometimes there are discrepancies inpower per pin requirements, whichagain challenge the socket’s ability toperform in the burn-in protocol.3. Burn-in test condition’s cyclingdwell times and profile: how longand at what intervals do the parts seeheat, cold and get tested electrically.This issue has come-up many timesas users try to induce failure in theirdevices. Thermal creep and set ofboth plastic and contacts can occur,dependent on dwell times at elevatedtemperatures for both the deviceand the socket, which can lead tocatastrophic failures.4. Applied loading and unloading/packaging equipment mechanicals.This is sometimes a huge issue in highpin count devices (>350 contacts) andin production environments wherehandling can shorten socket lifesubstantially. The termination load ofthe socket cover can limit the amountof sockets used per board or loadingfixture, or an individual operator’sability to load the socket. The physicalhandling of the board from loadingfixture to oven and back to packaginghas a substantial effect on the socketsnear the edges of the burn-in board, asmany times we see broken parts fromhandling issues.5. Height of contacts off board,the termination datum, board-toboardspacing, and socket density onthe burn-in board. In a productionenvironment, these are requirements, asthey determine how much mechanicalstress the sockets and correspondingequipment will see, which willdetermine how long both sides of thesystem will endure.6. Operating temperaturerequirements. These requirementsinclude those for the device undertest, and those mechanical (board-toboardor rack spacing) and electricalconstraints of the system (poweravailability beyond the basic controller),relative to the use (or not) of a passiveheat sink, active heat sink, chamberChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]13

control, or local control. Some socketcompanies can add value in the designof the complete system, which, ifdefined in the beginning, can lead toa very robust and flexible system forfuture requirements.7. Cycling: a practical amount ofdurability cycles are needed. Userswant the maximum available for “design* patents pendingYou can rely on our award-winning support network.Visit our website to contact your local office:USA | China | Europe | Japan | Korea | India | Singapore | TaiwanFind out more now: advancedjetting.comsecurity;” however, many times therequirements are well above the life ofthe particular device being burned-in.Most of the time the first and seconditems listed above are provided, whichgets us to first base. However, what iscritical in the success of the program isan understanding of the remaining itemsin the overall execution of a robust andFaster,Easier,SmarterJettingThe NexJet ® System*featuring the one-pieceGenius Jet Cartridge*The Genius Jet Cartridge is the onlysystem part that contains fluid — theonly piece that needs tobe changed and cleaned.It is easily removed inseconds without tools.Built-in memory tracksand stores usage data,thereby increasing qualityand consistency in precisionmanufacturing applicationssuch as adhesive dispensing, precisecoating and underfill.See Nordson ASYMTEKat SEMICON China,Booth #3663value-oriented design. Socket OEMscertainly understand that many timesusers want to “stack” the requirementsand use certain “production” levelsockets, which have been optimizedfor one set of conditions with manyother conditions for which they werenot intended. Unfortunately, thisusually ends-up with a call into theOEM describing failures. Other times,the design of a new socket missesthe mark because Items 3-7 were notfully comprehended, or communicatedupfront, which is usually a sharedresponsibility between parties. Item7 is always an interesting subject todiscuss, as cost via contact design is ahuge determining parameter regardingthe practical amount of cycles required.The real key is how the parts are used ina production environment.In summary, requirements for robustand value oriented burn-in socketdesigns are dependent on a whole hostof requirements that are sometimes notgiven enough time to be thoroughlyunderstood, as many times the socketOEMs are brought in towards the end ofthe chip development cycle. As can beseen from the list above, there are manythings to comprehend when designing aburn-in socket. While for the most part,the industry does a good job on both sidesof the equation, we do experience enough“hiccups” to inspire the holistic set ofrequirements such as those presentedabove to ensure successful execution inany burn-in application. In this business,there are a plethora of packages thatcan house die. It is incumbent on allof us to work together to better definerequirements upfront to produce betteroutcomes for both the supplier and theuser of burn-in sockets.BiographyDavid Barnum received his BSdegree in mechanical engineering fromthe U. of Massachusetts-Lowell, andstudied finance, operations managementand marketing at the U. of New Haven.He is senior director and global businessunit manager at Sensata Technologies;email dbarnum@sensata.com14Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

GUEST EDITORIALRobust Process Solutions for MEMSFlip-Chip Applications With MediumDensity Lead-Free Solder InterconnectsBy Dave DiPaola [DiPaola Consulting]With the proliferationof MEMS in sensorproducts in a varietyof applications, packaging challengescontinue to be at the forefront ofsuccessful production launches.Furthermore, package shrinkage, costpressure and rapid time to marketmagnify these challenges becausetraditional approaches can no longermeet these constraints. The four majorpackaging challenges that consistentlyappear in product development areelectrical interconnection, mitigatingthe effect of packaging strains on senseelement performance, protecting thesensor from the environment, and propermanagement of temperature distributionand resulting material behavior. Giventhe complexity of these topics, this articlewill review the challenges in electricalinterconnection for increasingly smallerMEMS flip-chip applications usinglead-free solder for medium densityI/O, size sensitive medical applications.With bump sizes of 90µm and bumppitch of 150µm, particular attention incomponent handling, material selectionand process development were requiredto overcome challenges of poor reflowdue to oxidation and shorting, whileminimizing tooling and process cost.In particular, cleanliness, materialhandling, flux selection and application,metallization and reflow profile tuningare reviewed in detail for a robust design.Challenges of Lead-free SolderInterconnectsThere are several factors that increasethe difficulty of lead-free solderinterconnects with medium density I/Ofor MEMS flip-chip applications.These factors include high reflowtemperature, increased surface area ofthe bump relative to its volume, fluxand cleaning limitations, necessity forunderfill and tight I/O spacing. In thetransition from Sn-Pb solder to thosecontaining solely tin, tin, copper andsilver, or other variants, the metal oralloy melting temperature increasedrequiring higher reflow temperatures toensure proper wetting of the joint. Thishigher temperature causes oxidation todevelop more quickly on metallizationand solder making it more difficultto obtain a properly wetted bump.This problem becomes even morechallenging as bump size decreases andthe bump's external surface where oxideis present becomes a larger percent ofthe total solder volume. Therefore,the ratio of oxidized to non-oxidizedsolder increases and increased heat isneeded to overcome this effect creatingan undesirable cycle that cannot besustained. Flux is used to preventoxide growth and remove it from thebumps' external surface during reflow.However, aggressive fluxes cannot beused because of their corrosive nature,ionic contamination and inability tobe cleaned post reflow. The fragilenature of MEMS devices for medicalapplications and the narrow gap betweenchip and substrate make cleaning postreflow ineffective or not practicaldue to product damage. Underfill isalso a requirement in this applicationto prevent shorts from tin whiskersbetween bumps and to minimizestress on the bumps from temperaturefluctuations for medical productslocated outside of the body. The tightI/O spacing also results in a smallerprocess window to prevent soldershorting. Despite these challenges,there are a number of combined stepsthat can be taken to create robust leadfreeinterconnects.Process ConsiderationsProduct cleanliness and materialhandling are crucial but oftenoverlooked steps in creating a robustsolder joint. Rigid and flexible printedcircuit boards readily absorb moistureand this moisture is outgassed from theproduct during reflow thereby increasingoxide growth on the bump. To preventthis, circuit boards can be pre-bakedat 125°C for 2-6 hours (depending onenvironmental exposure and moisturepresent) in an oven to drive offmoisture prior to reflow. In addition,metallization on the substrates should beselected to minimize oxidation growthduring this step. If the substrate isbumped rather than the MEMS flip-chip,another option is to ship the productsin vacuum sealed, desiccant bags andstore them in nitrogen back-filledChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]15

chambers when not being processed tolimit exposure to humidity and oxygen.Product cleanliness is equally importantbecause specific contaminations such assodium chloride can accelerate oxidationgrowth and ionic contamination cancreate shorts in the presence of moisture.Clean process environments andaqueous-based cleaners followed by postbake are often effective.The cleaning action of flux to removeoxide is another critical step to a propersolder reflow process. Without thepost reflow cleaning option for manymedical MEMS devices, rosin-basedROL0 fluxes without halides thatcompletely evaporate during refloware recommended for use. The use ofhalides in fluxes provide better cleaningaction but are avoided because of theircorrosive nature and they cause ioniccontamination that can lead to shortswithout cleaning. One flux option thatprovides more aggressive cleaning butcontains no halides is ROM0. It is bestto limit flux application to the lowerhalf of the bump covering 30-50% ofits surface. In some cases, more fluxis required to clean the oxide presentand maintain activity during highertemperature processing of lead-freesolders. In either case, it is importantto ensure no residue is left that mayinterfere with the underfill processcreating voids or adhesion issues.Lastly, it is important to choose a fluxwith an 8+ hour working life and thathas sufficient tackiness to preventthe part from skewing during reflow.MEMS devices are extremely lightweight and can be easily moved fromthe desired position.Solder reflow profile selection andsubstrate metallization are of equalimportance to the previous steps inachieving proper bump wetting andcollapse. In an ideal scenario, it isdesired to achieve a 15-30% collapseof the solder bump and have the soldercompletely wet the substrate surface.Examples of properly wet and non-wetbumps are provided in Figure 1.A typical reflow profile for SAC 305Figure 1. Non-wet and wet solder bumps.lead-free solder consists of pre-heatingincluding soak, reflow and cool downzones. To achieve the proper wettingdefined above for MEMS applications,the typical reflow profile needs tobe adjusted. More specifically, it isimportant to minimize the preheat zoneto keep the flux active and prevent itfrom drying out. This could result innearly a straight ramp to the reflow zone.In addition, the reflow zone needs to beadjusted to compensate for the level ofoxide on the bumps and type of solderbeing used. It's best to keep reflow peaktemperature as low as possible whilestill maintaining a reasonable processwindow. If the reflow is performed ina nitrogen atmosphere, which is highlyrecommended to limit oxide growth,the peak temperature will be lowerand the reflow zone shorter. If reflowis performed in air, one can expecthigher reflow peak temperature forlonger duration. Although a nitrogenatmosphere is recommended, it is notalways easily implemented, especiallywhen production equipment is alreadyin place, or funds are extremely limitedin a medical device startup. In othercases, the product may already belaunched with an air reflow process withpoor yield, and it could be weeks beforean equipment upgrade to add nitrogencan occur. Figure 2 shows a typicallead-free solder reflow profile with twomodified versions, for air and nitrogen,as described above.After reflow is complete, underfillapplication is an important step tominimize the stress induced in thesolder joints from differing coefficientsof thermal expansion (CTE) of thesubstrate and MEMS flip-chip. Theunderfill minimizes shear forces on thebump and causes the substrate and chipto slightly bend as one unit. Anothercritical function of the underfill is toprevent tin whiskers from creatingshorts between the bumps. Leadfreesolders have a high percentage oftin and are highly susceptible to thisunpredictable failure mode. NASA hasobserved whisker formation after a fewhours, and in some cases, they do notform for many years [1].A robust metallization for the bondpad on the mating substrate is alsorequired to prevent oxide growth,ensure proper wetting and excellentadhesion. On printed circuit boards,this metallization is often electrolytic orelectroless nickel with flash gold overa copper base layer. There are multipleFigure 2. Typical and modified lead-free solder reflow profiles for SAC 305.16Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

40 + years ofAnd now, the perfect nameTMQi•nex [kuh-nekts] 1. Over 40 years ofreliable burn-in and custom connections;2. Quality interconnects for nex-gen solutions.Introducing Qinex, thenew brand name forsuperior interconnectionsolutions from SensataTechnologies. Qinex, thenew word in perfectpitch.QUALITY. High-value interconnectionsolutions since 1970.• 24/7 global engineering• 24/7 global support teams• Local engineering and sales• Six Sigma quality management• Proven, reliable high-volumemanufacturing• Expert molding, design, andcustomizationINNOVATION. More I/O choices,smaller form factors, superiorperformance in less time.• Latest 3D design tools• On-site model shops• Rapid prototyping• Advanced thermal analysis• Design on demand• Broad range of innovativecontact designsPARTNERSHIP. In a fierce globalmarket, only Qinex reliably supportsthe innovation, reputation andcompetitiveness of your business.We’ll work with you to get it right,the first time.40+ years of perfect pitch.And now, the perfect name.WEB www.qinex.comEMAIL qinex@sensata.comCALL 1-508-236-1306Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]17

options for the chip metallization, butone popular example is immersion goldover electroless nickel with a zincatedaluminum base layer. Both Pac Techand Uyemura have reported differinglevels of success with palladium as adiffusion barrier between the nickel andsolder. The tin and nickel intermetallicis brittle and can be a source of failurein high stress conditions such as droptest. There are examples of palladiumuse between the nickel and gold layers,or as the top layer without gold [2-3].SummaryThe difficulties in creating robustlead-free solder joints for medicalMEMS flip-chip applicationsEVG ® 850TB/DB XT FRAMEIntroducing the next-generationtemporary bonding and debonding platformfor high-volume 3D IC manufacturingLowTempDebondingEVG TechnologyZoneBOND ®LowTemp DebondingEVG ® ZoneBOND ® Open PlatformTemporary Wafer Bonding / Debonding SolutionsMultiple Adhesive SuppliersHigh Throughput Production SystemsIntegrated Metrology for Advanced Process ControlU.S. Patents 6,792,991 and 7,910,454Further Patents Pendingwww.EVGroup.comof increasing smaller size withconfounding process parameters andmaterials is a real challenge. Thesolution to this problem lies withinan intertwined mix of oxide growthminimization, proper materialselection and application, and subtleprocess parameter adjustments. Morespecifically, cleanliness, proper storageand handling or pre-bake, flux and itsapplication, the solder reflow profile,chip and substrate metallizations andunderfill, are all critical elements in theprocess. Hence, when each of theseparameters and materials are designedto work together, robust lead-free solderjoints with high first-pass yields canbe achieved.References1. J. Brusse, H. Leidecker, L.Panashchenko, "Metal Whiskers,A Discussion of Risks andMitigation," Proc. of Symposiumon Part Reprocessing. NASA, 12Nov. 2008; Web, 12 Feb. 2012,.2. G. Milad, D. Gudeczauskas,"Solder Joint Reliability of GoldSurface Finishes (ENIG, ENEPIGand DIG) for PWB Assembled withLead Free SAC Alloy," Solder JointReliability; Uyemura InternationalCorp. 2012; Web. 14 Nov. 2012;http://www.uyemura.com/solder_joint_reliability.htm#53. T. Teutsch, "ENIG vs. ENEP(G)Under Bump Metallizationfor Lead-free WL-CSP SolderBumps – a Comparison ofIntermetallic Properties UsingHigh Speed Pull Test," IMAPSInternational Conf. on DevicePackaging. 17-20 March 2008,Scottsdale, AZ. Pac Tech; Web.14 Nov 2012, http://pactech.com/files/56%20NiPdAuforIMAPS%20Scottsdale%202008.pdfBiographyDavid DiPaola is Managing Director forDiPaola Consulting, www.dceams.com;email david@dceams.com18Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

INDUSTRY NEWSUltratech Acquires Assets ofCambridge Nanotech, Inc.Ultratech, Inc. has acquired the assetsof Cambridge Nanotech, Inc. Basedin Cambridge, Mass., Cambridge wasa leader in atomic layer deposition(ALD) solutions with hundreds ofsystem installations in research andmanufacturing settings worldwide.Financial terms of the transaction werenot disclosed. With this acquisition,Ultratech expands its nanotechnologyand intellectual property (IP) portfoliowith ALD technology to providesolutions for new layers within theelectronics industry and entry into newmarkets, such as biomedical and energy.The company noted that ALDtechnology will be in high demand involume manufacturing environments,and in particular for micro-electromechanicalsystems (MEMS),implantable devices in the biomedicalsector, and batteries and fuel cells inthe energy arena. ALD is an enablingtechnology and provides coatingsand material features with significantadvantages to other existing techniques.Ultratech Chairman and ChiefExecutive Officer Arthur W. Zafiropoulostated, "As a global leader inexperimental ALD solutions, Cambridgehas developed a portfolio of valuabletechnology and systems. We planto integrate the intellectual propertyacquired from Cambridge Nanotech intoUltratech and include the ALD systemsin our nanotechnology product group.By increasing our IP and expanding ournanotechnology portfolio to new levels,we expect to generate a new revenuestream in existing and new markets."interposer (TSI) multi-project wafer(MPW) service, aimed at providing acost-effective platform to do researchand development prototyping and proofof-conceptin 2.5D TSI technology.Supported by IME’s state-of-the-art 3Dthrough-silicon-via (TSV) engineeringline, the MPW service is a one-stopsolution for 2.5D TSI R&D prototypingthat comes with comprehensive designkits, via and redistribution/bumpingtechnology, as well as packaging andassembly capabilities. By enablingthe heterogeneous integration ofdifferent functionalities including logic,memory, analog/RF, photonics, microelectromechanicalsystems, devices withmore functionality, smaller form factorand less power consumption can nowbe realized.The service will enable the academic,research and industrial community toYour Best Testing PartnerAddress: 101 Metro Dr.#540 San Jose, CA 95110Tel: 1-408-452-7680Fax: 1-408-452-7689A*STAR’s IME Launches 2.5DSilicon Interposer Multi-projectWafer OfferingThe Institute of Microelectronics(IME), a research institute of the Agencyfor Science, Technology and Research(A*STAR) in Singapore, announcedthe launch of its 2.5D through-silicondevelop2.5D research test vehicles withleading-edge designs, materials andprocesses so that they can be appliedto products such as smart phones,tablets, networking and sensors, andbiomedical applications.A*STAR’s IME to Collaboratewith SFC Fluidics ® on AutomatedBiosensorA*STAR recently announced thatthrough its Institute of Microelectronics(IME), it will be collaborating withSFC Fluidics ® , a USA microfluidicsbasedbiomedical device developmentcompany, to develop a portablediagnostic tool for rapid triaging oftraumatic brain injury (TBI) victimsand to improve the treatment strategies.TBI is one of the most common causesof death and disability in the world,usually resulting from blasts, falls,KYECHuge test capacities● HQ in Taiwan & Worldwide Offices, covering USA, Japan, Europe, China and Singapore● Over 2000 sets of test systems and growing● Powerful test capabilities and efficient production logisticsKYEC is a leading providerof testing services andsolutions to the IC industryWide range of test capabilities● Professional testing services, covering Wafer probe, Final test, Pre-Assembly, Burn-in, Backend● Complete testing Solutions and equipment, such as Memory, Logic, SOC, RF, CIS, MEMS● Customized test accessories service● Strong R&D team and advance test technologywww.kyec.comChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]19

knocks, traffic accidents, and assaults.The proposed diagnostic tool is afully-integrated, automated biosensordevice that requires only a drop of bloodto detect up to three biomarkers releasedby the brain after sustaining injury. Thebiomarker readings will be displayed onan easy-to-read screen, along with anindicator, alerting the caregiver to theseverity of the injury.Unlike conventional diagnostic toolssuch as neurological tests and computedtomography (CT) scans, the biosensordevice does not require any trainedpersonnel for sample handling. Theportable feature of the device facilitatesrapid on-site diagnosis of the injury.Caregivers will be able to respondquickly with the proper course oftreatment to prevent injury aggravation.The biosensor device leveragesand integrates IME’s silicon-basedmicrofluidic sensor and biosensortechnology and bio-electrochemicalassay development capability. IME hasbuilt up strong capabilities in biomedicalmicrosystems and has establisheddeep collaborations with the clinicalcommunity and key industry partnersin Singapore to advance silicon-basedpoint-of-care diagnostics devices.SFC noted that, by leveraging IME’sindustry standard mass productionfacilities, the company will be able tocut down the product development cycletime. SFC’s VP of R&D, Sai Kumar,stated that the TBI project is the startof a longer term collaboration that thecompany will explore together with IME.AG Semiconductor Services EntersRemarketing BusinessAG Semiconductor Services, LLC(AGSS), announced the formation ofa new remarketing services divisiontargeting 150, 200 and 300mmsemiconductor, IC test/assembly andprinted circuit assembly equipment.The company has made a significantinvestment in personnel and businesssystems to ensure its ability to delivera full slate of remarketing services inaddition to the purchase and sale ofsurplus semiconductor manufacturingequipment, turnkey solutions, inventorymanagement, market metrics, compliancecontrol, and the ability to reach thelargest number of buyers. A seasonedteam has been brought on board toramp up the remarketing activities. Themajority of the new remarketing teamcame to the company from the formerGE Capital Global Electronics Services'(GES) remarketing business.ZESTRON Opens JapanHeadquarters and Technical CenterZESTRON has opened its JapanHeadquarters and 6th Technical Centerlocated in Kanagawa; it represents thecompany’s 4th Asian Technical Center.Figure: ZESTRON Japan Headquarters andTechnical CenterThe investment enables the company tointroduce leading edge aqueous-basedcleaning agents within this market as anenvironmentally sound alternative to themany solvent-based cleaning productscurrently used.Mr. Daido Sawairi, General Managerfor ZESTRON Japan, is responsiblefor operations and leading the localapplication engineers and sales team.He has over 20 years of domestic andinternational business experience in theelectronics field and has held variousmanagement positions during his career.Test Advantage Hardware NamesBilly Liu Country Managerfor TaiwanBoston Semi Equipment LLC (BSEGroup) announcedthe appointmentof Billy Liu asTest AdvantageHardware’s countrymanager for Taiwan.Liu is responsibleBilly Liu for managing TestAdvantage’s expanding business fornew and pre-owned semiconductortest equipment, spare parts, technicalcapabilities and financial solutionswithin Taiwan.Liu will work within the company¹snewly formed Taiwan operation, TestAdvantage PTE Ltd., Taiwan Branch,with additional responsibilities forstaffing and recruitment. He bringsa background in semiconductor testand over 18 years of experience in thetechnology industry within Taiwan.Philippe Wieczorek NamedMinalogic’s Software DirectorMinalogic announced that PhilippeWieczorek has beennamed directorof the SoftwareDepartment. Hewill be responsiblefor coordinatingand expandingPhilippe Wieczorek Minalogic’s softwaredevelopment activities, includingprojects that help cluster membersintegrate innovative software featuresin microelectronics and develop smartminiaturized products and solutions.Wieczorek most recently servedas chief of staff of Hewlett Packard’sInternal Sites Management Team (ISMT)in Grenoble. In that position, he focusedon creating R&D activity and on ISMT’srelationships with institutional playersand academics. At HP, Wieczorek alsowas an innovation manager for thecompany’s Communications and MediaSolutions business unit, managinginternational projects.Earlier in his career, Wieczorek workedin the network and telecommunicationfields, where he held engineering20Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

positions ranging from software development to engineeringmanager. He also worked for five years at Cap Gemini S.A.He holds an MS in computer science from McGill Universityin Montreal, Canada, and an engineering degree from INSALyon, France.Patrick Boisseau, Head of Leti’s Nanomed Program,Elected Chairman Of the European Technology Platformon NanomedicineCEA-Leti has announced that PatrickBoisseau, the head of Leti’s nanomedicineprogram, has been elected chairman ofthe European Technology Platform –Nanomedicine (ETPN), a joint initiativebetween industry, academia, clinicians andthe European Commission to help build aPatrick Boisseau profitable nanomedicine sector in Europe.Most of the innovation in Europe is occurring in research labsand small to midsize enterprises (SMEs), including start-upsthat have spun off from universities and research institutes.Boisseau said two of his primary goals during his twoyearterm as chairman of ETPN are keeping the nanomedinnovation that is underway at many European facilities andSMEs in Europe, and to help build a nanomedicine sector thatcan compete strongly with Asia and the U.S. “One key wayto do that is to organize a supply chain of SMEs to facilitatethe transfer of innovation and technology to large companiesand make these technologies available to patients as soonas possible,” said Boisseau. “It also will require us to buildkey infrastructure in Europe, such as an EU nanotechnologycharacterization lab or a network of good manufacturingpractices sites for medical nanomaterials. This initiative alsowill be a good opportunity for leading European institutes likeKTH, EPFL, Helmholtz Foundation, Tecnalia, Fraunhofer,SINTEF, and Leti to expand their nanomed partnerships withboth SMEs and large companies.”Boisseau has chaired the ETPN working group on nanodiagnosticssince the ETPN was formed in 2005. In the sameelection, Dr. Laurent Levy, CEO of Nanobiotix, was electedvice chairman of ETPN. He represents SMEs on the platform’sexecutive board.Edward Watkins Joins SMT International as SeniorResearch ChemistSMT International, LLC has justannounced the hiring of Edward Watkinsas a Senior Research Chemist for thecompany’s AMTECH solder products.An accomplished chemist with decadesof experience in research, productdevelopment and analytical testing,Mr. Watkins will utilize his extensiveEdward WatkinsZoneBOND ® technologyThe proven thin-wafer-handling solutionMaterialsProcessesequiPMentSiliconCompound SemiconductorMEMSContact Brewer Science for your product or process needswww.brewerscience.comChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]21

ackground and experience to assist inthe development of innovative solderpastes, fluxes, and process supportproducts utilized in circuits assembly.Watkins’ educational backgroundincludes degrees from SusquehannaUniversity (BA) and PennsylvaniaState University (PhD), as well asserving as a full-time associate researchscientist at Yale University. Watkins’resume also includes working for globalcorporate leaders such as Pfizer, DowChemical and Amgen. These and otherexperiences have allowed Watkinsto take a leadership role in productresearch and development, intellectualproperty rights and patents, technicalwriting, manufacturing and QC processdevelopment, regulatory investigationsand filings, as well as managing teamsof research scientists.ESCATEC Promotes Markus Waltherto CEOESCATEC hasannounced theappointment ofMarkus Waltherto the role of CEOof the ESCATECGroup, effectiveMarkus Walther January 1, 2013.Markus started at ESCATEC as aTechnical Manager 23 years ago andadvanced through the company to hiscurrent role as COO. The position ofCOO will remain open until a suitablecandidate is selected.Christophe Albin, ExecutiveChairman of the Board of Directorsand founder of ESCATEC, said,"Markus has made major contributionsto the success of ESCATEC, helpingthe company establish itself as amajor global player in the electronicsengineering and manufacturing("E2MS") industry through offeringworld class customer service backedby Swiss quality and reliability. It isparticularly gratifying that our policyof continually investing in our peopleand their career development producesoutstanding staff such as Markus, whohas worked in most departments duringhis 23 year career at ESCATEC, andtherefore has hands on experienceto draw upon to bring out the bestin people."Commenting on his appointment,Markus Walther added, "I am veryhonored to continue to serve ESCATECin my new appointment as CEO.Handing the day to day operationalmanagement of the business to anew COO will enable me to applymore of my time to supporting thestrategic growth of the business. Wesee significant opportunities to growthrough more focus on the US market,continuing to expand our presence inEurope, and offering a very effectivemanufacturing alternative in SouthEast Asia to the ever increasing cost ofChina. It will also allow me to continuethe development of, and investmentin, our employees, our manufacturingtechnologies and capacity in orderto support our growth strategy andwith customer service always in ourminds. We call this ESCATEC's wayto success."Barry Cox Joins TouchstoneSemiconductor as ExecutiveChairman of the BoardTouchstone Semiconductorappointed BarryL. Cox ExecutiveChairman of itsBoard of Directors.Cox brings morethan 45 yearsof leadershipexperience in theBarry Coxsemiconductor industry. He has heldsenior management positions includingPresident, CEO and Chairman of theBoard at several private and publiccorporations. In addition to Touchstone,he is a member of the Board ofDirectors of Pixelworks and Audience.He has served on the Board of Directorsof 18 corporations and been involvedin four public offerings, two secondaryofferings and 11 acquisitions at thesecompanies. He holds a Bachelor ofScience degree from the US Air ForceAcademy and a Master’s in BusinessAdministration from Boston University.Carsem Expands Role of VP AllanCalamoneriCarsem announced that AllanCalamoneri has assumed theresponsibilities of VP of Sales, NorthAmerica, effective immediately.Calamoneri is based in the Scotts Valley,California office and reports to AlbertLaw, Carsem’s VP of World Wide Salesand Marketing.Calamoneri – who has a 23-yearcareer in the semiconductor industry –has COO experience and a track recordof successful results in both domesticand international management roles,noted the company. Associated withCarsem Inc. since 2004, his most recentexperience was as VP of Test BusinessDevelopment. In his new, expanded role,Calamoneri will have responsibilityfor the entire selling organization ofCarsem in North America. Reportingto him are three regional sales directorsand a technical sales director.ECTC Registration is Now OpenThis year’s Electronic Componentsand Technology Conference (ECTC)will feature more than 300 high-qualitypapers over 36 oral sessions, fourinteractive presentation sessions andone student poster session.The sessions cover peer-reviewedpapers on 3D/TSV, embeddeddevices, LEDs, co-design, RFpackaging, electrical and mechanicalmodeling, advanced packagingand interconnections technologies,22Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

materials, assembly manufacturing,system packaging, optoelectronics,reliability, MEMS, and sensors.There will also be four invitedsessions:LED Packaging Technologies andMarket Trends – For A BrighterFutureChair: Ricky Lee – Hong KongUniversity of Science and TechnologyPackaging Challenges Across theWireless Market Supply ChainChair: Lou Nicholls - AmkorThe Role of Wafer Foundries inNext Generation PackagingChair Sam Karikalan - BroadcomCorporationCPMT Seminar: AdvancedLow Loss Dielectric Materials forLarge Data High-speed Wide BandTransmissionChair: Kishio Yokouchi – Fujitsu ITLAnd a special modeling session:Modeling and Simulation Challenges in3D systems.Chairs: Yong Liu - FairchildSemiconductor; Dan Oh - AlteraThe ECTC also features 16 CEUapprovedprofessional developmentcourses and over 70 exhibitors.The 63rd ECTC, sponsored by theCPMT society of IEEE, will be heldMay 28 - 31, 2013 at the CosmopolitanHotel, Las Vegas, Nevada. For moreinformation and registration, visitwww.ectc.net.the 10th Annual International Wafer-Level Packaging Conference andTabletop Exhibition. This premierindustry event explores leadingedgedesign, material, and processtechnologies being applied to Wafer-Level Packaging applications. Therewill be special emphasis on thenumerous device and end productapplications (RF/wireless, sensors,mixed technology, optoelectronics)that demand wafer level packagingsolutions for integration, cost, andperformance requirements.The IWLPC Technical Committeewould like to invite you to submit anabstract for this program. Abstractdeadline is March 29, 2013.The conference includes threetracks with two days of technicalpaper presentations covering: WaferLevel Packaging; 3-D (Stacked)Packaging; and MEMS Packaging.Also we will offer professionaldevelopment courses.If you would like to present at thisconference, please submit a 200-300 word abstract by March 29th,2013. Please include a title, authorname, and contact information withyour abstract.Note that technical papers arerequired and will be due August23, 2013.For more information on theconference, please contact PattiHvidhyld at 952-920-7682 or topatti@smta.org. For informationto exhibit and sponsorshipopportunities please contact yourCSR sales rep or CSR Publisher atinfo@chipscalereview.comSockets, Contactors & Adaptersfor Prototype Development & Test• Compatible with virtually any footprint• Probe-pin & Elastomer solutions• Pitch range from 0.30mm to 2.54mm• Pin counts up to 2000• Bandwidth to 40GHz• SMT, thru-hole & solderless options• Several socket closure styles available• Custom requirements are welcome• Competitive pricing• Expedited deliveryCall for PapersInternational Wafer-LevelPackaging ConferenceThe SMTA and Chip Scale Revieware pleased to announce plans forFor further information visit www.e-tec.comor contact us directly for immediate attentionE-Tec Interconnect Ltd, USA Marketing & SalesE-mail: info-US@E-tec.com, Telephone: +1 408.746.2800(www.e-tec.com)Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]23

Cost Efficient Wafer-Level Stacking TechnologiesBy Mariam Sadaka, [Soitec USA] Ionut Radu, Chrystelle Lagahe-Blanchard, [Soitec France] Lea Di Cioccio [CEA-Leti]3D integration aimsat providing highlyintegrated systems by verticallystacking and connecting variousmaterials, technologies, and functionalcomponents together. In this emergingfield, new technologies and integrationschemes will be necessary to meet theassociated manufacturing challenges.To address these challenges, we havedeveloped two wafer-level stackingtechnologies – Smart Stacking TM andSmart Cut TM – for improving the processcost efficiency and providing submicronalignment capability.3D Process Integration OptionsThere are a number of 3D processintegration options – the verticalstacking of top and bottom layers isone example. This stacking can beperformed in two different ways: waferto-wafer(W2W) bonding, or die-towafer (D2W) bonding. W2W bondingis where the entire top and bottomwafers are bonded together. D2Wbonding is where the top layer is dicedinto chips that are individually stackedusing pick-and-place on top of a bottomwafer. The bonding process for the twoapproaches is collectively performed ina single step. Dicing of the W2W stackis done through the entire bonded stack,whereas dicing for D2W is done throughthe bottom wafer with the bonded dieon top.With these two stacking options,different trade-offs arise. WhileD2W stacking uses known good die(KGD) and facilitates the integrationof heterogeneous technologies, W2Wstacking simplifies the stackingprocess flow and maximizes theprocess throughput for homogeneousFigure 1a: Process schematic of the Smart Stacking technology.technologies with matching die size.W2W bonding is a fab-compatibleprocess with throughput independentof die size. D2W integration does notoffer the same level of cleanlinesswhen using standard wafer processingequipment, and wafer cycle time isdirectly impacted by die size [1]. W2Wbonding is most suitable for applicationswith high wafer yield and matching diesize; one example is memory stacking,which also benefits from a variety ofrepair strategies [2].While there are still many remainingissues for 3D integration, cost iscertainly a major challenge. We havedeveloped a W2W high throughputdirect bonding to improve process costefficiency and to provide sub-micronalignment capability required for highdensitythrough-silicon vias (TSV) [3].This article will describe our buildingblocks for 3D IC wafer-level stacking:Smart Stacking – a high-throughputlow temperature direct wafer bondingwith sub-micron alignment, and SmartCut – a low-temperature layer transferstacking process.Smart StackingSmart Stacking is a W2W stackingtechnology platform of partially orfully processed wafers (Figure 1a). Theprocess includes surface conditioning,room temperature low stress bondingwith alignment, low-temperature postbondanneal, grinding and thinning.Room temperature bonding ensures lowthermal expansion mismatch, less stressand mechanical deformation, which arecritical for high alignment accuracy [4].To address the thermal budget constraintimposed by stacking of backend ofthe line processed wafers (i.e.,

layers of backend metal (10ML) and adeposited oxide layer on top acting asthe bonding layer. Wafer topology wascontrolled by a chemical-mechanicalpolishing process that maintains waferedge quality and wafer micro-roughness1J/m² atonly 200°C (Figure 2a). An acousticmicroscope image of two bonded300mm wafers with more than 10MLshow excellent defectivity at theFigure 1b: W2W alignment accuracy across a300mm wafer.Precision W2W alignment representsa key requirement for the waferlevelvertical integration of 3D ICs.Following the preparation of thepatterned surfaces, the processed wafersare bonded using an EVG Smartview®tool. The common alignmentspecification for this tool is ±1µm,and the alignment is measured usingan infrared transmission microscope.Since no external force or pressure, ortemperature cycle, is applied during thebonding process, excellent alignmentwith minimum mechanical deformationis obtained. W2W alignment accuracyof ~0.2µm across 300mm wafers hasbeen achieved (Figure 1b) [5, 6].Oxide-Oxide Direct BondingSmart Stacking technology based onlow-temperature dielectric, hermeticallysealed, and reliable (MIL-STD883)direct bonding, is a promising pathfor 3D integration that benefits fromestablished oxide-oxide bondingtechnology [8]. The motivation behinddielectric bonding is to achieve amechanical bond between the faceto-face(F2F) bonded wafers withoutintroducing new materials in orderto maintain manufacturability andreliability standards. This stackingprocess requires a TSV last approach toform the desired inter-wafer connection.Direct bonding of two oxide surfacesrequires considerable control ofsurface properties. The Smart Stackingtechnology was demonstrated on300mm wafers with more than 10ŖoHSChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]25

Figure 2a: Surface energy ( ) evolution with temperature of oxide bonding stacks using three differentdeposited oxides.bonding interface and with minimumedge exclusion (Figure 2b) [5].Figure 2b: Acoustic microscope image of the oxidebonding interface of 300mm processed wafers.atmospheric pressure and is based onmolecular adhesion between surfaces incontact. The bonding process does notrequire any additional processing steps;standard dual-damascene processesand surface treatment techniques areoptimized to ensure smooth hydrophilicsurfaces for good bonding conditions[6]. The bonding can be done directlyafter standard backend processes andcan be adapted with via middle and vialast, F2F and F2B integration schemes.Copper pad sizes varying from 5µmto 500µm with a pitch of 10µm and40µm were investigated, and excellentbonding interface defectivity wasdemonstrated (Figure 3a). Typically,Figure 3a: Acoustic microscope image of thepatterned Cu bonding interface (5x5µm Cu padsize and 10µm pitch, Cu density 20%) with 2h ofannealing at 400°Cvarious interfaces are formed afterpatterned copper bonding. The bondingstrength of the different types ofinterfaces has been evaluated (Figure3b). The highest bonding energy isobtained for copper-copper (Cu-Cu)interfaces, followed by SiO 2 -SiO 2 .The Cu-SiO 2 interface leads to theweakest adhesion even after 400°Cannealing [6]. Copper interdiffusionand/or grain growth across the Cu-Cubonded interface are the driving forcesfor achieving high bond strength [6, 8].The achieved bonding strength has beensufficient to sustain post-processing suchas silicon back thinning using coarseand fine grinding. In terms of electricalcharacterization, a specific contactresistance of 0.5Ω•µm² for a 10x10µm²contact area after annealing at 200°CMetal-Metal BondingSmart Stacking technology basedon low-temperature patterned metalbonding enables the formation ofelectrical connections during thestacking process—a promising pathfor high-density 3D interconnects [9].Even if TSVs are still needed for power,input/output (I/O), and signal routingthrough the different strata, metalbonding has a significant bandwidthadvantage over dielectric bonding [10].Unlike thermo compression, thenon-thermo compression bonding isperformed at room temperature underFigure 3b: Bonding energy evolution with temperature of different types of interfaces (Cu-Cu, Cu-Ox andOx-Ox).26Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

and 400°C for 2h was achieved [6,11]. The resistance per node extractedfrom a ~30K daisy chain after 400°Cpost-bond anneal showed negligibleresistance induced by bonding [11, 12].In addition, initial reliability data basedon electromigration (EM) testing showsthat the bonded metallic interfacesare not the dominant path for the EMphenomena [13].Stacking by Smart CutSmart Cut technology [14] providesa path to monolithic 3D integrationand enables the transfer of a blanketlayer of single-crystal Si film onto aprocessed wafer (Figure 4a). On thisnew single-crystal Si surface, a secondlevel of devices can be processed andthis integration can be repeated in aniterative mode.This technology benefits fromexisting high-volume manufacturingSOI infrastructure in addition tooptimum donor wafer recyclingtechniques for lower cost-of-ownership.Figure 4a: Process schematic of the Smart Cut TechnologyCompared to standard back thinningtechniques, the Smart Cut atomic levelsplitting enables ultrathin (down to0.1µm) layer transfer, thus simplifyingand lowering the cost-of-ownershipof the TSV process. The ultrathintransferred Si contributes to a smallerTSV aspect ratio that allows scaling to ahigher TSV density, or simply the use ofmore cost effective regular backend viasinstead, thus making this technologyattractive for applications that requirehigher interconnect densities.This approach is based on our abilityto optimize the bonding energy bydiminishing the overall thermal budgetChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]27

(as done for Smart Stacking) as wellas optimizing the splitting kinetics toachieve splitting at low temperature(

A PoP for the Post-PC EraBy Ilyas Mohammed [Invensas Corporation]Mobile computing hasevolved beyond PCcomputing capabilities and can carry outtasks ranging from office productivityand communication to high-density(HD) media and gaming. There are threebroad trends in computing over the pastfew years that have a significant impacton the processor-memory architectureand its implementation. They are:1) The transition from single core tomulti-core CPUs, which dramaticallyincreased the need for multiple memorychannels, the channel bandwidth andthe amount of memory that is accessibleto each core; 2) Low power computingthat emphasizes physically shortinterconnects along with a wide bus atlower speeds for high bandwidth, and 3)Cloud computing, which benefits fromhaving both hardware and softwareoptimized and centrally managed forpower and usage.The most critical feature to keepincreasing the performance is theprocessor-memory interconnect. TheCPU and memory cycle time gap isincreasing, which means that it takes farlonger to get data to the processor thanthe time taken to use it. This problem istypically addressed by optimizing acrossvarious memory hierarchies. Knowingthat storage is not suitable due to itsvery high latency, processor-DRAMsubsystem receives the most attentionfor improvement.Hence, there is a need for a solutionthat addresses the processor-memorybottleneck through very wide I/O forhigh bandwidth while consuming lowpower. An order of magnitude increasein the processor-memory I/O will makethe 3D package a universal candidate forhigh computing. The current packageon-package(PoP) modules have limiteddata I/O (~32-64) and a new technologyis needed to meet the high I/O (128-512) requirements. Bond Via Array TM(BVA TM ) Package-on-Package (PoP)offers ultra-high bandwidth betweenmulti-core CPU-GPU SoC processorsand wide I/O low power memorychips utilizing conventional wirebondtechnology and existing materialsand infrastructure.Bond Via Array (BVA) Package-on-Package (PoP)Figure 1 illustrates the BondVia Array (BVA) wire-bond arrayinterconnect concept. The main featureis that the BVA interconnects (freestandingwire-bonds) extend from thebottom substrate to the top surface ofthe bottom package to be connected to apackage mounted on top.The mature wire-bonding technologyoffers very fine pitch, and free-standingwires are formed using proprietaryprocesses utilizing conventional wirebondequipment. As the wire-bondscan be done at a pitch as small as50µm, and can extend in length toany desired value, high aspect ratio(height to diameter ratio greater than10) interconnects can be achieved. Thisinterconnect technology lends itself to awide variety of 3D packaging, includingPoP, wafer level, embedded, etc.The interconnect scalingcapabilities are tabulatedin Table 1. For a given14mm x 14mm package andassuming a 1mm peripheralwidth for I/O, up to 1440interconnects can be formedat 0.2mm pitch. Thesenumbers of I/O are enoughto meet future wide I/Omemory requirements.Pitch(mm)Figure 1: BVA PoP design features.Manufacturing ProcessA 432 I/O BVA PoP daisy-chain testvehicle was designed and fabricatedthat measured 14mm x 14mm withtwo perimeter rows of palladiumcoatedcopper wires at 0.24mm pitchwith a wire diameter of 50µm and aheight of 0.4mm. This test vehicle hasan interconnect aspect ratio (height/diameter) of 8 and pitch ratio (height/pitch) of 1.7, which is better than anyexisting PoP technology.The process flow for the BVAPoP consists of stacking a memorypackage over a logic package withBVA interconnects. The top (memory)package is similar to current memorypackages, including high I/O BGA. Forexample, four memory chips with eachbeing x32 can be packaged to form ax128 BGA package. With higher I/O,wide I/O memory can also be used. Thebottom package has the logic deviceNo. of interconnect rows2 3 4 5 60.50 200 288 - - -0.40 248 360 - - -0.30 336 492 640 - -0.25 408 600 784 960 -0.20 512 756 992 1220 1440Table 1: Maximum possible interconnects as a function of pitch.Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]29

in conventional flip-chip format, withthe BVA wires around the periphery.The molding with wires is alsodifferent. Finally, stacking is done usingconventional surface mount technology(SMT) with the condition that the topmemory package has fine pitch BGA.The four unique process steps areexplained below.Forming the BVA CopperInterconnect. The free-standing wirebondsare the most important feature ofBVA PoP. Forming the wire-bonds withthe tips having good positional accuracy(x and y) and uniform height (z) areimportant in enabling very fine pitch andhigh yield package assembly. Figure 2shows bottom package substrate withthe flip-chip attached logic chip andBVA around the periphery.BVA tips with aconsistent desiredheight.A filmassistedmoldtechnique was usedto expose the tips.It isa mature technologycommonly foundin many packagingassembly operationsand stable suppliersupport. The processuses a mold chasedesign with mold cavities only slightlydeeper than the formed Cu wires. Whenthe mold is clamped to the substrate,Figure 3: Wire-bond tip measured position data.( a ) ( b )Figure 4: Wire tips a) before and b) after wet etch.Connecting Top Package to ExposedWire Tips. The last step is to stack thememory package on top of the logicpackage, as shown in Figure 5. Thisprocess is very similar to conventionalPoP assembly where solder paste isprinted on the main board, the logicpackage is placed on the board, thememory package is dipped in solder fluxand placed on top of logic package, andthe stack is reflowed along with othercomponents on the board. An underfillmay be dispensed along the peripheryof the stack for high reliability underdynamic loading. Good joints wereobtained across all interconnects overthe whole package, as shown in Figure 6.Figure 2: BVA interconnects (free standing wirebonds)at 0.24mm pitch around the periphery ofthe bottom (processor) chip.The x, y and z positional accuracydata is shown in Figure 3. The resultsgiven in these graphs depict data from43 packages with each data point on thegraph representing all the wire bondsin one package. The average data iswithin 20µm for all x, y and z positions,which translates to better than ±10µm.The wires were also bonded well, andan average of greater than 15 grams wasobtained from bond pull test.Molding and Exposing theInterconnect. The next step is to moldthe logic package while exposing thethe Cu wires are pushed into the moldfilm. The mold cavity is filled withthe molding compound, the moldingcompound is cured, the mold is openedand the mold film is pulled away fromthe package exposing the wire tips.The mold film thickness determinesthe wire tip exposure. Some processdevelopment was needed to optimize thewire tip exposure. No special moldingparameters were needed to providerepeatable wire tip exposure results.The target value was 0.12mm and thisheight was obtained within a toleranceof ±10µm.Cleaning wire tips with RobustSurface Finish. The wire tips need tobe cleaned after molding and varioustechniques such as wet blast andchemical etch were used. The bestresults were obtained with wet etch asshown in Figure 4. The exposed wireheight increased uniformly by about10µm because of this cleaning step.Figure 5: Assembled BVA PoP.ReliabilityA full suite of reliability tests weredone and the results are summarized inTable 2. The moisture sensitivity level(MSL) 3 test was done for individualmemory and logic packages. The hightemperature storage and unbiasedautoclave tests were done as PoP(memory package stacked on logicpackage) with underfill between them.The board level thermal cycling and30Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

( a ) ( b ) ( c )Figure 6: a) 3D CT scan image of the BVA PoP; b) 2D CT scan image of the BVA interconnect; and c) SEMimage of the BVA to solder joint cross section.drop tests were done with PoP on thetest board with underfill. The underfillwas used for all cases since this is acommon implementation in phonesand other mobile devices. All the testspassed without any failures. The droptest was extended up to 128 dropsbefore stopping the test and no failureswere detected.To study the effect of copper-tindiffusion between the copper wireand the solder ball, accelerated testingwas done by evaluating the amountof intermetallic formation under hightemperature storage test (3x solderreflow cycles followed by 230 hoursat 175 0 C). To inhibit diffusion andintermetallic formation, thecopper wires were coatedwith palladium. Figure 7shows that wet etch methodhas not damaged the wiretip palladium coating, whichhas served as an effectivebarrier against intermetallicgrowth, whereas the wet blastmethod has damaged thecoating leading to extensiveintermetallic growth.SummaryMobile computingrequirements driven by multicore,low power and cloudcomputing trends have placed a highpremium for high processor-memorybandwidth through a very large numberof interconnects with short physicallength. To meet this challenge, aninterconnect technology is presentedthat is based on wire bonds and can beutilized in different applications suchas 3D packaging, embedded packaging,Figure 7:The wet etch cleaned wire tip a) before and b) after hightemperature storage test, and the wet blast cleaned wire tip c)before and d) after high temperature storage test.Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]31

Test Standard Test condition Sample size Evaluation ResultMoisture IPC/JEDEC- 125 0 C for 24hrs; 22 logic and C-SAM Passsensitivity J-STD-020C 30 0 C/60% RH for 22 memory inspectionsLevel 3192 hrs, 3X Pb-free packages at T0 andHigh temp.storageUnbiasedautoclaveJESD22-A103DconditionB22 PoP offboardJESD22-A102DconditionDreflow150 0 C,1000 hours121C/100%RH/2atmfor 168 hoursTable 2: Current status of BVA PoP qualification testing.wafer-level packaging, etc. The keybenefits of this technology are as follows:High performance. Ultra-high I/O(quad-channel+) between the bottomDrop test JESD22-B111 >30 drops, 1500 G, 20 PoP on0.5 msec of half sine board withpulseunderfillTemp. cycling(board level)22 PoP offboardJESD22-A104DCondition GMSL3 and then-40 0 C to 125 0 C ,1000 cycles45 PoP onboard withunderfillpost-MSL3E-test after Pass168, 500and 1000hoursE-test after96 and 168hoursPassIn-situ Pass (128monitoring drops)In-situ PassE-test up to1000 cycleslogic package and the top memorypackage offers a greater than 12.8GB/s bandwidth through a >1000 logicto memory interconnects package ata 0.2mm pitch in a standard 14mm x14mm package.PoP approach. This approach hasbeen independently sourced, packaged,and tested logic and memory for highyield and supply chain flexibilityMemory compatibility. Thetechnology uses current LPDDR2 andLPDDR3, while being scalable to wideI/O memory devicesHigh-level package reliability andlow cost. The method uses establishedassembly equipment, processes andmaterials with completely molded topand bottom packages for low warpageand standard SMT for high yield.BiographyIlyas Mohammed received his PhDfrom the U. of Texas at Austin anda BTech from the Indian Institute ofTechnology, Madras, India, both inaerospace engineering. He is a Sr.Director and Principal Technologistat Invensas Corporation; emailimohammed@invensas.com32Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

Supply Chains for High-Volume Manufacturing of 3DIC IntegrationBy John H. Lau [ITRI]3D IC integration istaking the semiconductorindustry by storm. It has been: (a)impacting the chip suppliers, fablessdesign houses, foundries, integrateddevice manufacturers, outsourcedsemiconductor assembly and test,substrates, electronic manufacturingservice, original design manufacturers,original equipment manufacturers,material and equipment suppliers,universities, and research institutes;(b) attracting the researchers andengineers from all over the world to goto conferences, lectures, workshops,panels, forums, and meetings to presenttheir findings, exchange information,look for solutions, learn the latesttechnologies, and plan for theirfuture; and (c) pushing the industryto build standards, ecosystems andinfrastructures for 3D IC integration.This is a perfect storm! People andcompanies think that Moore’s Law isgoing to take a bow soon and 3D ICintegration is the next one. In orderto prepare for their future and havea competitive edge, they have beeninvesting heavily on both human andphysical resources for 3D IC integration.The potential applications and highvolumemanufacturing (HVM) of 3D ICintegrations is shown in Figure 1 [1].Basically, it can be classified into fourgroups, namely: memory-chip stacking,wide I/O memory (or logic-on-logic),wide I/O DRAM, and wide I/O interface(or 2.5D IC integration).Memory-Chip StackingThe drawing and sample in the far-leftof Figure 1 show the simplest exampleof memory-chip stacking published bySamsung in 2006. These chips could beDRAM (dynamicrandom-accessmemory) orNADA Flash withless than 100 I/Os(78 to be exact).Even with eightchipstacking, theirtotal thickness(560μm) is stillless than that ofan ordinary chip(this is significant).This memorychipstack isattached to anorganic substrate.Unfortunately,Memory-ChipStackingUnderÞll is needed between the active/passive TSV interposer and the organic substratedue to cost issue and competing wirebonding technology, memory-chipstacking with TSVs is not in volumeproduction today for consumer products.Currently, Samsung is shooting for thenext-generation server products andmost likely is considering going withthe DDR4 (double data rate – type 4)SDRAM (synchronous DRAM).Wide I/O Memory or Logic-on-LogicThe second column on the lefthandside of Figure 1 shows a wideI/O memory, which consists of lowpowerconsumption and widebandwidthmemory usually with morethan thousands of interface pins. Thismemory is supported by a CPU/logicor SoC with TSVs, which is called anactive interposer. This wide I/O memorymodule is attached to an organicsubstrate. Since mobile productssuch as smartphones want it, sampleshave been made and published by, forexample, Samsung. Unfortunately,the readiness of the fabless supplyWide I/OMemoryØ DRAM or NAND Flash Ø Wide bandwidth/low Øwith TSVs stacking on power memory onorganic substrate CPU/Logic/SoC withØ Over molding DRAM TSVsor NAND Flash Ø Logic on Logic with ØTSVsØ UnderÞll is neededbetween active chipsWide I/ODRAMDRAM with TSVsstacking onLogic/SoC withTSVsOver molding theDRAMsOrganic SubstratePCBFigure 1: Potential applications and high-volume manufacturing of 3D ICintegration.chain infrastructure, including industrystandards, supply chain businessmodels, and competitive pricing, takestime and is not here yet! Logic-on-logicfalls into this category.Wide I/O DRAM (HMC)The third column on the right-handside of Figure 1 shows a wide I/ODRAM. Samsung has been publishingmany papers on this topic for at leastthree years [2] and finally, at the 2011IEEE ISSCC in San Francisco, thecompany showed the sample of twoDRAMs on a master controller logicchip (or SoC) with TSVs, which is calledan active interposer. For this DRAM,the number of TSVs and interface pinsis slightly more than one thousand. TheJEDEC standard defines this structureas having 1200 I/O pins in four channels(http://www.jedec.org/). This wide I/ODRAM module is attached to an organicsubstrate. Recently, the Hybrid MemoryCube (HMC) consortium, whichincludes such companies as Micron,ØØWide I/OInterfaceMooreÕs law chipson a passiveinterposer withTSVsUnderÞll is neededbetween chips andthe interposerChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]33

Figure 3: Critical steps and ownerships for (face-to-face) wide I/Omemory using the TSV via-middle fabrication process.fabricated by the via-last (from thebackside) process should be avoideduntil these issues are resolved.Based on the above discussions, itseems that for active device wafersbeing used for 3D IC integrationapplications, TSVs are better fabricatedusing the via-middleprocess. Also, theTSVs should befabricated by thefab, where all theequipment andexpertise alreadyexist and the cost tofabricate the TSVs isless than 5% of thecost in fabricating the (32nm) device wafers!How Aboutthe Passive TSVInterposers: Whenthe industry definedthe TSV processesfor 3D IC integration,there were no passiveinterposers yet. Also, since thereis no active device in the passiveinterposers, they don’t fit into any of thepreceding categories!Who Wants to Fabricate the TSVfor Passive Interposers: Both the faband OSAT want to do it! It dependson the layout, design, and fabricationcapabilities, especially the line widthand spacing of the RDLs. Usually, afew microns of line width and spacingcan be done by the OSAT. Otherwise, itshould be done by the fab.B) Who Does the MEOL. For thethicknesses of memory-chip stackingand DRAMs in HMC, and active andpassive interposers under consideration,all the TSVs fabricated are blind vias.The blind TSV wafer is followed bysolder bumping/temporary bonding/back grinding/TSV revealing/thinwafer handling/debonding/cleaning,which, taken together, are called MEOL(middle-end-of-line). In this study,except for the vertically integratedcompanies (e.g., TSMC and Samsung),it is better for the MEOL process flowto be performed by the OSAT.C) Critical Steps and Ownershipsfor HVM of 3D IC Integration.C.1) Wide I/O Memory (Faceto-Back)by the TSV Via-MiddleFabrication Process: Figure 2 showsCompression, SMT, &Thru-Hole PCB MountingLead pitches as low as 0.4mm, up to 125,000 insertions.QuickOn/Off LidFully automated or manually operatedsolutions to test any lead pitch & IC packageQuick TurnLow NRECustom Test FixturesEasy Screw - Lidremoved to show detail.Easy KnobconfigurationMulti-Cavity SocketsSignificantly reduce your socket& labor costs with these multipleIC test and burn-in solutions.1-800-232-7837EMULATIONTECHNOLOGY, INCwww.emulation.comChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]35

the critical steps and ownerships forthis process. After FEOL (to pattern thedevices) and MOL (to make the metalcontacts), the TSVs are fabricated byfive key steps, namely via formation bydeep reactive ion etch [10], dielectricdeposition by plasma enhance chemicalvapor deposition, barrier and seed layerby physical vapor deposition, Cu-fillingby electroplating [11], and chemicalmechanical polishing (CMP) to removethe overburden Cu [12]. These stepsare then followed by the build upof the metal layers, and finally, thepassivation/openings (BEOL). All thesesteps should be done in the fab.The MEOL starts off by under bumpmetallization (UBM) and C4 ordinarywafer bumping with solder to the wholewafer. It is followed by temporarybonding of the TSV wafer to asupporting (carrier) wafer with adhesive[13, 14]. The next step is back grindingof the TSV wafer to a few micronsfrom the tip of the Cu-filled TSV. Thisis followed by silicon dry etching to afew microns below the tip of the CufilledTSV. After that, a low temperatureisolation SiN/SiO 2 deposition is appliedto the whole wafer. Then CMP is usedto remove the SiN/SiO 2 and the Cu andseed layers of the Cu-filled TSV (Curevealing) [12, 15]. Finally, a UBM isbuilt on the tip of the Cu-filled TSV. Allthese steps should be done by the OSAT.Separately, the memory wafer is microbumped with tiny solder bumps [16] orCu-pillars with solder caps [17]. Thenthe wafer is diced into individual chipswith micro bumps/Cu-pillars. Thesesteps also should be done by the OSAT.Next is chip-to-wafer (C2W) bonding[18, 19], i.e., the micro bumped memorychip is bonded (either by natural reflowor thermal compression) to the TSVwafer with the carrier. After face-tobackC2W bonding, the carrier waferis debonded from the TSV wafer. It isfollowed by dicing the TSV wafer intoindividual TSV modules. This TSVmodule is solder (natural) reflowed ona package substrate, then tested. Allthese C2W bonding, dicing, assembly,and testing steps should be done bythe OSAT.C.2) Wide I/O Memory (Face-to-Face) by TSV Via-Middle FabricationProcess: The FEOL, MOL, TSV, andBEOL processes are exactly the same asthose done in the TSV via-middle (faceto-back)process. However, the processesthat follow it are different. Instead of C4ordinary wafer bumping with solder afterthe UBM, the TSV wafer is temporarilybonded to carrier #1. Then, back grindingof the TSV wafer is done and the Cureveal and UBM are accomplished.Those steps are followed by C4ordinary wafer bumping with solderand temporary bonding to a secondcarrier #2. Then carrier #1 is debondedfrom the TSV wafer and C2W (face-toface)bonding is performed. After C2Wbonding, the carrier #2 is debondedfrom the TSV wafer. It is followed bydicing the TSV wafer into individualTSV modules. This TSV module issolder reflowed on a package substrate,then tested. The critical steps and theirownerships are shown in Figure 3.C.3) Wide I/O Memory (Face-to-Back) by TSV Via-Last (from theBackside) Fabrication Process: Figure4 shows the critical steps and theirownerships. After FEOL (to patternthe devices), MOL (to make the metalcontacts), and BEOL (to build the metallayers and passivation/openings), theUBM and C4 ordinary wafer bumpingwith solder are fabricated. Then, theFigure 4: Critical steps and ownerships for (face-to-back) wide I/O memoryusing the TSV via-last from the backside fabrication process.structure is temporarily bonded to acarrier wafer. It is followed by backsideback grinding, TSV fabrication andpassivation/openings, and UBM.Next is C2W face-to-back bonding,followed by debonding of the carrierwafer from the TSV wafer, and thenthe TSV wafer is diced into individualTSV modules. This TSV module issolder reflowed on a package substrateand test.C.4) Wide I/O Memory (Face-to-Face) by TSV Via-Last (from theBackside) Fabrication Process: TheFEOL, MOL, and BEOL processesare exactly the same as the (face-toback)TSV via-last (from the backside)process. However, for the face-to-facecase, after the UBM step, the devicewafer is temporarily bonded to carrier#1 as shown in Figure 5. Then, thebackside is subjected to back grinding,TSV fabrication, and passivation/openings from the backside of thedevice wafer. These processes arefollowed by UBM, C4 wafer bumpingwith solder, and temporary bonding tocarrier #2; then debonding from carrier#1 is accomplished.After the above processes arecompleted, C2W face-to-face bondingis done next. After C2W bonding, thecarrier #2 wafer is debonded from theTSV wafer and diced into individualTSV modules. The TSV module issoldered on apackage substrate,then test.From Figures4 and 5 it can beseen that the TSVcan be fabricatedby either the fab orOSAT. However,due to the logisticsof the process flow,the chance for thefab to do it is veryslim. (Once thewafer is out of thefab and processedby the OSAT, it isalmost impossiblefor the wafer togo back to the fab36Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

Solder Research KitSOLDERING TO NITINOLFigure 5: Critical steps and ownerships for (face-to-face) wide I/O memoryusing the TSV via-last from the backside fabrication process.for further processing.) Also, because of technical issues,such as hitting the various embedded alignment targets in thex-, y- and z-directions (to enable the alignment between themetal layers on the topside of the wafer and the positioning ofTSVs formed from the backside), it is very challenging for theOSAT. Thus, the TSV via-last (from the backside) fabricationprocess should be avoided until these issues are resolved.C.5) Wide I/O DRAM by TSV Via-Middle FabricationProcess: After FEOL, MOL, TSV, and BEOL of the DRAMand SoC/logic wafers, the SoC/logic wafer will go throughthe same steps as shown in Figure 2 of section C.1 for faceto-back,or Figure 3 of section C.2 for face-to-face. For theDRAMs, UBM is done first followed by micro wafer bumpingof the whole wafer. These processes are then followed bytemporary bonding to a carrier wafer, back grinding, Curevealing, and UBM. These in turn are followed by debondingof the carrier wafer and dicing of the TSV DRAM wafer intoindividual TSV DRAM chips as shown in Figure 6.The next process is C2W (DRAM chip to SoC/Logic wafer)bonding (e.g., 2-stacking, 4-stacking, 6-stacking or 8-stacking).After C2W bonding, the carrier wafer is debonded from theSoC/Logic wafer and diced into individual hybrid memorycubes (DRAM-stacking + SoC/Logic). These steps arefollowed by assembly of the hybrid memory cube with overmoldon a package substrate, then testing.C.6) Memory-Chip Stacking by TSV Via-MiddleFabrication Process: The critical steps and ownerships ofmemory-chip (either DRAM or NAND Flash) stacking areexactly the same as those of the DRAMs of the wide I/ODRAM case as shown in section C.5. However, instead of C2Wbonding as in the wide I/O DRAM case, memory-chip stackingis accomplished by stacking the individual TSV chips first andthen attaching them to a package substrate and over molded.Following these steps, the TSV memory-chip stacking moduleis attached to a printed circuit board such as the registered dualAll the materials for optimizingyour Nitinol assembly process.KIT INCLUDES:• Indalloy ® #121 96.5Sn/3.5Ag0.030” solder wire• Indalloy ® Flux #2• Indalloy ® Flux #3• Nitinol #1 wire 0.017”• Available on e-commercewww.indium.com/soldering-to-nitinolmedical@indium.comLearn more:http://indium.us/C210ASIA • CHINA • EUROPE • USA©2013 Indium CorporationChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]37

Figure 6: Critical steps and ownerships for wide I/O DRAM using the TSV viamiddlefabrication process.in-line memory modules (RDIMMs).C.7) 2.5D IC Integration with TSV/RDL Passive Interposers: Figure7 shows the critical steps and theirownerships. After the deposition of apassivation layer on a piece of dummysilicon (no active devices), the TSV canbe fabricated, RDL can be built, andpassivation/openings can be made. Afterthe UBM, the TSV wafer is temporarilybonded to carrier #1. It is followedby back grinding, silicon etching,low-temperature passivation, andCu revealing. Then, UBM, C4 waferbumping with solder, and temporarybonding to carrier #2 are accomplished.Separately, the device wafer withoutTSVs is subjected to either microbumping with tiny solder bumps, orCu-pillars with solder caps. The deviceFigure 7: Critical steps and ownerships for 2.5D IC integration with aTSV/RDL passive interposer.wafer is then dicedinto individualchips with microbumps/Cu-pillars.The nextprocesses to beaccomplishedare debondingof carrier #1,performing C2Wbonding (the devicechip to the TSVwafer). After C2Wbonding, carrier#2 is debondedand the TSV waferis diced intoindividual TSVmodules. Finally, the TSV module canbe assembled on a package substrate,then tested.It can be seen from Figure 7 thatthe TSV and RDL can be made byeither the fab or the OSAT. It dependson the layout, design, and fabricationcapabilities, especially the line widthand spacing of the RDLs. Usually, afew microns of line width and spacingcan be done by the OSAT. Otherwise, itshould be done by the fab.Except vertically integratedcompanies, such as TSMC, who wantto do the chip-on-wafer-on-substrate(CoWoS) process completely in house,most fabless design houses prefer thefab (e.g., UMC and GlobalFoundries)to make the blind TSVs and the RDLsof the passiveinterposer. Then,the fabs hand theunfinished “TSVinterposer” off to anOSAT for MEOL(solder bumping/temporary bonding/thin wafer handling/back grinding/TSV revealing/debonding/cleaning), assemblyand test. This isalso true for theunfinished TSVdevice wafers.SummaryThe technology supply chains for3D IC integration manufacturing havebeen studied. Critical steps such asFEOL, MOL, BEOL, TSV, MEOL,assembly and test, and their ownershipsfor potential applications and HVM of3D IC integrations such as memorychipstacking, wide I/O memory (orlogic-on-logic), wide I/O DRAM (orHMC), and wide I/O interface (or 2.5DIC integration), have also been providedand discussed. Some important resultsand recommendation are summarizedas follows:• For device wafers, TSVsfabricated by the via-last fromthe backside process should beavoided until the logistic andtechnical issues are resolved.• For device wafers, TSVsfabricated by the via-middleprocess is the right way to go andshould be performed by the fab.• For passive interposers, TSVscan be done by either the fab orOSAT. For ≥3μm line width andspacing RDLs, either the fab orthe OSAT can do it. Otherwise, itshould be done by the fab.• For both device wafers andinterposer wafers, the MEOL,assembly and test processesshould be done by the OSAT(except vertically integratedcompanies). It can be seen fromFigures 2 to 7 that there are manyimportant steps in the MEOL(solder bumping/temporarybonding/back grinding/TSV Curevealing/thin wafer handling/debonding/cleaning), assemblyand test; therefore, the OSATsshould strive to make themselvesready for a robust and high-yieldmanufacturing process.• In order to have a smooth handofffrom the fab to the OSAT ofthe unfinished TSV wafer, moreresearch and development workshould be performed on the testingmethods for blind TSV wafers forelectrical [20, 21], thermal, [22],and mechanical performance.38Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

Wafer-Level Test as Full Functional Test IncreasesRequirements for Spring Probes and Probe CardsBy James Brandes, Christopher Cuda [Multitest]There are many differencesbetween wafer probe andwafer-level test. Someare obvious and some are more subtle.There are both electrical and mechanicaldifferences. These differences requirethat different contact technologies beused for wafer-level test than were usedfor wafer probe.The original contact technique forwafer probe is cantilever-beam. Itis inappropriate for wafer-level testbecause it is intended for peripheralbonding pads and is not readilyadapted to either arrays of solder ballsor multiple sites. More recent waferprobe technologies are vertical probeand membrane probe. Both of theseare array-capable, but fall short inone or more categories of electricalor mechanical performance. Theserequirements dictate the use of springprobes for wafer-level test.Wafer-level test considerationsWafer-level test is final test, so theinterface must have all the electricalcapabilities traditionally associatedwith package test. The path musthave low resistance for accurate DCmeasurements. High bandwidth is arequirement for at-speed functionaltests or AC measurements. Bandwidthbeyond the third harmonic means fasterrise and fall times and crisper edgesapplied to the device and sensed by thetester. The entire path, but especially thecontactor, should have low inductancefor power delivery, to reduce the noiseon the device under test’s (DUT’s)power and ground as its currentrequirements change at its switchingfrequency. The interface must also beable to conduct significant current bothfor power delivery and for some DCparametric tests. Table 1 comparesthese parameters for various waferlevelcontactor technologies. (Datawas not available on the internet for allparameters for all technologies.)There are several importantmechanical considerations, such asforce, tip geometry, probe length,and compliance. Unlike wafer probe,in which relatively clean aluminumor copper bond pads are contactedTypeTechnologyCSP050Pogo TM ProbeMER040Spring Probe(typically in a clean room), waferleveltest makes contact to solder balls,often in a less-clean environment dueto the additional processing involvedwith adding the redistribution layer andsolder balls. Wafer-level test requiresgreater force to pierce thick tin oxidesand (potentially) debris on the solderball. Sharp probe tips are extremelyimportant for piercing the solderball to make contact to the clean tininside without affecting solderability.While probe length is not an importantparameter in and of itself, shorter probeswill generally improve all the electricalparameters mentioned above.The mechanical parameter on whichthis article is focused is compliance.(When characterizing probe cards,the term overdrive is used to describethe distance beyond initial contactthat the wafer should be plunged intothe contact set. For spring probes theterm compliance is used to describethe total travel of the probe.) Probedwafers are extremely coplanar, and littlecompliance (overdrive) is required tomake reliable contact to them.Packaging considerationsPackaging, including wafer-levelpackaging, adds significant variationMER030 [1]Spring ProbeMembrane Vertical 1 Vertical 2Inductance 1.22nH 0.9nH 1.7nH 0.2nH [2] N/A N/ADC Current @ 1.7A 1.8A 1.5A 200mA [3] 0.5A 1.6A20CContact 100mOhm typ. 70mOhm typ. 150mOhm < 200mOhm < 2Ohm N/AResistancetyp.Bandwidth 5.7GHz 18GHz 12.4GHz 20 - 33GHz 1.3GHz N/A[1]In Development [2]Tip Only [3]On SolderTable 1: Key electrical properties of various wafer-level contact technologies.to the target height. This variationis expressed on the package outlinedrawing as the Z-height tolerance ofthe solder ball. Wafer-level test contactsmust have more compliance thantraditional wafer probe technologiesto accommodate this tolerance. Thegreater the compliance of the contactset, the less effect underdriving theprobe will have. Because of its externalspringdesign, Quad Tech probes havemore compliance than traditionalFigure 1: Pogo-style probe (CSP050), and twoQuad Tech probes: MER040 and MER030 (top tobottom).40Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

probes. Figure 1 shows the relativesizes of a Pogo probe and two QuadTech probes. These probes are suitablefor pitches of 0.5mm, 0.4mm, and0.3mm, respectively.The first probe with an externalspring was the Bantam®, introducedabout thirteen years ago; thearchitecture provided improved forceand compliance in a significantlyshorter probe. The Quad Tech proberetains the advantages of the externalspring design, is more cost-effectiveto manufacture, and is scalable tothe finer pitches required for waferleveltest. Table 2 shows several keymechanical properties among variousprobe technologies that are used forwafer-level test. The compliance of themembrane probe is a bit misleading.The contact points are not individuallycompliant. In fact, if adjacent contactpoints vary by more than 0.05mm(as when there is a missing solderball) the contact set can be damagedat touchdown.In addition to the contactor, the probehead includes a printed circuit board(PCB). PCB planarity is also important.Spring probes make solderless contact tothe PCB, and these probes are preloadedon the PCB side of the contact set toprevent pad-damaging chatter with eachtouchdown. Any deviation from planarconsumes some of the spring probecompliance. As wafer-level contactorsgrow larger and test parallelismincreases, the distance between theprobes, which are furthest apart,grows. As the distance grows, planaritybecomes more difficult to achieve.The distance between the two furthestprobes is growing as higher pin countTypeTechnologyCSP050Pogo TM ProbeMER040Spring Probedevices are tested at the wafer level, andvarious test site patterns are employedto leverage the economic advantages ofwafer-level packaging and test.Controlling PCB planarity startswith the PCB's layer stack-up in thedesign. Using evenly-distributed planesFigure through 2: Copper the Thieving layer stack on a PCB and Signal adding Layernon-functional copper pour (knownas thieving) are common practicesemployed to maintain planarity. Astest speeds have increased, we haveconducted extensive tests to ensure thatthe copper pour is executed in a waythat ensures it will have no negativeeffect on electrical signal performance.Figure 2 shows an inner layer from anATE board where floating thieving hasbeen added to the blank areas of a signallayer to more evenly distribute copperacross the surface.Figure 2: Copper thieving on a PCB signal layer.Figure 3 shows an example of abalanced, mixed-dielectric stack upwhere the Rogers® brand material isused for the high speed signals, andthe Nelco® brand material is usedfor the balance. The key attributeis that the thicknesses of each arechosen to maintain symmetry fromthe center. As each material will moveMER030 [1] Membrane Vertical 1 Vertical 2Spring ProbeTest Height 6.45mm 3.3mm 3.5mm 0.065mm [2] 3 - 7mm 5.95mmCompliance 0.51mm 0.44mm 0.55mm 0.25mm 0.125mm 0.3mmMin. Array 0.5mm 0.4mm 0.3mm 0.15mm 0.15mm 0.2mmPitchForce @Test Height35g 30g 25g 16g 25g 6g @0.2mmTip Shape 3 or 4 points two points two points one point one point four pointsProbe off apex off apex off apex at apex at apex off apexMark(s)[1]In Development [2]Tip OnlyTable 2: Key mechanical properties of various wafer-level contact technologies.Figure 3: Balanced, mixed-dielectric layerstack-up.differently during lamination, keepingthe symmetrical balance minimizesthe material-mismatch impacts on theoverall warp of the PCB.When mixed laminate materials arerequired for signal integrity purposes,careful consideration must be made toensure a proper match of the laminates’resins, especially their coefficient ofthermal expansion and weave direction.A mismatch will cause excessive warpor delamination, robbing the contactorprobes of their valuable compliance andaffecting the parallelism of the contactset and the target wafer.Wafer-level package testingapplications commonly require 0.4mmball pitch. At this pitch, and with thethicknesses required for rigidity androuting layers, most PCB manufacturersrequire multiple lamination cycles.However, there is a planarity benefit tomanufacturing with monolithic books(one lamination cycle). To accomplish amonolithic build, the PCB requires highaspectratio vias. Less stress occurs onthe laminate resins of PCBs built with asingle lamination cycle. The undesirablestress contributes to PCB warp. Theexamples in Figure 4 show two differentbuild methods for a 0.4mm pitch, 49pin, 7 x 7 ball array. The pad arraydensity necessitates four signal layers toescape the DUT area. Figure 4a showsa multiple lamination approach, andFigure 4b shows a single lamination. Inthe multiple lamination approach, microvias and blind vias are used to escape theDUT pattern; the multiple laminationskeep aspect ratios low for easier plating.Single lamination requires the use ofsmaller vias, higher aspect ratios, andsmaller antipads.Regardless of the number ofChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]41

Figure 4: Comparison of a) multiple lamination and b) single lamination.lamination cycles, there is always someelement of bow and twist in a PCB aswell as the football effect. The termfootball effect was coined to describethe shape the PCB panel can takeon after lamination: The PCB panelresembles the shape of an Americanfootball, where the center of the panelis thicker than the outer edges (Figure5). We have developed a process foreliminating the football effect, calledUltraFlat. This new process improvesplanarity by subjecting the panel to aseries of polishing steps to eliminatethe height differences across the panel.The process also provides permanentimprovement to the planarity of thePCB. Other traditional processes ofimproving PCB planarity such asflat-baking only offer a temporaryimprovement. As flat-baked PCBs ageFigure 5: Comparison of an UltraFlat Board with a typical Football-Effect Boardand take on moisture from atmospherichumidity, the PCBs will return to theirpre-baked shape.Figure 5: Comparison of an UltraFlat Board with atypical football-effect board.Validation of planarity is a challengein itself. In recent years, users havetightened warpage tolerances in hopesof capturing planarity. Final test ATEboards for many years have used0.5% as the pass limit for PCB warp(>0.005"of warp per inch of diameter ofthe PCB causes the PCB to be rejected).The most common method of measuringPCB warp employs a pin gauge aroundthe perimeter of the finished PCB atopa flat granite surface. This methodis simple, but does not provide theinformation that is most important forwafer-level testing because it measuresoverall PCB warp, instead of planarityin the DUT area, which is typically inthe center of the PCB. A test interfacecan allow considerably more warp onthe outer edges of the PCB, whereas thecenter/DUT pattern planarity is mostimportant, both because of the limitedcontactor probe compliance and therequirement to maintain parallelism tothe target wafer. Therefore, planarityin the contactor area must be held to amuch tighter tolerance. We recommenda maximum warpage tolerance of 0.3%for spring probe contacts in wafer-leveltest applications. Whenever possible,Figure 6: ATE Board Flatness Measuring Techniquea DUT tolerance of 0.15% should beused for optimum performance ofthe interface.SummaryAs PCB planarity and warp tolerancesare reduced to meet the needs of futurewafer-level testing, the industry needschanges in PCB planarity validationtechniques. Current methods vary fromthe standards put forth by the IPCto customized methods that confirmthe planarity where it matters for aparticular contact technology. In thispaper, we suggest a method for waferprobe and wafer-level test that uses aheight gauge as a true measurement ofDUT-area planarity. The height gauge iszeroed on one plated pad location in ornext to the critical DUT area, and thenmeasures the height at predeterminedpads around the critical areas as definedby the user. The delta between all thepoints is used to determine a pass/failcriteria using a system of allowableunits of deviation. This output canFigure 6: ATE board flatness measuring technique.be expressed as a percentage, or as amaximum value of the delta. Becauseof the inconsistencies in commonlaminates, measuring a plated surfaceoffers a more consistent and applicationrelevantsurface height versus measuringthe laminate surface. Because of themechanical contact required for thismethod, we recommend users includedepth gauge test pads in the design thatare not electrically connected to therest of the PCB so that pogo landingpads are not touched. To eliminate theunderlying surface variability, a flatgranite block should be used as the base;then, to eliminate the bow and twist ofthe non-critical areas of PCB, use threeidentical posts at equal distances apartto hold the PCB above the surface of thegranite block (Figure 6).The unique challenges of waferleveltest require a fresh look atthe mechanical requirements of theinterface. Traditional probe technologiesand PCB construction methods canhave a negative impact on yields or testhardware life, which adds to cost of testin production.AcknowledgmentsPogo is a trademark, and Bantam is aregistered trademark of Everett CharlesTechnologies. Rogers is a registeredtrademark of the Rogers Corporation.Nelco is a registered trademark ofthe Nelco Corporation. UltraFlat is atrademark of Multitest.BiographiesJames Brandes received his BSEEfrom DeVry Institute of Technology andis a product manager at Multitest; emailj.brandes@multitest.comChristopher Cuda is in charge ofproduct development for the PCB groupat Multitest.42Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

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Package-Level Circuit Modifications UsingPlasma-FIB to Create Functional PrototypesBy Peter Carleson, Brian Routh Jr., Trevan Landin, Kenny Mani [FEI Company]Plasma-based focused ionbeam (PFIB) systems havenow been used successfully to createprototypes that incorporate packagelevelmodifications. Packaging playsan increasingly important role inimproving the performance of integratedcircuits [1]. Multichip packages allowthe integration of different types ofICs to provide better performance andgreater functionality in less space. Thisis particularly true of circuits intendedfor mobile applications where space islimited by the handheld nature of thedevice, and digital, analog and radiofrequency components must be tightlyintegrated. Equally important, signalrouting for analog and RF circuitscan have significant performanceeffects that are difficult to model andmay not become apparent until thecircuit is packaged and tested [2,3].Making design changes and creatingnew prototypes can take 1-2 weeksfor package-level modifications,whereas it takes 6-8 weeks for die-levelchanges that require new masks andnew silicon. The PFIB technology canmake modifications in less than a day,significantly shortening the design andtest cycle.FIB circuit modification has beenused for many years at the die levelwhere it allows manufacturers toimplement and test changes withoutrepeating the lengthy process of creatingnew masks and fabricating new silicon.Die-level circuit elements typicallyhave dimensions of a few micrometersor less. Modifications to features of thissize can be accomplished in a matter ofhours with conventional FIB systemsthat use liquid metal ion sources (LMIS).Circuit elements at the package levelare much larger and the time requiredto modify them with conventional FIBis prohibitively long. In some cases,the features are large enough (>100µm)to permit modifications with laserbasedsystems [4], however, advancedpackaging processes now cominginto production frequently use signaltraces in the middle range (10µm -100µm), too big for conventional FIBmodification and too small for lasers.PFIB, which uses a plasma source ratherthan LMIS, can generate higher currention beams with milling rates 20 to 100times faster, permitting modifications ofthese advanced package circuit elementswithin a practical time frame [5-8].System ConfigurationThe Vion PFIB used in the workdescribed here is configured similarlyto conventional FIB systems. Theprimary differences are the inductivelycoupledplasma source and a three lenscolumn specially designed to deliverbeam currents ranging from 1.5pA tomore than 1µA. It includes a 150mmpiezo-ceramic stage, a detector forsecondary electron and secondary ionimaging, a gas injector system (GIS)for gas assisted etching and deposition,an electron flood gun for chargeneutralization, both optical and infrared(IR) microscopes, CAD (computeraided design) overlay and navigationsoftware, job automation software, andaccess to specially adapted applicationsprotocols and methods.Comparing Liquid Metal andPlasma SourcesIn the LMIS used in conventionalFIB, a liquid metal (gallium) flowsfrom a reservoir along the surface ofa sharply pointed electrode. At thevery fine tip of the electrode a strongelectric field ionizes metal atoms andaccelerates the ions toward the sampleinto the focusing column. In a plasmasource, a gas (typically xenon, thoughother gases may be used) flows into acell surrounded by a helical antenna.The antenna couples energy into thecell, ionizing gas atoms to create aplasma. Gas ions exit the cell through asmall aperture into the extraction opticswhere a strong electric field acceleratesthem into the focusing column. TheLMIS can be considered a point sourcewith low angular intensity (0.02mA/sr). The plasma source is broader inextent but offers a high angular intensity(50mA/sr). Because the LMIS is sosmall (50nm diameter), it requireslittle or no demagnification to form asmall diameter beam, however, spacecharge effects cause strong sphericalaberrations that dramatically expandbeam diameter at high beam currents.The plasma source (which may be15µm in diameter) requires strongdemagnification to achieve small beamdiameters, but can maintain smallerbeam diameters at high currents. Below10nA, LMIS beams may have diametersas much as an order of magnitudesmaller than plasma FIB. The crossover in performance occurs at 50-60nA.Above this value, the LMIS beamdiameter deteriorates rapidly and plasmasources can deliver more current intosmaller beams. The Vion PFIB providesspatial resolution of

sputtering rates (the average amountof material removed by each ion). Theincrease is material dependent andranges from 1.0 to 1.6 times higher formaterials commonly used in integratedcircuits, with significant increases forSi, Al and Cu. The combination of 1Xto 1.6X higher sputtering rates with20X to 60X increases in beam currentresults in overall material removalrates 20X to 100X faster. The PFIBoffers clear advantages for applicationswhere fast material removal is the firstpriority, such as package-level circuitmodifications, while still preservingsolid performance at lower currents. Theincreased material removal rates reducetotal processing time for packagelevelcircuit modifications from days tohours, making PFIB a practical tool forthis application.NavigationSimply finding the circuit elementsto be modified can be challengingfor a packaged circuit. Removingthe package, a viable option forfailure analysis, is not an optionwhen trying to create a modified butfunctional prototype. Depending on theapplication, it may also be necessary tolocate the circuit elements through the“flipped” silicon substrate. An opticalmicroscope (NavCam) mounted on thesample chamber door assists with initialnavigation by providing an opticalimage registered with the coordinatesystem of the FIB when mounting thesample on the stage. The operator canuse the NavCam image to navigatedirectly to the location of interest basedon external package features suchas solder balls. Navigation softwareis available to overlay CAD data onthe image, from package level signalpathways down to circuit elementswithin the die. When needed, an infraredmicroscope provides imaging capabilityfrom the backside of the die throughthe silicon substrate. Finally, imagingwith the scanning ion beam, usingeither secondary electrons or secondaryions, provides high resolution andstrong contrast.Gas-assisted Milling and DepositionAlthough the ion beam alone willmill most materials, milling speedcan be increased by introducing smallamounts of specific gases throughan injector needle at the milling site.Because different gases increase millingrates differentially for specific types ofmaterials, this selectivity can be used torestrict milling to certain features, or tostop milling when a particular interfaceis reached.Xenon difluoride (XeF 2 ) is used inconventional FIB to enhance millingrates on silicon, especially whenremoving large volumes of the siliconsubstrate to access circuitry from thebackside of the die. In the PFIB, XeF 2 -assisted etching generates flat flooredtrenches even at 1.3µA beam currents.Volume removal rates typically rangefrom 400k to 600k-µm 3 /min, 3 to4 times faster than Ga FIB. Nwellcontrast appears in the FIB image 2 to4μm before the etch surface reachesthe circuitry, providing an effectiveendpoint for the etch process.A metal organic precursor gas (in thiscase, methlycyclopentadienyltrimethylplatinum) can be used to deposit metallines. When the gas molecules aredecomposed by the ion beam, the metaldeposits on the surface and the volatileorganic components are pumped awayby the vacuum system. Xe exhibitshigher Pt deposition efficiency (averagevolume deposited per ion) than Ga.Although the Pt deposited by PFIBexhibits higher resistivity than Ga FIB,this can be compensated by depositingthicker lines to lower total resistance.Similarly, insulators can bedeposited by using a precursor gas,such as hexamethylcyclohexasiloxaneHMCHS). Preliminary results indicatethat oxide depositions performed withXe are significantly more resistivethan depositions performed with Ga.Resistivities appear to be >>10 16 μΩ•cm.A special O 2 -assisted process has beendeveloped to etch polyimide using lowbeam energies to avoid damage. Highlytextured surfaces can form during PIremoval, but the high selectivity ofthe gas-assisted removal allows theChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]45

underlying metal or oxide to serve as aneffective etch stop.Charge NeutralizationCharge can accumulate rapidlywhen milling insulating materials withpositive ions, ultimately interferingwith milling and imaging processes. Adefocused electron flood gun directedat the milling site supplies electrons toneutralize charge buildup.Application examples. Figures 1through 6 illustrate application examplesof package-level device editing.Figure 1 shows a sample that hasbeen tilted to show the cut more clearly.The access window is several hundredmicrons in length. The process took30 minutes to pump down, align, andcut with the Xe beam, and another 3minutes for XeF 2 cleanup. The openingwas subsequently filled with a 5 minuteinsulator deposition so that when thesolder is re-flowed it does not flow intothe cut box.Figure 2a shows CAD data that hasbeen overlaid on the FIBimage to locate a buriedsignal line and an accesswindow has exposed theline. Figure 2b is a closeup of the access windowin which the copper line isvisible crossing diagonallyat the upper right corner.Figure 2c shows that theline has been cut and thecopper completely removedleaving the underlyingfiberglass filaments andepoxy substrate visible at the bottom ofthe hole.Sometimes complex etch anddeposition patterns are needed as shownFigure 1: a) (left) The redistribution layer is visualized with CAD overlay and the cut is defined; and b) (right)An FIB image showing the access window milled through the overlaying solder mask and the cutRDL below.in Figure 3. On the left, two circular (1and 2) and two rectangular patterns (3and 4) are combined to create exclusionzones to protect deposited platinumfrom cleanup while preventing shortingto other components. On the right isan example of via isolation from thecopper pad using a donut-shaped dualFigure 2: a) (left) CAD data has been overlaid on the FIB image; b) A close up of the access window; and c)The line has been cut and the copper completely removed.Figure 3: a) Two circular (1 and 2) and two rectangular patterns (3and 4) are combined to create exclusion zones; and b) An example ofvia isolation from copper pad using a donut-shaped dual concentriccircle pattern.concentric circle pattern that enablesvisual verification of the completeseparation between the pad and the via.This is the simplest method of disablinga via/pad connection. PFIB providesbetter accuracy than previously obtainedusing a laser. The outer diameter is75μm, the inner diameter is 50μm. Theprocess took less than 5 minutes at abeam current of 0.57μA.Plasma FIB modifications arenot limited to substrate alone andcan be executed directly on thecircuitry of wafer-scale packages. Theinherent challenges of FIB millingthrough polyimide can be overcomewith optimized choices of current,accelerating voltage and gas, enablingmodification directly onto the die.Figure 4a shows the Pt jumper, severalhundred microns long, deposited directlyon top of the polyimide. Figure 4b is aclose up near the left end of the jumpershowing the cut buried signal line.Figure 4c is a close up of the connectionat the right end of the jumper.In this modification shown in Figure5, a probe was used to temporarily movegold bond wires, providing access tocopper traces below, which needed to beswapped at the bond fingers. The imageshows the nudged wires and the initialbeam-deposited platinum connection.The gas injector nozzle is visible in theupper right corner of the image.Figure 6 shows a complex signalswap with the cutting of adjacenttraces and re-routing of signals usingdeposited metal lines and insulation. Afinal coating of insulation will preventcorrosion and shorting.46Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

Functional Testing of 0.3mm-pitch Wafer-LevelPackages to Multi-GHz SpeedBy Ila Pal [Ironwood Electronics]Today’s electronic packageshave high clock speeds(in the multi-GHz range), fine pindensities (below 0.4mm pitch) and highpin counts (over 1000). When thesepackages are assembled onto a printedcircuit board (PCB), they performcertain functions at a certain speed.Socketing is one of the avenues to testthe functionality of IC packages withoutdamaging them. Socketing these highspeedand high-density IC packagesrequires an innovative solution to thechallenges of designing a shorter signalpath (less resistance), good electricalinsulation (prevents signal loss), andproper thermal management. Design ofthe socket is dictated not only by thefunctions mentioned above, but alsoby other parameters such as durability,power consumption, assembly methods,and the environment in which thesystem will operate. The Silver BallMatrix (SM) GHz socket (Figure 1)provides a solution that is fast, denseand durable.Figure 1: Silver Ball Matrix (SM) GHz socket.Socket FunctionA socket can be defined as anelectromechanical device that providesa removable interface between the ICpackage and system circuit board withminimal effect on signal integrity. Havinga removable interface is the major reasonfor using a socket and it is required fora variety of reasons, including ease ofassembly, reworking, upgrading and costsavings. The cost advantage is saving theIC by not attaching it permanently to thePCB. The socket is semi-permanently(solder-less) attached to the PCB,while the IC device can be inserted intoor removed from the socket withoutdisturbing the connections to the PCB.A socket helps to test, evaluate andinspect the complete system. Socketsalso allow for maintenance, testing, andreplacement or upgrades in the field.This in the field capability becomes acritical factor because of the pace oftechnology evolution.A GHz Socket SolutionWe have developed a sequel to thestandard GHz socket that can test ICpackages with a 0.3mm pitch. The SMGHz Socket provides a range of highspeed,high-density socket solutionsfrom very compact production socketsto robust test and prototype applications.A cross section photograph revealingSM contacts is shown in Figure 2. Thesockets are designed such that force isevenly distributed on the top of the IC,pushing the solder balls into very highspeed, Z-axis, silver ball columns. Thenew contact has precise silver balls heldtogether by a proprietary conductiveFigure 2: Cross section of SM contacts.formulation. These conductivecolumns (diameter optimized for 50ohm impedance) are suspended ina nonconductive flexible elastomersubstrate with a patented solid corefor enhanced durability and reliableperformance over time, temperatureand cycles. This flexible substrate iscompliant and resilient and enables theconductive columns to revert back totheir original shape when the force isremoved. Elastomer is the only mediumbetween the IC package and the circuitboard. A heat sink screw and the socketbody provide heat dissipation for the ICin the socket. Precision guides for theIC body and solder balls position thedevice for connection.Mechanical CharacterizationRemovable interface requirementsare generally stated in terms of theinsertion/extraction force and number ofinsertion/extraction cycles a socket cansupport without degradation. Insertion/extraction forces become increasinglyimportant as the pin count of thedevice increases. Additionally, as theICs are direct silicon (wafer), they arevery delicate as opposed to enclosedpackages, so the insertion force is alsoan important consideration. The firsttest examines the relationship betweendeflection of the contact, force andthe contact resistance. A displacementforce (DF) test station was used tomeasure the contact deflection and itscorresponding force. Force increaseslinearly as the displacement increases.Similarly, the contact resistancedecreases as the force increases. Astable contact resistance has to beidentified based on the minimum forcerequired. A desired displacement has tobe identified based on the compliance48Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

equirement of each device/application.This information is very important forthe test engineer to set up failure criteriawhen performing the device test usingthis contact technology.The second test examines therelationship between contact resistanceover contact life cycle count. An actualhandler was used for this experiment. Acontact set consisting of 44 leads and 16ground leads (QFN configuration) wasmounted on the test board, which wasthen connected to a tester. A gold-platedshorted device simulator was mountedon the plunger head. The test set up wasadjusted such that the head moved down0.3mm, which was the chosen travel forthe SM contact. Initial contact resistancedata was measured via the tester and theautomatic test equipment (ATE) wasturned “on.” This moves the plungerback and forth, which in turn cyclesthe SM contact. A digital counter wasinserted into the test setup to measurethe cycle count. The test setup includesa cycle speed of ~2,500 actuations/hour,a dwell time of ~0.7s, and is conductedat ambient temperature. The test vehiclewas designed for a 7x7mm 44 lead,0.5mm QFN shorted device simulator.No cleaning was performed to the goldplateddevice under test (DUT) or tothe SM contact. Contact resistance datacollected at different cycle intervals isshown in Figure 3.It can be seen from the graph that theaverage contact resistance is less than25m-Ohms over 1,000,000 cycles. Thestandard deviation was also shown toprovide an understanding of the dataspread. Based on the graph, it can beconcluded that the contact operatesover 1,000,000 cycles with 25m-Ohmsaverage contact resistance. Theexperiment was repeated with differentCRES(Ohms)lots manufactured atdifferent times. Thedata is consistent overthe different lots exceptthe average is shifteddown by 5m-Ohms.This shows that theprocess variations cancause a shift in contactresistance within5m-Ohms. Similarly,the contact was testedat various temperaturesand the acceptablerange was defined as-50C to +150C.Electrical CharacterizationElectrical requirements are generallystated in terms of the bandwidth andcurrent carrying capacity. Currentcapacity is determined by injectingdrive current in steps of 10mA to amaximum value of 5A. For temperatureas a function of resistance, dwell time isset to 3 minutes per data point to allowtemperatures to stabilize. Results areshown in Figure 4. From the graph, itcan be seen that for a 4A continuouscurrent, the temperature rise is 14C. It isimportant for the test engineer to knowthat there is no joule heating effect dueto the contact’s base structure.Measuring the bandwidth at final testdetermines if this contact technologyis right for a particular test application.Bandwidth is typically specified interms of insertion and return loss. Avector network analyzer is used for thisexperiment. A signal is sent from port1 (top of the contact) and received atport 2 (bottom of the contact). Signalreflections are measured and reported asS21 curves (Figure 5).An insertion loss of -1dB @ 40GHzCyclesFigure 3: Contact resistance data collected at different cycle intervals.Figure 4: Temperature as a function of drive currentis interpreted as 90% of the signalpass through the interconnect mediumand only 10% of the signal is lostthrough the interconnect transition at40GHz. It is important to note that theIC functionality is being verified at aspecific frequency.Insertion Loss - 1dB @ 40GHzFigure 5: Signal reflections measured andreported as S21 curves.SummaryA primary concern to anyone utilizinghigh-density WLPs is that the socketmust provide a high performance,low and stable value of resistancewhile meeting mating requirements.In particular, the mating force and thenumber of mating cycles the socketcan withstand without degradationare key. SM GHz sockets addressthese concerns.BiographyIla Pal received his MSME fromIowa State U. and an MBA from St.Thomas U. He is VP of Marketingat Ironwood Electronics; emailila@ironwoodelectronics.comChip Scale Review Jan/Feb 2013 [ChipScaleReview.com]49

INTERVIEWDeca Technologies : Growing Up in Tough TimesAfter a year of being in virtual stealth mode, interconnect start-up DecaTechnologies recently launched its second product family, the M-Series,an embedded die packaging technology featuring its proprietary AdaptivePatterning software technology. Chip Scale Review talked to Chris Scanlan,VP of product management, about the company’s first full year in business,recent accomplishments, and future plans for the company.CSR: The company was launchedduring one of the worst worldwideeconomic crises. What has it been liketo become a player in the advancedpackaging sector and to rampproduction under these conditions?CS: We have been very fortunate tohave customers respond favorably toour value proposition, which is basedon a fundamentally different way tomanufacture wafer-level interconnect.Our focus has been to achieve ourdevelopment milestones on schedule,and to complete qualifications and initialproduction ramp for our launchingcustomers. As a start-up, our successthus far has been largely a function ofour ability to execute. We have beenless affected by macroeconomic cycles.CSR: Market analysts have predictedthat 2013 will be the beginning ofan upturn in the industry, drivenby the demand for mobile andwireless devices. Many technologyadvances are expected to address theperformance, power and form factorneeds of these devices. How is Decapositioned to address this demand?CS: Our launching product line is afan-in wafer-level chip-scale package(WLCSP), as well as the requisite testand die finishing services. WLCSP is oneof the fastest growing semiconductorpackage types, particularly in mobileand wireless applications. We are ableto take advantage of this trend with adifferentiated service offering focusedon speed, flexibility, and lower costof-ownership(CoO). Our factory wasdesigned from the ground up with theflexibility to run 200mm or 300mmwafers without change-over, so wehave the capability to respond quicklyto changing demand without dedicatedcapital investment. Our new M-Seriesfully molded CSP is positioned to offerthe electrical and thermal benefitsof flip-chip CSP with the smallestpossible form factor and a cost thatis competitive with wire bond BGAs.We’re already seeing strong interest inthe technology, particularly for mobileand wireless applications.CSR: The M-Series has beencompared to fan-out waferlevelpackages (FOWLP) like theembedded wafer-level ball grid array(eWLB), yet it is structurally differentthan eWLB. What are the maindistinctions between the M-Seriesand FOWLP? What are the targetapplications for the M-Series?CS: M-Series is a fully encapsulated,rugged package structure that hasthe look and feel of a molded flipchipCSP package (Figure 1). Boththe structure and the manufacturingprocess have been designed to avoidthe chronic issues with typicalFOWLP technologies. The balancedstructure allows us to avoid excessiveFigure 1: M-Series fully molded device structure.panel warpage and eliminate nonvalueadded steps typically requiredto maintain panel flatness. The dieis fully protected by epoxy, and thepanel level redistribution is performedon a flat surface with no die-to-moldcompound transition. This simplifiesthe copper redistribution layer (CuRDL) patterning process and allowsus to apply advanced design rules tothe entire unit (Figure 2). The panelformat has been co-designed with ourWLCSP manufacturing infrastructureto allow M-Series panels to run throughour process interchangeably with Siwafers. This increases capital efficiencyand avoids costly conversions. We havealso developed a proprietary patterningFigure 2: Cross section view of the M-Series.50Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

technology that finally resolves thedie-shift problem, resulting in bothhigher interconnect yield and higherdie-attach throughput.M-Series is ideal for devicesrequiring the smallest possible formfactor (x,y, and z) that are unable toutilize conventional fan-in WLCSP.Its electrical performance andminiature outline offer an attractivealternative to flip-chip and wire bondBGAs, CSPs in smartphones, or otherhigh-density applications.CSR: In your paper at IWLPC, youdescribed the Adaptive Patterningprocess. Can you briefly summarizehow that works? Can it be applied topackages other than the M-Series?CS: Adaptive Patterning is actuallya suite of design and manufacturingtechnologies that resolves the die-shiftproblem that has plagued embeddeddie technologies for two decades. Theprocess of embedding an array of diein a substrate panel or molded waferresults in some variability or shift of thedie with respect to the target position.When you then try to align a routingpattern to the entire panel, or to aportion of the panel, the interconnectpads on the die don’t perfectly align totheir respective vias and capture padsin the build-up routing layers. This canresult in yield loss. Typical solutionsto the die-shift problem include usinghigh-accuracy, slow speed die-attachmachines and modifying chip designs toincrease the size of the die bond pads.The adaptive patterning processworks by dynamically adjusting aportion of the RDL pattern to accuratelyconnect to the bond pads or otherstructures on each individual die in theembedded die panel. After placing anarray of chips on a panel using a highspeed placement machine, the actualposition and rotation of every die on thepanel is measured. This data is ported toa proprietary design tool that adjusts thefan-out unit design for each package onthe panel so that the via layers or RDLpatterns are properly aligned to bondpad features on the die. The individualpackage designs are then combined toform a drawing of the full panel for eachof the layers that need to be adjusted,typically including the first via layer onthe panel and the first RDL layer. Thedesigns for each panel are transferredto a lithography tool, which uses thedesign data to dynamically apply acustom, adaptive pattern to each panel.The under bump metallurgy (UBM)pads are held constant to maintainconformance to the package outlinespecifications. Adaptive Patterningallows us to target smaller bond padsassociated with advanced Si nodes withhigher yield while using lower cost,faster die placement equipment. It alsoBiTS Workshop Interconnectology Talk ShowFeatures Deca’s Tim OlsonThere is a grass-roots initiative tointroduce terminology that betterdefines processes used to build thenext-generation of IC devices. “Theterm ‘wafer-level packaging’ is givingway to “electronic interconnect” asit’s the interconnect technology thatprovides the value-add at the systemlevel to packaging technologies,”notes Tim Olson, CEO ofDeca Technologies.Olson will join fellow“interconnectologists,” Scott Jewler, ofANSI, Simon McElrea, of Invensas, andsemiconductor technology consultant,Ira Feldman, Feldman Associates,as guests on the‘Talking Points’ talkshow on “Interconnectology” at BiTS2013, March 4 at 1pm. The show ishosted by Queen of 3D, Françoise vonTrapp, 3D InCites, and co-produced byImpress Labs.allows us to design M-Series arounddie that are designed for wire bond orflip-chip interconnect without imposingspecial constraints on the chip design.This technique could be applied toany embedded die process wherein dieare placed in a fixed position beforeforming an interconnect pattern over thedie. This would include embedded chipin substrate and FOWLP, among others.CSR: What’s next on the drawingboard?CS: Deca’s approach is to identifyseemingly insurmountable problemsthat are holding back the industry, andthen to challenge all core assumptionsen route to a solution. Our first productoffering, a fan-in WLCSP, is structurallysimilar to industry standard WLCSPofferings. Under the hood, we havecompletely rethought the wafer-levelinterconnect manufacturing process.We drew inspiration from SunPowerCorp. to create a flow-line approach towafer-level processing to break downthe capital cost and manufacturingcycle time barriers. With M-Series, weleveraged our wafer-level manufacturingapproach and added innovations inpackage structure, design methods andsoftware, patterning technology, andinspection methodologies. M-Series willstart production in 2013. Future productannouncements will see our waferlevelprocessing capabilities applied toincreasing levels of Si integration.CSR: How do you see 2013 unfoldingfor the industry as a whole andfor Deca? What is the company’sstrategy for future growth?Demand for WLCSP and other formsof wafer-level interconnect willcontinue to grow at a healthy rate.Deca is positioned for strong growth in2013. We will be focused on rampingproduction volume on our currentWLCSP offering, as well as launchingour M-Series into production.Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]51

Product NewsRudolph Unveils 2X ReductionStepper Total Lithography System;Announces Azores AcquisitionRudolph Technologies enteredthe back-end advanced packaginglithography market with the release ofits JetStep Lithography System thatfeatures a 2X reduction stepper. The newsystem was developed in conjunctionwith the company’s acquisition ofWilmington, Massachusetts-basedAzores Corp. The product announcementand acquisition were announced byRudolph in tandem. According toRudolph, the company has combinedits knowledge of advanced packagingand an established tool set for back-endmanufacturing with Azores’ proprietarytechnology and numerous featuresdeveloped for the flat panel market intoa solution that has not been utilized inthe semiconductor market before.The company further noted that theacquisition expands its business modeland enlarges its role within the advancedpackaging market. It is anticipated thatJetStep Lithography Systemthe acquisition – one of several plannedsteps the company is taking to expandits portfolio – may result in more thandoubling its total addressable back-endmarket. The terms of the deal were notdisclosed, but the acquisition was an allcash transaction, utilizing less than 10%of the company’s cash. It is expectedthat the new Lithography Systems Group(LSG) will account for approximately10% of Rudolph’s revenues in 2013,the first year of its manufacturing ramp.LSG is forecast to be accretive withinits first year.ICOS ® WI-2280 Wafer InspectorKLA-Tencor Launches ICOS ® WI-2280 Wafer Inspector for LED andAdjacent MarketsKLA-Tencor Corporation hasannounced its next-generation lightemittingdiode (LED) patterned waferinspection tool, the ICOS WI-2280. Designed specificallyfor defect inspection and 2Dmetrology for LED applications,the ICOS WI-2280 also providesenhanced inspection capabilitiesand increased flexibility formicroelectromechanical systems(MEMS) and semiconductorwafers spanning two inches toeight inches in size.The ICOS WI-2280represents the company’sfourth generation LED waferinspection system and it isbuilt on its WI-22xx platform.The tool supports handling of wholewafers in carriers and diced wafersin hoop ring or film frame carriers toaccommodate multiple media withminimal equipment changeover time.The WI-2280 also features an enhancedrule-based binning defect classificationand recipe qualification engine, enablingmanufacturers to achieve faster yieldlearning during production ramps, aswell as improve process control andprocess tool monitoring strategies intheir manufacturing process.HITACHI Solder Paste Printers,Koh Young SPI SystemsInterface for ‘On-the-Fly’ PrintProcess OptimizationHitachi high-speed, high performancesolder paste printers and Koh YoungTechnology’s 3D Solder PasteInspection (SPI) systems cannow “talk” to one another viaKoh Young’s Closed LoopInterface process controlsoftware. The process controlsoftware brings the SPI systemand the printer together via aclosed-loop communicationslink to not only identify defectsin solder paste printing, butcorrect them at the printer.This process optimization toolprevents soldering defectsdownstream that result in excessrework, productivity delays, and loweryields. Hitachi’s HP-07 and HP-08 solderpaste printers also have the capacity toaccommodate large-size printed circuitboards with a range from 50 x 50to 620 x 510mm.Koh Young’s aSPIre2 Solder PasteInspection System.Based on the true 3D measurements ofthe Koh Young SPI system (after the52Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

print) communicated to the printer, theprinter’s software automatically adjustsprinting parameters to optimize the printprocess and mitigate potential problemsand defects. Whereas the SPI machinetypically detects solder paste print defectsand offers real-time defect analysisand trend charts, the KY Closed LoopInterface ‘talks’ to the printer, whichautomatically makes corrections. SPIprint offset and theta measurements aresent directly to the printer for on-the-flyalignment correction. Automated offsetcorrections can be verified in real timethrough offset histograms and bull’s-eyecharts from KY SPC Plus software.Multitest Announces MEMSOscillator Capability for Its MT9928Test HandlerMultitest announced that itsequipment fully supports the advantagesof MEMS oscillators. This capability isimportant because MEMS oscillators areconsidered to be a favorable alternativeto the long-established, quartz crystaloscillator technology.Besides the superior performanceof MEMS oscillators, reliability andthe more comprehensive features, onesubstantial advantage is that packagingand test of these devices is very similarto standard IC processes. Economyof scale can be achieved, whichTest Handler MT9928significantly contributes to the favorablecost structure, price and availability.The company’s standard TestHandler MT9928 has been deployedfor calibrating and trimming MEMSoscillators at various customers. Allsystems were delivered as full plug andyield solutions, including the Multitestconversion kit, socket, and load board.All typical package sizes of MEMSoscillators are supported.The MT9928 Gravity Feed Handlerensures the required temperatureaccuracy (up to +/-0.2K), but alsoprovides high throughput and low costof test, and as such, fully supports thefavorable cost structure.Imec Teams With Cadence toPresent Automated Design-for-Test(DFT) Solution for 3DMemory-on-LogicAt the European3D TSV Summit inGrenoble, France onJanuary 22-23, 2013,imec, announcedthat, together withCadence DesignSystems, theyhave developed,implementedand validated anautomated 3DDesign-for-Test(DFT) solution totest logic-memoryinterconnects inDRAM-on-logicstacks. The solution,based on Cadence®Encounter® Testtechnology, wasverified on anindustrial test chipcontaining a logicdie and a JEDECcompliantWide-I/OMobile DRAM.Memory-onlogic3D stacks offerthe possibility ofBoard-toto-B-BoardSuperBututtoton®heterogeneous integration with denselow-power inter-die interconnects.They are, therefore, among the first3D products that will come on themarket, enabling next-generationhigh-performance low-power mobileapplications. Recently, JEDEC releaseda standard (JESD-229) for stackableWide-I/O mobile dynamic randomaccess memories (DRAMs) specifyingthe logic-memory interface. Unlikemany previous DRAMs, the standardcontains boundary scan features tofacilitate interconnect testing. Imec andCadence now present a design-for-test(DFT) architecture and correspondingautomatic test pattern generation(ATPG) approach. It is an extensionof their previously announced logicon-logic3D DFT architecture andit supports post-bond testing of theinterconnects between the logic die andPackage-e-to-Boaoard820A Kifer Road,Sunnyvale, CA 94086(408) 743-9700 x331www.hcdcorp.comISO 9001:2008 CertiiedBoard-to-F-FlelexFeaturing HCD PatentedSuperButton® andSuperSpring® ContactElements incorporated intosocket and interposer solutionsfor prototyping, validation,space transformer, and testapplications.Comomingsoon to asshownearyou:DesesignignCConJanuarary y29-30Santa Clara, CABiTSMarch 4-5 45Mesa,AZ“Our Proprietary Technology,Your Competitive Advantage”Copyright © 2013 High Connection Density, Inc. All rights reserved. Information is subject to change without notice.“SuperSpring” and “SuperButton” are trademarks of High Connection Density, Inc.Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]53

the DRAM stacked on top of it.The solution implemented by Cadenceand imec includes the generation ofDRAM test control signals in the logicdie and the inclusion of the DRAMboundary scan registers in the serialand parallel test access mechanisms(TAMs) of the 3D test architecture.The automated design for test solutionhas been validated on an industrialtest chip. The design of the test chipis an interposer-based 3D stacked ICwhich includes a silicon interposerbase die, a 94mm 2 logic system-onchipin 40nm technology, and a singleWide-I/O DRAM rank. The validationresults show that the silicon area of theadditional DFT wrapper is negligiblecompared to the total logic die size(

16. C. K. Lee, T. C. Chang, J. H. Lau,Y. Huang, H. Fu, J. Huang, et al.,“Wafer Bumping, Assembly, andReliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-DIC Integration,” IEEE Trans. onCPMT, Vol. 2, No. 8, Aug. 2012,pp. 1229-1238.17. V. Rao, X. Zhang, S. Ho, R.Rajoo, C. Premachandran, V.Kripesh, et al., “Design andDevelopment of Fine PitchCopper/Low-k Wafer LevelPackage,” IEEE Trans. onAdvanced Packaging, Vol. 33,No. 2, May 2010, pp. 377–388.18. J. H. Lau, C. J. Zhan, P. J.Tzeng, C. K. Lee, M. J. Dai,H. C. Chien, et al., “FeasibilityStudy of a 3D IC IntegrationSystem-in-Packaging (SiP) froma 300mm Multi-Project Wafer(MPW),” IMAPS Trans., Jour. ofMicroelectronic Packaging, Vol.8, No. 4, Fourth Quarter 2011,pp. 171-178.19. C. Zhan, P. Tzeng, J. H. Lau,M. Dai, H. Chien, C. Lee, etal., “Assembly Process andReliability Assessment of TSV/RDL/IPD Interposer withMulti-Chip-Stacking for 3D ICIntegration SiP,” IEEE/ECTCProc., San Diego, CA, May 2012,pp. 548-554.20. S. Sheu, Z. Lin, J. Hung,, J.H. Lau, P. Chen, et al., “AnElectrical Testing Method forBlind Through Silicon Vias(TSVs) for 3D IC Integration,”IMAPS Trans., Jour. ofMicroelectronic Packaging, Vol.8, No. 4, Fourth Quarter 2011,pp. 140-145.21. J. F. Hung, J. H. Lau, P. Chen,S. Wu, S. Lai, M. Li, et al.,“Electrical Testing of BlindThrough-Silicon Via (TSV) for3D IC Integration,” IEEE/ECTCProc., San Diego, CA, May 2012,pp. 564-570.22. J. Chien, Y. Chao, J. H. Lau,M. Dai, R. Tain, M. Dai, etal., “A Thermal PerformanceMeasurement Method forBlind Through Silicon Vias(TSVs) in a 300mm Wafer,”IEEE ECTC Proceedings,Orlando, Florida, June 2011,pp. 1204-1210.SAN JOSE, CALIFORNIAN O V E M B E R 4 - 7, 2 01 3BiographyJohn H. Lau received his PhD degreefrom the U. of Illinois at Urbana-Champaign and is a Fellow at theElectronics & Optoelectronics ResearchLaboratory, Industrial TechnologyResearch Institute (ITRI); emailjohnlau@itri.org.tw>> Call For PapersSMTA and Chip Scale Review are pleased to announce plans for the 10th AnnualInternational Wafer-Level Packaging Conference and Tabletop Exhibition. This premierindustry event explores leading-edge design, material, and process technologies beingapplied to Wafer-Level Packaging applications.The IWLPC Technical Committee would like to invite you to submit an abstractfor next year’s program. Deadline for submittal is March 29th, 2013.SUBMIT ABSTRACT ONLINE: www.iwlpc.comSuggested Topics to SubmitWAFER LEVEL PACKAGING• Wafer Level Chip Scale Packaging (WLCSP), Flip Chip, Fan-Out and Redistribution,Wafer and Device Cleaning, Nanotechnology, Quality, Reliability, and COOMEMS PACKAGING• MEMS Processes and Materials, MEMS Design Tools or Methods, Nano-MEMS andBio-MEMS, Integration , MEMS Integration and Interconnects, RF/wireless, Sensors,Mixed Technology, Optoelectronics3-D PACKAGE INTEGRATION• 3D WLP, Thru Silicon Vias (TSV), Silicon Interposers, Stacking Processes (W2W, D2W, D2D),IC Packaging Substrate, Embedded Die and Passives, TSV Integration: FEOL vs BEOLORGANIZED BY10 th ANNIVERSARYSMTASurface Mount Technology AssociationFor more information on the conference, please contact Patti Hvidhyld at952-920-7682 or to patti@smta.org. For information to exhibit and sponsorshipopportunities please contact Seana Wall at 952-920-7682 or to seana@smta.org.Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]55

Official Media Sponsor:MORE THAN 300TECHNICAL PAPERS COVERING:Advanced PackagingModeling & SimulationOptoelectronicsInterconnectionsMaterials & ProcessingApplied ReliabilityAssembly & Manufacturing TechnologyElectronic Components & RFEmerging TechnologiesConference Sponsors:HIGHLIGHTS• 41 Technical sessions including:• 2 Interactive Presentation sessions• 1 Student Poster session• 16 CEU-approved professionaldevelopment courses• Technology Corner Exhibits, featuringover 70 industry-leading vendors• 4 Special Invited sessions• Several evening receptions• Wednesday luncheon speaker• Many opportunities for networking• Great locationADVERTISER-INDEXAmkor Technology Inc. www.amkor.com ................................................BiTS www.bitsworkshop.org .......................................................................Brewer Science www.brewerscience.com ................................................CSC Pure Technologies www.cscptech.com .........................................DL Technology www.dltechnology.com ....................................................ECTC www.ectc.net ....................................................................................Emulation Technology www.emulation.com ...........................................E-tec Interconnect www.e-tec.com ..........................................................EV Group www.evgroup.com ......................................................................HanMi Semiconductor www.hanmisemi.com ..........................................HCD Corp www.hcdcorp.com ....................................................................Honeywell www.honeywell-radlo.com........................................................IDI www.idinet.com ....................................................................................Indium Corporation www.indium.com/soldering-to-nitinol ......................Invensas www.interconnectology.com ......................................................Ironwood Electronics www.ironwoodelectronics.com .............................IWLPC www.iwlpc.com ..............................................................................JF Microtechnology www.jftech.com.my................................................KYEC www.kyec.com ..................................................................................Micro Control www.microcontrol.com......................................................Nanium www.nanium.com ........................................................................Nordson Asymtek www.advancedjetting.com...........................................Panasonic www.panasonicfa.com/pennatronics ........................................Plastronics www.plastronics.com .............................................................Rudolph Technologies www.rudolphtech.com........................................SEMI www.semi.org/events .........................................................................Sensata www.qinex.com ............................................................................SSEC www.ssecusa.com .............................................................................Wafer-Handling.com www.wafer-handling.com .....................................139213212563523182&3534IBC37272555919314514711OBC4317IFC5ADVERTISING SALESUSA West, USA-North Central, Asia-PacificKim NewmanChip Scale ReviewP.O. Box 9522 San Jose, CA 95157-0522T: 408.429.8585 F: 408.429.8605ads@chipscalereview.comUSA-East, USA-South CentralRon MolnarAZ Tech Direct LLC13801 S. 32nd Place Phoenix, AZ 85044T: 480.215.2654 F: 480.496.9451rmolnar@chipscalereview.comEuropeRon FriedmanP.O. Box 370183, W. Hartford, CT 06137T: 860.523.1105 F: 860.232.8337rfriedman@chipscalereview.comKoreaYoung J. BaekYoung Media Inc.407 Jinyang Sangga, 120-3 Chungmuro 4 gaChung-ku, Seoul, Korea 100-863T: +82.2.2273.4819 F: +82.2.2273.4866ymedia@chol.com56Chip Scale Review Jan/Feb 2013 [ChipScaleReview.com]

With manufacturing facilities in four countries and more designengineers on staff than some socket companies have peoplein their building, it’s no surprise that IDI is theworld’s largest manufacturer of testsockets.What’s surprising is how agile wecan be -- nimble enough to haveindustry-leading designs for PoP,WLCSP, extended contact life,and ultra high frequencies.Whether you’re the world’slargest consumer of socketsor its smallest, and whether youneed 200 micron pitch or 40 GHz,IDI is your best partner.To learn more, visit www.idinet.comChip Scale Review March/April 2012 [ChipScaleReview.com] 3

4Chip Scale Review March/April 2012 [ChipScaleReview.com]