DRIE Technology for MEMS, PEUG 2-09 - Avsusergroups.org

The Bosch DRIE ProcessF + ions SiF 4SiSF 6 PlasmaPassivationSi-CF 2-C 4 F 8 PlasmaScallopingSF 6 PlasmaBosch: A cyclic process alternating betweenEtch and passivation©All rights reserved 2009 6

Silicon DRIE – Improved gas utilizationeeSF 6eSF 5FSF 4FSF 3F100 % Increase in gas dissociation with IP-2 source©All rights reserved 2009 9

Silicon DRIE – Improved etch rate60IP-2 plasma source:> 30 µm/min@±5% uniformity2008200650403020Etch rate (um/min)Etch rate (µm/min)2002100100806040200Open Area (%)Open area (%)Newest Generation plasma source significantlyincreases silicon etch rate©All rights reserved 2009 10

Silicon DRIE - Angle DeviationGas and plasma uniformity improvements providetight profile control across the wafer, < 0.15 °©All rights reserved 2009 11

Thermal Dissipation IssuesEtch: Si(s) + 4F(g) SiF4(g) + 385 kcal/molHeatSiliconHeCooled chuckRIEDRIEIncreasing etch rate inevitably produces moreheat to dissipate.©All rights reserved 2009 12

Thermal Dissipation IssuesWafer clamping with He backside pressure is the only wayto maintain a low temperature substrate surface.Thermal conductivity of materials (W/M-K)HeatSiliconGlass + TapeHeCooled ESCChill PlateGlass Alumina AlN Kapton Silicon Aluminum Helium≈ 1 15-30 180 0.16 156 210 0.15Thermal resistive substrate materials can be a limiting factorfor High etching rate and profile control.Chill plate interface can impactthe ESC cooling effectiveness .Newest generation ESC design improveswafer cooling efficiencyESC for SOI©All rights reserved 2009 13

MEMS & SOI: notchingNotching is the local side etching of a conductive layer (silicon)above an insulating layer (oxide).Pattern bottoms are charged up by an excess of positive ions,resulting in a divergence of ion trajectories close to the oxide layer.NotchingPlasmaRF SheathSiliconNotchingOxideMEMS devices on SOI substrates require carefulattention to notch suppression©All rights reserved 2009 14

How to suppress the notching ?1 – Increase the sidewall protection– Protection decreases with Aspect Ratio– Net Etch rate tends to zero at higher AR!!!2 – Neutralize the charge built-up– Reduce the bias frequency and pulsethe bias power.– During the “Off” period, surfacepotential decreases.– Electrons accelerate toward thesurface and neutralize the positivecharges at the bottom.– Less charge => less trajectory bending=> smaller notchesTegal DRIE process technology can suppress notchformation on SOI substrates©All rights reserved 2009 15

ARDE Control in Si EtchingAspect Ratio Dependent Etching (ARDE):etch rate decreases when A.R increases.Most MEMS devices include structureswith a wide range of feature sizes, whichcan have different etch rates.High over-etching time is required tocomplete the etching of the narrowfeatures.©All rights reserved 2009 16

Silicon DRIE – ARDE30Silicon Etch Rate vs. Aspect Ratio (25% exposed area)25Etch rate (um/min)201510500 5 10 15 20Aspect ratioAspect Ratio Dependent Etch rate: Higher AspectRatios result in lower etch rates©All rights reserved 2009 17

ARDE: Role of Ions5045ARDE= 45 %max ER = 7.1 µm/minmin ER = 3.9 µm/minARDE (%)403530252015105ARDE= 18 %max ER= 4.4 µm/minmin ER = 3.6 µm/min00.60.50.40.30.20.10Relative Ion FluxDecreasing the Ion flux reduces the effect ofARDE©All rights reserved 2009 18

ARDE: Role of passivation layerLowPassivationHigh10ARDE: 12 %max ER = 3.2µm/minARDE(%)50-5ARDE: 0%max ER = 3µm/minARDE: -12 %max ER = 2.9µm/min-10Further ARDE improvement can be made bymodification of the passivation process©All rights reserved 2009 19

High Aspect Ratio limitationThe standard Bosch process is limited to anaspect ratio of ~20.©All rights reserved 2009 20

The Tegal SHARP ProcessStandard solutions for increasing the maximum aspectratio are inefficient. (pressure, bias, ion flux)Etch rate (nm/s)141210864200 20 40 60 80 100Bias Voltage (V)OxygenSF6An O2 Plasma removes polymer 5 time faster thanan SF6 plasma.©All rights reserved 2009 21

SHARP*: Super High Aspect Ratio Process*Patent pending0.4µm 0.5µm 0.6µm 1.0µmAR= 65 AR= 56 AR= 50 AR= 36Insertion of an O 2 step into a standard Boschprocess sequence optimizes polymer removal.Aspect Ratios of 100:1 can be achieved.©All rights reserved 2009 22

Super High Aspect Ratio Process (SHARP)SHARP Patented ProcessAchieving Aspect Ratio> 100Courtesy: ESIEECourtesy: CEA .LETIAR= 107Selective and faster removal of the polymer layerimproves high aspect ratio etching©All rights reserved 2009 23

Process StabilityPassivation polymers deposit on all the cooled reactor surfaces.Accumulation of polymers can produce process drift.Etch Rate (µm/min)Process Stability (Customer Data)3Asia Region2.8Average ER= 2.33 µm/min2.62.42.22.010Tegal chamber walls aretemperature controlledto reduce polymer layerbuilt up.Average Non Uniformity = 2.0 %8642Uniformity %Less frequent “wet”cleans are required.00 500 1000 1500 2000 2500 3000 3500 4000 4500 5000WafersReactor design improves process stability andreduces manual cleaning downtime.©All rights reserved 2009 24

Thick Oxide & Glass EtchingDeep etching of glass materialsBias Voltage optimizedEtch Rate > 0.4 µm/min Selectivity > 18:12000SiO 2Etch Rate (Å/min)10000VthresholdSi (mask)-10000 50 100 150 200 250 300 350 400Bias Voltage (-V)Tegal DRIE can also etch deep oxide features.©All rights reserved 2009 25

ConclusionDRIE of silicon is a key enabling technology for MEMS.Significant DRIE improvements have been discussed:– Improved gas utilization and etch rate (Hardware)– Angle deviation (Process & Hardware)– Improved thermal dissipation (Hardware)– Notching control (Process & Hardware)– Improved ARDE (Process)– SHARP (Process)– Improved Process Stability (Hardware)©All rights reserved 2009 26

Tegal Corporationwww.tegal.comQuestions?Plasma Etch Users Group, 26 February, 2009©All rights reserved 2009 27