Motorola - MECL data - dl122rev7 - Italy

DL122/DRev. 7, Mar-2000MECL DataON Semiconductor

MECL DataDL122/DRev. 7, Mar–2000© SCILLC, 2000Previous Edition © 1996“All Rights reserved”

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.PUBLICATION ORDERING INFORMATIONNorth America Literature Fulfillment:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail: ONlit@hibbertco.comN. American Technical Support: 800–282–9855 Toll Free USA/CanadaEUROPE: LDC for ON Semiconductor – European SupportGerman Phone: (+1) 303–308–7140 (M–F 2:30pm to 5:00pm Munich Time)Email: ONlit–german@hibbertco.comFrench Phone: (+1) 303–308–7141 (M–F 2:30pm to 5:00pm Toulouse Time)Email: ONlit–french@hibbertco.comEnglish Phone: (+1) 303–308–7142 (M–F 1:30pm to 5:00pm UK Time)Email: ONlit@hibbertco.comASIA/PACIFIC: LDC for ON Semiconductor – Asia SupportPhone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)Toll Free from Hong Kong 800–4422–3781Email: ONlit–asia@hibbertco.comJAPAN: ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549Phone: 81–3–5487–8345Email: r14153@onsemi.comFax Response Line: 303–675–2167800–344–3810 Toll Free USA/CanadaON Semiconductor Website: http://onsemi.comFor additional information, please contact your localSales Representative.http://onsemi.com1

This book presents technical data for a broad line of MECL integrated circuits. Complete specificationsfor the individual circuits are provided in the form of data sheets. In addition, selectorguides are included to simplify the task of choosing the best combination of circuits for optimumsystem architecture. For the most up–to–date information, please visit our website at:http://onsemi.comECLinPS, ECLinPS Lite, MECL, MECL 10H, MECL 10K, MECL III, MTTL, and ON–Demand CDROM are a trademarks of SemiconductorComponents Industries, LLC.MOSAIC is a trademark of Motorola, Inc.The brands and product names mentioned are trademerks or registered trademarks of their respective holders.http://onsemi.com2

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Table of ContentsDeleted DevicesListing of Deleted Devices . . . . . . . . . . . . . . . . . . . . 5End–of–Life Devices (EOL)Listing of EOL Devices . . . . . . . . . . . . . . . . . . . . . . . 5Numeric Data Sheet ListingMECL 10H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6MECL 10K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Carrier Band Modem . . . . . . . . . . . . . . . . . . . . . . . . 9Chapter 1. General InformationHigh–Speed Logic . . . . . . . . . . . . . . . . . . . . . . . . . 11MECL Products . . . . . . . . . . . . . . . . . . . . . . . . . . 11MECL Family Comparison . . . . . . . . . . . . . . . . . 12Basic Design Considerations . . . . . . . . . . . . . . . 13Definitions of Symbols & Abbreviations . . . . . . 15Pin Conversion Tables . . . . . . . . . . . . . . . . . . . 18MECL Positive and Negative Logic . . . . . . . . . . 19Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21General Characteristics . . . . . . . . . . . . . . . . . . . 21Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Switching Parameters . . . . . . . . . . . . . . . . . . . . . 24Setup and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . 25Testing MECL 10H, 10K and III . . . . . . . . . . . . . 26Operational Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 27System Design Considerations . . . . . . . . . . . . . . 29Thermal Management . . . . . . . . . . . . . . . . . . . . . 29Optimizing Reliability . . . . . . . . . . . . . . . . . . . . . . 31Thermal Effects on Noise Margin . . . . . . . . . . . 33Mounting and Heatsink . . . . . . . . . . . . . . . . . . . . 33Circuit Interconnects . . . . . . . . . . . . . . . . . . . . . . 34Applications Assistance Form . . . . . . . . . . . . . . 39Chapter 2. MECL 10H Data SheetsMECL 10H Selector Guide . . . . . . . . . . . . . . . . . . . 41MECL 10H Introduction . . . . . . . . . . . . . . . . . . . . . . 42MECL 10H Data Sheets . . . . . . . . . . . . . . . . . . . . . . 45Chapter 3. MECL 10K Data SheetsMECL 10K Selector Guide . . . . . . . . . . . . . . . . . . 239MECL 10K Data Sheets . . . . . . . . . . . . . . . . . . . . . 240Chapter 4. Carrier Band ModemCarrier Band Modem Data Sheet . . . . . . . . . . . . . 437Chapter 5. Ordering InformationDevice Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 461Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462ON Semiconductor WorldwideSales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470http://onsemi.com4

The following list of devices have been deleted since the last publication of this book.DATA SHEETS DELETEDMC10137 MC1648 MC1650 MC1651MC1658 MC1660 MC1662 MC1670MC1692 The following list of devices have been placed on EOL and are not recommended for new designs, since the last publicationof this book.END OF LIFE DEVICESMC10H145MC10H660http://onsemi.com5

MECL 10H Data SheetsMC10H016 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45MC10H100 Quad 2–Input NOR Gate With Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48MC10H101 Quad OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50MC10H102 Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52MC10H103 Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54MC10H104 Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56MC10H105 Triple 2–3–2–Input OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58MC10H106 Triple 4–3–3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60MC10H107 Triple 2–Input Exclusive OR/Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 62MC10H109 Dual 4–5–Input OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64MC10H113 Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66MC10H115 Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68MC10H116 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70MC10H117 Dual 2–Wide 2–3–Input OR–AND/OR–AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 72MC10H121 4–Wide OR–AND/OR–AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74MC10H123 Triple 4–3–3–Input Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76MC10H124 Quad TTL–to–MECL Translator With TTL Strobe Input . . . . . . . . . . . . . . . . . . . . . . . 78MC10H125 Quad MECL–to–TTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80MC10H130 Dual Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82MC10H131 Dual D Type Master–Slave Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84MC10H135 Dual J–K Master–Slave Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86MC10H136 Universal Hexadecimal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88MC10H141 Four–Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91MC10H158 Quad 2–Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94MC10H159 Quad 2–Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96MC10H160 12–Bit Parity Generator–Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99MC10H161 Binary to 1–8 Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101MC10H162 Binary to 1–8 Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104MC10H164 8–Line Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107MC10H165 8–Input Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110MC10H166 5–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114MC10H171 Dual Binary to 1–4 Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118MC10H172 Dual Binary to 1–4–Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120MC10H173 Quad 2–Input Multiplexer/ Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122MC10H174 Dual 4 to 1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125MC10H175 Qunit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127MC10H176 Hex D Master–Slave Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130MC10H179 Look–Ahead Carry Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133http://onsemi.com6

MECL 10H Data SheetsMC10H180 Dual 2–Bit Adder/Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137MC10H181 4–Bit Arithmetic Logic Unit/ Function Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139MC10H186 Hex D Master–Slave Flip–Flop with Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143MC10H188 Hex Buffer with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146MC10H189 Hex Inverter with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148MC10H209 Dual 4–5–Input OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150MC10H210 Dual 3–Input 3–Output OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152MC10H211 Dual 3–Input 3–Output NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154MC10H330 Quad Bus Driver/Receiver with 2–to–1 Output Multiplexers . . . . . . . . . . . . . . . . . . . 156MC10H332 Dual Bus Driver/Receiver with 4–to–1 Output Multiplexers . . . . . . . . . . . . . . . . . . . . 159MC10H334 Quad Bus Driver/Receiver with Transmit and Receiver Latches . . . . . . . . . . . . . . . 162MC10H350 PECL* to TTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165MC10H351 Quad TTL/NMOS to PECL* Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168MC10H352 Quad CMOS to PECL* Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170MC10H424 Quad TTL to ECL Translator with ECL Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172MC10/100H600 9–Bit TTL/ECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174MC10/100H601 9–Bit ECL/TTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176MC10/100H602 9–Bit Latch TTL/ECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178MC10/100H603 9–Bit Latch ECL/TTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180MC10/100H604 Registered Hex TTL/ECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182MC10/100H605 Registered Hex ECL/TTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184MC10/100H606 Registered Hex TTL/PECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188MC10/100H607 Registered Hex PECL/TTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191MC10/100H640 68030/040 PECL–TTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194MC10/100H641 Single Supply PECL–TTL 1:9 Clock Distribution Chip . . . . . . . . . . . . . . . . . . . . . . . . 200MC10/100H642 68030/040 PECL–TTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206MC10/100H643 Dual Supply ECL–TTL 1:8 Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213MC10/100H644 68030/040 PECL–TTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216MC10H645 1:9 TTL Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220MC10/100H646 PECL/TTL–TTL 1:8 Clock Distribution Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223MC10/100H680 4–Bit Differential ECL Bus/TTL Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227MC10/100H681 Hex ECL/TTL Transceiver with Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233MECL 10K Data SheetsMC10101 Quad OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240MC10102 Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243MC10103 Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246MC10104 Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249MC10105 Triple 2–3–2–Input OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252MC10106 Triple 4–3–3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255MC10107 Triple 2–Input Exclusive OR/ Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 257http://onsemi.com7

MECL 10K Data SheetsMC10109 Dual 4–5–Input OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260MC10110 Dual 3–Input/3–Output OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263MC10111 Dual 3–Input/3–Output NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266MC10113 Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269MC10114 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272MC10115 Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276MC10116 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278MC10117 Dual 2–Wide 2–3–Input OR–AND/OR–AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 281MC10121 4–Wide OR–AND/OR–AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284MC10123 Triple 4–3–3–Input Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287MC10124 Quad TTL to MECL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289MC10125 Quad MECL to TTL Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294MC10129 Quad Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299MC10131 Dual Type D Master–Slave Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306MC10133 Quad Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309MC10134 Dual Multiplexer With Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312MC10135 Dual J–K Master–Slave Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315MC10136 Universal Hexadecimal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318MC10138 Bi–Quinary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329MC10141 Four Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333MC10153 Quad Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337MC10154 Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340MC10158 Quad 2–Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343MC10159 Quad 2–Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345MC10160 12–Bit Parity Generator–Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347MC10161 Binary to 1–8 Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350MC10162 Binary to 1–8 Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353MC10164 8–Line Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355MC10165 8–Input Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358MC10166 5–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363MC10168 Quad Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367MC10170 9+2–Bit Parity Generator/ Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370MC10171 Dual Binary to 1–4 Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373MC10172 Dual Binary to 1–4 Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376MC10173 Quad 2–Input Multiplexer/ Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379MC10174 Dual 4 to 1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382MC10175 Quint Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384MC10176 Hex D Master/Slave Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387MC10178 Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390MC10181 4–Bit Arithmetic Logic Unit/ Function Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393MC10186 Hex D Master–Slave Flip–Flop With Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398http://onsemi.com8

MECL 10K Data SheetsMC10188 Hex Buffer With Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401MC10189 Hex Inverter With Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403MC10192 Quad Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405MC10195 Hex Inverter/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407MC10197 Hex AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409MC10198 Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411MC10210 Dual 3–Input/3–Output OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420MC10211 Dual 3–Input/3–Output NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423MC10212 High Speed Dual 3–Input/ 3–Output OR/NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . 426MC10216 High Speed Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429MC10231 High Speed Dual Type D Master–Slave Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . 432Carrier Band Modem Data SheetMC68194 Carrier Band Modem (CBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437http://onsemi.com9

CHAPTER 1General InformationHigh–Speed Logic . . . . . . . . . . . . . . . . . . . . . . . . . 11MECL Products . . . . . . . . . . . . . . . . . . . . . . . . . . 11MECL Family Comparison . . . . . . . . . . . . . . . . . 12Basic Design Considerations . . . . . . . . . . . . . . . 13Definitions of Symbols & Abbreviations . . . . . . 15Pin Conversion Tables . . . . . . . . . . . . . . . . . . . 18MECL Positive and Negative Logic . . . . . . . . . . 19Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21General Characteristics . . . . . . . . . . . . . . . . . . . 21Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Switching Parameters . . . . . . . . . . . . . . . . . . . . . 24Setup and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . 25Testing MECL 10H and 10K . . . . . . . . . . . . . . . . 26Operational Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 27System Design Considerations . . . . . . . . . . . . . . 29Thermal Management . . . . . . . . . . . . . . . . . . . . . 29Optimizing Reliability . . . . . . . . . . . . . . . . . . . . . . 31Thermal Effects on Noise Margin . . . . . . . . . . . 33Mounting and Heatsink . . . . . . . . . . . . . . . . . . . . 33Circuit Interconnects . . . . . . . . . . . . . . . . . . . . . . 34Applications Assistance Form . . . . . . . . . . . . . . 39http://onsemi.com10

HIGH–SPEED LOGICHigh speed logic is used whenever improved systemperformance would increase a product’s market value. Fora given system design, high–speed logic is the most directway to improve system performance and Emitter–CoupledLogic (ECL) is one of today’s fastest forms of digital logic.Emitter– coupled logic offers both the logic speed and logicfeatures to meet the market demands for higher performancesystems.MECL PRODUCTSMotorola, now ON Semiconductor, introduced theoriginal monolithic emitter–coupled logic family withMECL I (1962) and followed this with MECL II (1966).These two families are now obsolete and have given way tothe MECL III (MC1600 series), MECL 10K, PLL(MC12000 series) and the new MECL 10H families.Chronologically the third family introduced, MECL III(1968) is a higher power, higher speed logic. Typical 1 nsedge speeds and propagation delays along with greater than500 MHz flip–flop toggle rates, make MECL III useful forhigh–speed test and communications equipment. Also, thisfamily is used in the high–speed sections and critical timingdelays of larger systems. For more general purposeapplications, however, trends in large high–speed systemsshowed the need for an easy–to–use logic family withpropagation delays on the order of 2 ns. To match thisrequirement, the MECL 10,000 Series was introduced in1971.An important feature of MECL 10K is its compatibilitywith MECL III to facilitate using both families in the samesystem. A second important feature is its significant powereconomy – MECL 10K gates use less than one–half thepower of MECL III.ON Semiconductor introduced the MECL 10H productfamily in 1981. This latest MECL family features 100%improvements in propagation delay and clock speeds whilemaintaining power supply currents equal to MECL 10K.MECL 10H is voltage compensated allowing guaranteed dcand switching parameters over a ±5% power supply range.Noise margins have been improved by 75% over the MECL10K series.Compatibility with MECL 10K and MECL III is a keyelement in allowing users to enhance existing systems byincreasing the speed in critical timing areas. Also, manyMECL 10H devices are pin out/functional duplications ofthe MECL 10K series devices. The emphasis of this familywill be placed on more powerful logic functions havingmore complexity and greater performance. With 1.0 nspropagation delays and 25 mW per gate, MECL 10H is oneof the best speed–power families of any ECL logic familyavailable today.MECL at +5V (PECL – Positive ECL)Any single supply ECL device is also a PECL device,making the PECL portfolio as large as the existing ECL one.(Note: The dual supply translator devices cannot operate at+5V and ground and cannot be considered PECL devices.)ECL devices in the PECL mode, must have theinput/output DC specifications adjusted for properoperation. ECL levels (DC) are referenced from the VCClevel. To calculate the PECL DC specifications, ECL levelsare added to the new VCC.EXAMPLE:PECL VOH = New VCC + ECL VOH, 5.0V + (–0.81V)= 4.190V and is the max VOH level at 25°C for a PECLdevice. Follow the same procedure to calculate allinput/output DC specifications for a device used in aPECL mode. The VTT supply used to sink the paralleltermination currents is also referenced from the VCCsupply and is VCC–2.0V. The PECL VTT supply =+5V – 2V = +3.0V and should track the VCC supplyone–to–one for specified operation.Since ECL is referenced from the VCC rail, any noise on theVCC supply will be reflected on the output waveshape at aone–to–one ratio. Therefore, noise should be kept as low aspossible for best operation. Devices in a PECL systemcannot have VCC vary more than 5% to assure proper ACoperation. See ON Semiconductor Application NoteAN1406/D “Designing With PECL (ECL at +5.0V)” formore details.AC performance in the PECL mode is equal to the ACperformance in the ECL mode, if the pitfalls set forth inApplication Note (AN1406/D) are avoided.http://onsemi.com11

MECL FAMILY COMPARISONSMECL 10KFeature MECL 10H 10,100 Series 10,200 Series1. Gate Propagation Delay 1.0 ns 2.0 ns 1.5 ns2. Output Edge Speed* 1.0 ns 3.5 ns 2.5 ns3. Flip–Flop Toggle Speed 250 MHz min 125 MHz min 200 MHz min4. Gate Power 25 mW 25 mW 25 mW5. Speed Power Product 25 pJ 50 pJ 37 pJ*Output edge speed: MECL 10K/10H measured 20% to 80%.Figure 1 – GENERAL CHARACTERISTICSAmbientTemperature Range MECL 10H MECL 10K0° to 75°C MC10H100 Series–30°C to +85°CFigure 2 – OPERATING TEMPERATURE RANGEMC10100 SeriesMC10200 SeriesMECL IN PERSPECTIVEIn evaluating any logic line, speed and powerrequirements are the obvious primary considerations.Figure 1 and Figure 2 provide the basic parameters of theMECL 10H, MECL 10K, and MECL III families. But theseprovide only the start of any comparative analysis, as thereare a number of other important features that make MECLhighly desirable for system implementation. Among these:Complementary Outputs cause a function and itscomplement to appear simultaneously at the device outputs,without the use of external inverters. It reduces packagecount by eliminating the need for associated invert functionsand, at the same time, cuts system power requirements andreduces timing differential problems arising from the timedelays introduced by inverters.High Input Impedance and Low Output Impedancepermit large fan out and versatile drive characteristics.Insignificant Power Supply Noise Generation, due todifferential amplifier design which eliminates current spikeseven during signal transition period.Nearly Constant Power Supply Current Drainsimplifies power–supply design and reduces costs.Low Cross–Talk due to low–current switching in signalpath and small (typically 850 mV) voltage swing, and torelatively long rise and fall times.Wide Variety of Functions, including complex functionsfacilitated by low power dissipation (particularly in MECL10H and MECL 10K series). A basic MECL 10K gateconsumes less than 8 mW in on–chip power in somecomplex functions.Wide Performance Flexibility due to differentialamplifier design which permits MECL circuits to be used aslinear as well as digital circuits.Transmission Line Drive Capability is afforded by theopen emitter outputs of MECL devices. No “Line Drivers”are listed in MECL families, because every device is a linedriver.Wire–ORing reduces the number of logic devicesrequired in a design by producing additional OR gatefunctions with only an interconnection.Twisted Pair Drive Capability permits MECL circuits todrive twisted–pair transmission lines as long as 1000 feet.Wire–Wrap Capability is possible with the MECL 10Kfamily because of the slow rise and fall time characteristicof the circuits.Open Emitter–Follower Outputs are used for MECLoutputs to simplify signal line drive. The outputs match anyline impedance and the absence of internal pulldownresistors saves power.Input Pulldown Resistors of approximately 50 kΩpermit unused inputs to remain unconnected for easiercircuit board layout.MECL APPLICATIONSON Semiconductor’s MECL product lines are designedfor a wide range of systems needs. Within the computermarket, MECL 10K is used in systems ranging from specialpurpose peripheral controllers to large mainframecomputers. Big growth areas in this market include disk andcommunication channel controllers for larger systems andhigh performance minicomputers.The industrial market primarily uses MECL for highperformance test systems such as IC or PC board testers.However, the high bandwidths of MECL 10H and MECL10K are required for many frequency synthesizer systemsusing high speed phase lock loop networks. MECL hashttp://onsemi.com12

continued to grow in the industrial market through complexmedical electronic products and high performance processcontrol systems.BASIC CONSIDERATIONS FOR HIGH–SPEEDLOGIC DESIGNHigh–speed operation involves only four considerationsthat differ significantly from operation at low and mediumspeeds:1. Time delays through interconnect wiring, which mayhave been ignored in medium–speed systems, becomehighly important at state–of–the–art speeds.2. The possibility of distorted waveforms due to reflectionson signal lines increases with edge speed.3. The possibility of “crosstalk” between adjacent signalleads is proportionately increased in high–speedsystems.4. Electrical noise generation and pick–up are moredetrimental at higher speeds.In general, these four characteristics are speed– andfrequency–dependent, and are virtually independent of thetype of logic employed. The merit of a particular logicfamily is measured by how well it compensates for thesedeleterious effects in system applications.The interconnect–wiring time delays can be reduced onlyby reducing the length of the interconnecting lines. At logicspeeds of two nanoseconds, an equivalent “gate delay” isintroduced by every foot of interconnecting wiring.Obviously, for functions interconnected within a singlemonolithic chip, the time delays of signals travelling fromone function to another are insignificant. But for a greatmany externally interconnected parts, this can soon add upto an appreciable delay time. Hence, the greater the numberof functions per chip, the higher the system speed. MECLcircuits, particularly those of the MECL 10K and MECL10H Series are designed with a propensity toward complexfunctions to enhance overall system speed.Waveform distortion due to line reflections also becomestroublesome principally at state–of–the–art speeds. At slowand medium speeds, reflections on interconnecting lines arenot usually a serious problem. At higher speeds, however,line lengths can approach the wavelength of the signal andimproperly terminated lines can result in reflections that willcause false triggering (see Figure 3 and Figure 4). Thesolution, as in RF technology, is to employ“transmission–line” practices and properly terminate eachsignal line with its characteristic impedance at the end of itsrun. The low–impedance, emitter–follower outputs ofMECL circuits facilitate transmission–line practiceswithout upsetting the voltage levels of the system.The increased affinity for crosstalk in high–speed circuitsis the result of very steep leading and trailing edges (fast riseand fall times) of the high–speed signal. These steepwavefronts are rich in harmonics that couple readily toadjacent circuits. In the design of MECL 10K and MECL10H, the rise and fall times have been deliberately slowed.This reduces the affinity for crosstalk without compromisingother important performance parameters.From the above, it is evident that the MECL logic line isnot simply capable of operating at high speed, but has beenspecifically designed to reduce the problems that arenormally associated with high–speed operation.4 = 8″A4 = 8″AREZO = 50 RL = ZoVEEVTT = – 2 VDCRECEIVING GATEINPUT ALOWHIGHRECEIVING GATEINPUT ALOWHIGHFigure 3 – UNTERMINATEDTRANSMISSION LINE(No Ground Plane Used)Figure 4 – PROPERLY TERMINATEDTRANSMISSION LINE(Ground Plane Added)http://onsemi.com13

MULTIPLEINPUTSINPUTSDIFFERENTIALAMPLIFIERGATE CIRCUITQ1 Q2 Q3 Q4 Q5A B C DVBB ≅–1.29 VBIASNETWORKVEE ( –5.2 V)VCC2 (GND)COMPLEMENTARYOUTPUTS –0.800VCC1 (GND)ORNORABCDOutput Voltage (Volts)–1.200–1.600–1.800GATE SYMBOLGATE TRANSFER CURVES–1.400 –1.200INPUT VOLTAGE(VOLTS)A + B + C + DA + B + C + DVBBHIGH (–0.90 VTYP.)–1.29 VLOW (–1.75 VTYP.)Figure 5 – MECL 10K GATE STRUCTURE AND SWITCHING BEHAVIORCIRCUIT DESCRIPTIONThe typical MECL 10K circuit, Figure 5, consists of adifferential–amplifier input circuit, a temperature andvoltage compensated bias network, and emitter–followeroutputs to restore dc levels and provide buffering fortransmission line driving. High fan–out operation is possiblebecause of the high input impedance of the differentialamplifier input and the low output impedance of the emitterfollower outputs. Power–supply noise is virtuallyeliminated by the nearly constant current drain of thedifferential amplifier, even during the transition period.Basic gate design provides for simultaneous output of boththe OR function and its complement, the NOR function. Thedesign of the MECL 10H gate is unchanged, with twoexceptions. The bias network has been replaced with avoltage regulator, and the differential amplifier sourceresistor has been replaced with a constant current source.(See section 2 for additional MECL 10H information.)Power–Supply Connections – Any of the power supplylevels, VTT, VCC, or VEE may be used as ground; however,the use of the VCC node as ground results in best noiseimmunity. In such a case: VCC = 0, VTT = –2.0 V, VEE =–5.2 V.System Logic Specifications – The output logic swing of0.85 V, as shown by the typical transfer characteristicscurve, varies from a LOW state of VOL = –1.75 V to a HIGHstate of VOH = –0.9 V with respect to ground.Positive logic is used when reference is made to logical“0’s” or “1’s.” Then“0” = –1.75 V = LOWtypical“1” = –0.9 V = HIGHCircuit Operation – Beginning with all logic inputsLOW (nominal –1.75 V), assume that Q1 through Q4 are cutoff because their P–N base–emitter junctions are notconducting, and the forward–biased Q5 is conducting.Under these conditions, with the base of Q5 held at –1.29 Vby the VBB network, its emitter will be one diode drop (0.8V) more negative than its base, or –2.09 V. (The 0.8 Vdifferential is a characteristic of this P–N junction.) Thebase–to–emitter differential across Q1 – Q4 is then thedifference between the common emitter voltage (–2.09 V)and the LOW logic level (–1.75 V) or 0.34 V. This is less thanthe threshold voltage of Q1 through Q4 so that thesetransistors will remain cut off.When any one (or all) of the logic inputs are shiftedupward from the –1.75 V LOW state to the –0.9 V HIGHstate, the base voltage of that transistor increases beyond thethreshold point and the transistor turns on. When thishappens, the voltage at the common–emitter point rises from–2.09 V to –1.7 (one diode drop below the –0.9 V basevoltage of the input transistor), and since the base voltage ofthe fixed–bias transistor (Q5) is held at –1.29 V, thebase–emitter voltage Q5 cannot sustain conduction. Hence,this transistor is cut off.This action is reversible, so that when the input signal(s)return to the LOW state, Q1 – Q4 are again turned off andQ5 again becomes forward biased. The collector voltagesresulting from the switching action of Q1 – Q4 and Q5 aretransferred through the output emitter–follower to theoutput terminal. Note that the differential action of theswitching transistors (one section being off when the otheris on) furnishes simultaneous complementary signals at theoutput. This action also maintains constant power supplycurrent drain.http://onsemi.com14

DEFINITIONS OF LETTER SYMBOLS AND ABBREVIATIONSCurrent:ICCICBOICCHICCLIEIFIinIINHIINLILIOHIOLIOSIoutIOZLIOZHIRIR′ISCVoltage:VBBVBETotal power supply current drawn from thepositive supply by a MECL unit under test.Leakage current from input transistor on MECLdevices without pulldown resistors when testvoltage is applied.Current drain from VCC power supply with allinputs at logic HIGH level.Current drain from VCC power supply with allinputs at logic LOW level.Total power supply current drawn from a MECLtest unit by the negative power supply.Forward diode current drawn from an input of asaturated logic–to–MECL translator when thatinput is at 0.4V.Current into the input of the test unit when amaximum logic HIGH (VIH max) is applied at thatinput.HIGH level input current into a node with aspecified HIGH level (VIH max) logic voltageapplied to that node. (Same as Iin for positivelogic.)LOW level input current, into a node with aspecified LOW level (VIL min) logic voltageapplied to that node.Load current that is drawn from a MECL circuitoutput when measuring the output HIGH levelvoltage.HIGH level output current: the current flowinginto the output, at a specified HIGH level outputvoltage.LOW level output current: the current flowinginto the output, at a specified LOW level outputvoltage.Output short circuit current.Output current (from a device or circuit, undersuch conditions mentioned in context).Output off current LOW – The current flowing outof a disabled 3–state output with a specifiedLOW output voltage applied.Output off current HIGH – The current flowinginto a disabled 3–state output with a specifiedHIGH output.Reverse current drawn from a transistor input ofa test unit when VEE is applied to that input.Reverse current leakage into an input of asaturated logic MECL/PECL translator whenthat input is at VCC.Short–circuit current drawn from a translatorsaturating output when that output is at groundpotential.Reference bias supply voltage.Base–to–emitter voltage drop of a transistor atspecified collector and base currents.VCBVCCVCC1VCC2VCMRVEEVFVIHVIH maxVIHAVIHA minVIH minVILVIL maxVILAVILA maxVIL minVinVmaxVOHtAACollector–to–base voltage drop of a transistor atspecified collector and base currents.General term for the most positive power supplyvoltage to a MECL device (usually ground,except for translator and interface circuits).Most positive power supply voltage (outputdevices). (Usually ground for MECL devices.)Most positive power supply voltage (currentswitches and bias driver). (Usually ground forMECL devices.)The CMR range is referenced to the mostpositive side of the differential input signal.Normal operation is obtained if the HIGH levelfalls within the specified range and thepeak-to-peak voltage lies between VPPmin and1V. The lower end of the CMR range varies 1:1with VEE. The numbers in the spec table assumea nominal VEE = –5.2V. Note for PECLoperation, the VCMR(min) will be fixed at 5.0V –|VCMR(min)|.Most negative power supply voltage for a circuit(usually –5.2 V for MECL devices).Input voltage for measuring IF on TTL interfacecircuits.Input logic HIGH voltage level (nominal value).Maximum HIGH level input voltage: The mostpositive (least negative) value of high–levelinput voltage, for which operation of the logicelement within specification limits is guaranteed.Input logic HIGH threshold voltage level.Minimum input logic HIGH level (threshold)voltage for which performance is specified.Minimum HIGH level input voltage: The leastpositive (most negative) value of HIGH levelinput voltage for which operation of the logicelement within specification limits is guaranteed.Input logic LOW voltage level (nominal value).Maximum LOW level input voltage: The mostpositive (least negative) value of LOW levelinput voltage for which operation of the logicelement within specification limits is guaranteed.Input logic LOW threshold voltage level.Maximum input logic LOW level (threshold)voltage for which performance is specified.Minimum LOW level input voltage: The leastpositive (most negative) value of LOW levelinput voltage for which operation of the logicelement within specification limits is guaranteed.Input voltage (to a circuit or device).Maximum (most positive) supply voltage,permitted under a specified set of conditions.Output logic HIGH voltage level: The voltagelevel at an output terminal for a specified outputcurrent, with the specified conditions applied toestablish a HIGH level at the output.Address Access Timehttp://onsemi.com15

Voltage (cont.):VOHA Output logic HIGH threshold voltage level.VOHA min Minimum output HIGH threshold voltage levelfor which performance is specified.VOH max Maximum output HIGH or high–level voltage forgiven inputs.VOH min Minimum output HIGH or high–level voltage forgiven inputs.VOL Output logic LOW voltage level: The voltagelevel at the output terminal for a specified outputcurrent, with the specified conditions applied toestablish a LOW level at the output.VOLA Output logic LOW threshold voltage level.VOLA max Maximum output LOW threshold voltage levelfor which performance is specified.VOL max Maximum output LOW level voltage for giveninputs.VOL min Minimum output LOW level voltage for giveninputs.VTT Line load–resistor terminating voltage foroutputs from a MECL device.Time Parameters:t+ Waveform rise time (LOW to HIGH), 10% to90%, or 20% to 80%, as specified.t– Waveform fall time (HIGH to LOW), 90% to 10%,or 80% to 20%, as specified.tr Same as t+tf Same as t–t+– Propagation Delay, see Figure 12 on page 24.t–+ Propagation Delay, see Figure 12 on page 24.tpd Propagation delay, input to output from the 50%point of the input waveform at pin x (falling edgetx±y± noted by – or rising edge noted by +) to the 50%point of the output waveform at pin y (falling edgenoted by – or rising edge noted by +). (CfFigure 12 on page 24.)tx+tx–Output waveform rise time as measured from10% to 90% or 20% to 80% points on waveform(whichever is specified) at pin x with inputconditions as specified.Output waveform fall time as measured from90% to 10% or 80% to 20% points on waveform(whichever is specified) at pin x, with inputconditions as specified.fTog Toggle frequency of a flip–flop or counter device.fshift Shift rate for a shift register.Temperature:TstgTJTAθJAθJClfpmθCAMiscellaneous:egTPinTPoutD.U.T.CinCoutZoutPDRLRTRpP.U.T.Maximum temperature at which device may bestored without damage or performancedegradation.Junction (or die) temperature of an integratedcircuit device.Ambient (environment) temperature existing inthe immediate vicinity of an integrated circuitdevice package.Thermal resistance of an IC package, junction toambient.Thermal resistance of an IC package, junction tocase.Linear feet per minute.Thermal resistance of an IC package, case toambient.Signal generator inputs to a test circuit.Test point at input of unit under test.Test point at output of unit under test.Device under test.Input capacitance.Output capacitance.Output impedance.The total dc power applied to a device, notincluding any power delivered from the device toa load.Load Resistance.Terminating (load) resistor.An input pull–down resistor (i.e., connected tothe most negative voltage).Pin under test.http://onsemi.com16

WHY SURFACE MOUNT?Surface Mount Technology is now being utilized to offeranswers to many problems that have been created in the useof insertion technology.Limitations have been reached with insertion packagesand PC board technology. Surface Mount Technology offersthe opportunity to continue to advance the State-of-the-Artdesigns that cannot be accomplished with InsertionTechnology.Surface Mount Packages allow more optimum deviceperformance with the smaller Surface Mount configuration.Internal lead lengths, parasitic capacitance and inductancethat placed limitations on chip performance have beenreduced.The lower profile of Surface Mount Packages allows moreboards to be utilized in a given amount of space. They arestacked closer together and utilize less total volume thaninsertion populated PC boards.Printed circuit costs are lowered with the reduction of thenumber of board layers required. The elimination orreduction of the number of plated through holes in the board,contribute significantly to lower PC board prices.Surface Mount assembly does not require the preparationof components that are common on insertion technologylines. Surface Mount components are sent directly to theassembly line, eliminating an intermediate step.Automatic placement equipment is available that canplace Surface Mount components at the rate of a fewthousand per hour to hundreds of thousands of componentsper hour.Surface Mount Technology is cost effective, allowing themanufacturer the opportunity to produce smaller units andoffer increased functions with the same size product.MECL AVAILABILITY IN SURFACE MOUNTON Semiconductor is now offering MECL 10K andMECL 10H in the PLCC (Plastic Leaded Chip Carrier)packages.MECL in PLCC may be ordered in conventional plasticrails or on Tape and Reel. Refer to the Tape and Reel sectionfor ordering details.TAPE AND REELON Semiconductor has now added the convenience ofTape and Reel packaging for our growing family of standardIntegrated Circuit products. The packaging fully conformsto the latest EIA RS-481A specification. The antistaticembossed tape provides a secure cavity sealed with apeel-back cover tape.GENERAL INFORMATION• Reel Size 13 inch (330 mm) Suffix: R2• Tape Width 16 mm• Units/Reel 1000MECHANICAL POLARIZATIONTYPICALPIN 1LINEAR DIRECTIONOF TRAVELORDERING INFORMATIONVIEWFROMTAPESIDE• Minimum Lot Size/Device Type = 3000 Pieces.• No Partial Reel Counts Available.• To order devices which are to be delivered in Tapeand Reel, add the appropriate suffix to the devicenumber being ordered.EXAMPLE:ORDERING CODEMC10101FNMC10101FNR2MC10H101FNMC10H101FNR2MC12015DMC12015DR2SHIPMENT METHODMagazines (Rails)13 inch Tape and ReelMagazines (Rails)13 inch Tape and ReelMagazines (Rails)13 inch Tape and ReelDUAL-IN-LINE PACKAGE TOPLCC PIN CONVERSION DATAThe following tables give the equivalent I/O pinouts ofDual-In-Line (DIL) packages and Plastic Leaded ChipCarrier (PLCC) packages.http://onsemi.com17

8–Pin DIL to 20–Pin PLCC8 PIN DIL 1 2 3 4 5 6 7 820 PIN PLCC 2 5 7 10 12 15 17 2014–Pin DIL to 20–Pin PLCC14 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 1420 PIN PLCC 2 3 4 6 8 9 10 12 13 14 16 18 19 2016–Pin DIL to 20–Pin PLCC16 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1620 PIN PLCC 2 3 4 5 7 8 9 10 12 13 14 15 17 18 19 2020–Pin DIL to 20–Pin PLCC20 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2020 PIN PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2024–Pin DIL to 28–Pin PLCC24 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2428 PIN PLCC 2 3 4 5 6 7 9 10 11 12 13 14 16 17 18 19 20 21 23 24 25 26 27 28http://onsemi.com18

INTRODUCTIONThe increasing popularity and use of emitter coupled logichas created a dilemma for some logic designers. Saturatedlogic families such as TTL have traditionally been designedwith the NAND function as the basic logic function,however, the basic ECL logic function is the NOR function(positive logic). Therefore, the designer may either designECL systems with positive logic using the NOR, or designMECL POSITIVE AND NEGATIVE LOGICwith negative logic using the NAND. Which is the moreconvenient? On the one hand the designer is familiar withpositive logic levels and definitions, and on the other hand,he is familiar with implementing systems using NANDfunctions. Perhaps a presentation of the basic definitions andcharacteristics of positive and negative logic will clarify thesituation and eliminate misunderstanding.V CC = gndC A B V BB = –1.29 voltsV EE = –5.2 voltsTable 1NEGATIVE LOGICINPUTS OUTPUTA B CAB11001010Table 2C = A B0111CINPUTS OUTPUTA B CLOLOHIHILOHILOHIHILOLOLOHI = –0.9 voltsLO = –1.7 volts0011ABTable 3POSITIVE LOGICINPUTS OUTPUTA B C0101C = A + B1000CFigure 6 – Basic MECL Gate Circuit and Logic FunctionIn Positive and Negative Nomenclature.Circuit diagrams external to ON Semiconductor products are included as a means of illustrating typical semiconductor applications; consequently, completeinformation sufficient for construction purposes is not necessarily given. The information in this Application Note has been carefully checked and is believed to beentirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductordevices described any license under the patent rights of ON Semiconductor or others.http://onsemi.com19

LOGIC EQUIVALENCIESBinary logic must have two states to represent the binary1 and 0. With ECL the typical states are a high level of –0.9volts and a low level of –1.7 volts. Two choices are possiblethen to represent the binary 1 and 0. Positive logic definesthe 1 or “true” state as the most positive voltage level,whereas negative logic defines the most negative voltagelevel as the 1 or “true” state. Because of the difference indefinition of states, the basic ECL gate is a NOR function inpositive logic and is a NAND function in negative logic.Figure 6 more clearly shows the above comparison offunctions. Table 1 lists the output voltage level as a functionof input voltage levels of the MECL gate circuit shown.Table 2 translates the voltage levels into the appropriatenegative logic levels which show the function to be C =A • B; that is, the circuit performs the NAND function.Table 3 translates the equivalent positive logic function intoC = A + B, the NOR function.Similar comparisons could be made for other positivelogic functions. As an example, the positive OR functiontranslates to the negative AND function. Figure 7 shows acomparison of several common logic functions.Any function available in a logic family may be expressedin terms of positive or negative logic, bearing in mind thedefinition of logic levels. The choice of logic definition, aspreviously stated, is dependent on the designer. ONSemiconductor provides both positive and negative logicsymbols on data sheets for the popular MECL 10,000 logicseries.Figure 7 – Comparative Positive and Negative Logic Functions.POSITIVE LOGICINPUTSA B AND OR NAND NOR EXOR EXNORLO LO LO LO HI HI LO HILO HI LO HI HI LO HI LOHI LO LO HI HI LO HI LOHI HI HI HI LO LO LO HIA B OR AND NOR NAND EXNOR EXORINPUTSNEGATIVE LOGICSUMMARYConversion from one logic form to another or the use ofa particular logic form need not be a complicated process. Ifthe designer uses the logic form with which he is familiarand bears in mind the previously mentioned definition oflevels, problems arising from definition of logic functionsshould be minimized.REFERENCEY. Chu, Digital Computer Design FundamentalsNew York, McGraw–Hill, 1962http://onsemi.com20

TECHNICAL DATAGENERAL CHARACTERISTICS AND SPECIFICATIONS(See pages 15 through 16 for definitions of symbols andabbreviations.)In subsequent sections of this Data Book, the importantMECL parameters are identified and characterized, andcomplete data provided for each of the functions. To makethis data as useful as possible, and to avoid a great deal ofrepetition, the data that is common to all functional blocksin a line is not repeated on each individual sheet. Rather,these common characteristics, as well as the applicationinformation that applies to each family, are discussed in thissection.In general, the common characteristics of majorimportance are:Maximum Ratings, including both dc and accharacteristics and temperature limits;Transfer Characteristics, which define logic levels andswitching thresholds;DC Parameters, such as output levels, threshold levels,and forcing functions.AC Parameters, such as propagation delays, rise and falltimes and other time dependent characteristics.In addition, this section will discuss general layout anddesign guides that will help the designer in building andtesting systems with MECL circuits.LETTER SYMBOLS AND ABBREVIATIONSThroughout this section, and in the subsequent datasheets, letter symbols and abbreviations will be used indiscussing electrical characteristics and specifications. Thesymbols used in this book, and their definitions, are listed onthe preceding pages.MAXIMUM RATINGSThe limit parameters beyond which the life of the devicesmay be impaired are given in Table 4. In addition, Table 5provides certain limits which, if exceeded, will not damagethe devices, but could degrade the performance below thatof the guaranteed specifications.Table 4 – LIMITS BEYOND WHICH DEVICE LIFE MAY BE IMPAIREDCharacteristic Symbol Unit MECL 10H MECL 10KPower Supply VEE Vdc –8.0 to 0 –8.0 to 0Input Voltage (VCC = 0) Vin Vdc 0 to VEE 0 to VEEOutput Source Current Continuous Iout mAdc 50 50Output Source Current Surge Iout mAdc 100 100Storage Temperature Tstg °C –65 to +150 –65 to +150Junction Temperature Ceramic Package TJ °C 165 165Junction Temperature Plastic Package TJ °C 140 140NOTES: 1. Maximum T J may be exceeded ( 250°C) for short periods of time ( 240 hours) without significant reduction in device life.2. For long term ( 10 yrs.) max T J of 110°C required. Max T J may be exceeded ( 175°C) for short periods of time ( 240 hours) without significantreduction in device life.Operating TemperatureRange CommercialTable 5 – LIMITS BEYOND WHICH PERFORMANCE MAY BE DEGRADEDCharacteristics Symbol Unit MECL 10H MECL 10KTA °C 0 to +75 –30 to +85Supply Voltage (VCC = 0) VEE Vdc –4.94 to –5.46 –4.68 to –5.72Output Drive Commercial – Ω 50 Ω to –2.0 Vdc 50 Ω to –2.0 VdcNOTES: 1. With airflow 500 lfpm.2. Functionality only. Data sheet limits are specified for –5.2 V ± 0.010 V.3. Except MC1648 which has an internal output pulldown resistor.4. Functional and Data sheet limits.http://onsemi.com21

MECL TRANSFER CURVES and SPECIFICATION TEST POINTSFigure 8 – MECL 10KFigure 9 – MECL 10HGate Output(measured test limits)V OHA minTest Conditions: 25 CV EE = –5.2V50Ω matchedinputs and outputsV OLA maxV OH maxV OH minV OL maxV OL minV IL min–1.850 –1.475 –1.105 –0.810–0.810–0.960OR –0.980VILA maxGate Input(Applied test voltage) V BB ≈ – 1.29V(Switching Threshold)HighStateNOR –1.630–1.650Low–1.850 StateV IH maxV IHA minV OH maxV OH minV OL maxV OL minVIL minGate Input(Applied test voltage)–1.95 –1.48 –1.13 –0.810–0.810–0.980ORV IL maxV BB ≈ –1.29V(Switching Threshold)HighStateNOR–1.630–1.950LowStateMECL TRANSFER CURVESFor MECL logic gates, the dual (complementary) outputsmust be represented by two transfer curves: one to describethe OR switching action and one to describe the NORswitching action. Typical transfer curves and associated datafor the MECL 10K/10H family are shown in Figure 8 andFigure 9, respectively.It is not necessary to measure transfer curves at all pointsof the curves. To guarantee correct operation it is sufficientmerely to measure two sets of min/max logic levelparameters.The first set is obtained for 10K by applying test voltages,VIL min and VIH max (sequentially) to the gate inputs, andmeasuring the OR and NOR output levels to make sure theyare between VOL max and VOL min, and VOH max and VOH minspecifications.The second set of logic level parameters relates to theswitching thresholds. This set of data is distinguished by an“A” in symbol subscripts. A test voltage, VILA max, isapplied to the gate and the NOR and OR outputs aremeasured to see that they are above the VOHA min and belowthe VOLA max levels, respectively. Similar checks are madeusing the test input voltage VIHA min.The result of these specifications insures that:(a) The switching threshold (≈ VBB) falls within thedarkest rectangle; i.e. switching does not begin outside thisrectangle;(b) Quiescent logic levels fall in the lightest shadedranges;(c) Guaranteed noise immunity is met.As shown in Figure 10, MECL 10K outputs rise withincreasing ambient temperature. All circuits in each familyhave the same worst–case output level specificationsregardless of power dissipation or junction temperaturedifferences to reduce loss of noise margin due to thermaldifferences.All of these specifications assume –5.2 V power supplyoperation. Operation at other power–supply voltages ispossible, but will result in further transfer curve changes.Table 6 gives rate of change of output voltages as a functionof power supply.OUTPUT VOLTAGE(VOLTS)Figure 10 – TYPICAL TRANSFERCHARACTERISTICS AS A FUNCTIONOF TEMPERATURE (MECL 10K)–0.950–1.350–1.750–30°C85°C25°C85°C–30°C85°C–1.6 –1.4 –1.2 –1.085°C25°C NOR OUTPUT–30°C–30°CINPUT VOLTAGE (VOLTS)25°COR OUTPUT25°CTable 6 – TYPICAL LEVEL CHANGE RATES / 1VVoltage MECL 10H MECL 10K∆VOH/∆VEE 0.008 0.016∆VOL/∆VEE 0.020 0.250∆VBB/∆VEE 0.010 0.148http://onsemi.com22

NOISE MARGIN“Noise margin” is a measure of logic circuit’s resistanceto undesired switching. MECL noise margin is defined interms of the specification points surrounding the switchingthreshold. The critical parameters of interest here are thosedesignated with the “A” subscript (VOHA min, VOLA max,VIHA min, VILA max) in the transfer characteristic curves.MECL 10H is specified and tested with:VOHA min = VOH minVOLA max = VOL maxVIHA min = VIH minandVILA max = VIL maxGuaranteed noise margin (NM) is defined as follows:NMHIGH LEVEL = VOHA min – VIHA minNMLOW LEVEL = VILA max – VOLA maxTo see how noise margin is computed, assume a MECLgate drives a similar MECL gate, Figure 11.At a gate input (point B) equal to VILA max, MECL gate#2 can begin to enter the shaded transition region.This is a “worst case” condition, since the VOLA maxspecification point guarantees that no device can enter thetransition region before an input equal to VILA max isreached. Clearly then, VILA max is one critical point for noisemargin computation, since it is the edge of the transitionregion.To find the other critical voltage, consider the output fromMECL gate #1 (point A). What is the most positive valuepossible for this voltage (considering worst casespecifications)? From Figure 11 it can be observed that theVOLA max specification insures that the LOW state ORoutput from gate #1 can be no greater than VOLA max.Note that VOLA max is more negative than VILA max. Thus,with VOLA max at the input to gate #2, the transition regionis not yet reached. (The input voltage to gate #2 is still to theleft of VILA max on the transfer curve.)In order to ever run the chance of switching gate #2, wewould need an additional voltage, to move the input fromVOLA max to VILA max. This constitutes the “safety factor”known as noise margin. It can be calculated as the magnitudeof the difference between the two specification voltages, orfor the MECL 10K levels shown:NMLOW – VILA max – VOLA max– –1.475 V – (–1.630 V)– 155 mV.Similarly, for the HIGH state:NMHIGH – VOHA min – VIHA min– –0.980 V – (–1.105 V)– 125 mVAnalogous results are obtained when considering the“NOR” transfer data.Note that these noise margins are absolute worst caseconditions. The lessor of the two noise margins is that for theHIGH state, 125 mV. This then, constitutes the guaranteedmargin against signal undershoot, and power or thermaldisturbances.As shown in the table, typical noise margins are usuallybetter than guaranteed – by about 75 mV. For MECL 10H the“noise margin” is 150 mV for NM low and NM high. (SeeSection 3 for details.)Noise margin is a dc specification that can be calculated,since it is defined by specification points tabulated onMECL data sheets. However, by itself, this specificationdoes not give a complete picture regarding the noiseimmunity of a system built with a particular set of circuits.Overall system noise immunity involves not onlynoise–margin specifications, but also other circuit–relatedfactors that determine how difficult it is to apply a noisesignal of sufficient magnitude and duration to cause thecircuit to propagate a false logic state. In general, then, noiseimmunity involves line impedances, circuit outputimpedances, and propagation delay in addition tonoise–margin specifications. This subject to discussed ingreater detail in the MECL System Design Handbook,HB205/D.http://onsemi.com23

Figure 11 – MECL Noise Margin DataVOHA MIN–1.475 –1.105OR–0.980HIGHSTATEV V High NoiseMarginLow NoiseMarginVOHA MIN *VIHA MIN *VILA MAX *VOLA MAX *GATEOUTPUTGATEINPUTVOLA MAX#1AVILA MAX VIHA MINVBB (SWITCHING THRESHOLD)BC–1.630Specification Points for Determining Noise Margin#2LOWSTATEFamily*V OHA min = V OH min , V OLA max =V OL max , V IHA min = V IH min andV ILA max = V IL max for MECL 10H.Noise Margin ComputationsGuaranteedWorst–Case dcNoise Margin(V)Typical dcNoise Margin(V)MECL 10H 0.150 0.270MECL 10K 0.125 0.210AC OR SWITCHING PARAMETERSTime–dependent specifications are those that define theeffects of the circuit on a specified input signal, as it travelsthrough the circuit. They include the time delay involved inchanging the output level from one logic state to another. Inaddition, they include the time required for the output of acircuit to respond to the input signal, designated aspropagation delay, MECL waveform and propagation delayterminologies are depicted in Figure 12. Specific rise, fall,and propagation delay times are given on the data sheet foreach specific functional block, but like the transfercharacteristics, ac parameters are temperature and voltagedependent. Typical variations for MECL 10K are given inthe curves of Figure 13 through Figure 16.Figure 12 – TYPICAL LOGIC WAVEFORMSOVERSHOOTUNDERSHOOT50%UNDERSHOOTVIHAVILAMECL WAVEFORM TERMINOLOGYVOUTT–80%20%T– = TF T+ = TRT+HIGH LEVELVBBLOW LEVEL50%VINT– –*T++ *VOUT OR 50%T– +*T+ –*VOUT NOR 50%*TPD = T – + T + +MECL 10K and MECL 10H Rise and Fall TimesMECL Propagation Delayhttp://onsemi.com24

t– – PROPAGATION DELAY (ns)Figure 13 – TYPICAL PROPAGATION DELAY t– – versusVEE AND TEMPERATURE (MECL 10K)2.62.52.42.32.22.12.01.91.81.71.650 Ω LOAD TO –2.0 VORNOR–3.6 –4.4 –5.2 –6.0 –6.8VEE, SUPPLY VOLTAGE (VOLTS)+85°C25°C–30°C85°C25°C–30°CFigure 14 – TYPICAL PROPAGATION DELAY t+ + versus VEEAND TEMPERATURE (MECL 10K)t++ PROPAGATION DELAY (ns)2.52.42.32.22.12.01.91.81.71.61.550 Ω LOAD TO –2.0 VNOROR–3.6 –4.4 –5.2 –6.0 –6.8VEE, SUPPLY VOLTAGE (VOLTS)85°C25°C–30°C85°C25°C–30°Ct–, FALL TIME (ns)Figure 15 – TYPICAL FALL TIME (90% to 10%) versusTEMPERATURE AND SUPPLY VOLTAGE (MECL 10K)3.93.83.73.63.53.43.33.23.13.02.950 Ω LOAD TO –2.0 VNOROR–3.6 –4.4 –5.2 –6.0 –6.8VEE, SUPPLY VOLTAGE (VOLTS)85°C25°C–30°C85°C25°C–30°Ct+, RISE TIME5.25.04.84.64.44.03.83.63.2Figure 16 – TYPICAL FALL TIME (10% to 90%) versusTEMPERATURE AND SUPPLY VOLTAGE (MECL 10K)4.23.450 Ω LOAD TO –2.0 VNOROR–3.6 –4.4 –5.2 –6.0 –6.8VEE, SUPPLY VOLTAGE (VOLTS)85°C25°C–30°C85°C25°C–30°CSETUP AND HOLD TIMESSetup and hold times are two ac parameters which caneasily be confused unless clearly defined. For MECL logicdevices, tsetup is the minimum time (50% – 50%) before thepositive transition of the clock pulse (C) that informationmust be present at the Data input (D) to insure properoperation of the device. The thold is defined similarly as theminimum time after the positive transition of the clock pulse(C) that the information must remain unchanged at the Datainput (D) to insure proper operation. Setup and holdwaveforms for logic devices are shown in Figure 17.Figure 17 – SETUP AND HOLD WAVEFORMSFOR MECL LOGIC DEVICESDCQ50%50%THOLDTSETUP50%Qhttp://onsemi.com25

TESTING MECL 10H AND MECL 10KTo obtain results correlating with ON Semiconductorcircuit specifications certain test techniques must be used. Aschematic of a typical gate test circuit is shown in Figure 18.This test circuit is the standard ac test configuration for mostMECL devices. (Exceptions are shown with devicespecification.)A solid ground plane is used in the test setup, andcapacitors bypass VCC1, VCC2, and VEE pins to ground. Allpower leads and signal leads are kept as short as possible.The sampling scope interface runs directly to the 50–ohminputs of Channel A and B via 50–ohm coaxial cable.Equal–length coaxial cables must be used between the testset and the A and B scope inputs. A 50–ohm coax cable suchas RG58/U or RG188A/U, is recommended.Interconnect fittings should be 50–ohm GR, BNC,Sealectro Conhex, or equivalent. Wire length should be < 1 4inch from TPin to input pin and TPout to output pin.The pulse generator must be capable of 2.0 ns rise and falltimes for MECL 10K and 1.5 ns for MECL 10H and MECLIII. In addition, the generator voltage must have an offset togive MECL signal swings of ≈ ±400 mV about a thresholdof ≈ +0.7 V when VCC = +2.0 and VEE = –3.2 V for ac testingof logic devices.The power supplies are shifted +2.0 V, so that the deviceunder test has only one resistor value to load into theprecision 50–ohm input impedance of the samplingoscilloscope. Use of this technique yields a close correlationbetween ON Semiconductor and customer testing. Unusedoutputs are loaded with a 50–ohm resistor (100–ohm forMC105XX devices) to ground. The positive supply (VCC)should be decoupled from the test board by RF type 25 µFcapacitors to ground. The VCC pins are bypassed to groundwith 0.1 µF, as is the VEE pin.Additional information on testing MECL 10K andunderstanding data sheets is found in Application NoteAN701/D and the MECL System Design Handbook,HB205/D.Figure 18 – MECL LOGIC SWITCHING TIME TEST SETUPSCOPECHANNEL ASCOPECHANNEL B* Matched 50–ohm coax** 0.1 µF–decouples fixture*** 25 µF–dampens supply variationsORNOR*COAX *COAX *COAXPULSE††GENERATORCOAXD.U.T.**1 16 8**††Pulse generator must be capable of riseand fall times 2.0 ns for 10K and1.0 ns for 10H.***NOTE: All power supply levelsare shown shifted 2 voltspositive.+2.0 VVCC–3.2 VVEEhttp://onsemi.com26

OPERATIONAL DATAPOWER SUPPLY CONSIDERATIONSMECL circuits are characterized with the VCC point atground potential and the VEE point at –5.2 V. While thisMECL convention is not necessarily mandatory, it doesresult in maximum noise immunity. This is so because anynoise induced on the VEE line is applied to the circuit as acommon–mode signal which is rejected by the differentialaction of the MECL input circuit. Noise induced into theVCC line is not cancelled out in this fashion. Hence, a goodsystem ground at the VCC bus is required for best noiseimmunity. Also, MECL 10H circuits may be operated withVEE at –4.5 V with a negligible loss of noise immunity.Power supply regulation which will achieve 10%regulation or better at the device level is recommended. The–5.2 V power supply potential will result in best circuitspeed. Other values for VEE may be used. A more negativevoltage will increase noise margins at a cost of increasedpower dissipation. A less negative voltage will have just theopposite effect. (Noise margins and performancespecifications of MECL 10H are unaffected by variations inVEE because of the internal voltage regulation.)On logic cards, a ground plane or ground bus systemshould be used. A bus system should be wide enough toprevent significant voltage drops between supply and deviceand to produce a low source inductance.Although little power supply noise is generated by MECLlogic, power supply bypass capacitors are recommended tohandle switching currents caused by stray capacitance andasymmetric circuit loading. A parallel combination of a 1.0µF and a 100 pF capacitor at the power entrance to the board,and a 0.01 µF low–inductance capacitor between groundand the –5.2 V line every four to six packages, arerecommended.Most MECL 10H, MECL 10K and MECL III circuitshave two VCC leads. VCC1 supplies current to the outputtransistors and VCC2 is connected to the circuit logictransistors. The separate VCC pins reduce cross–couplingbetween individual circuits within a package when theoutputs are driving heavy loads. Circuits with large drivecapability, similar to the MC10110, have two VCC1 pins. AllVCC pins should be connected to the ground plane or groundbus as close to the package as possible.For further discussion of MECL power supplyconsiderations to be made in system designing, see MECLSystem Design Handbook, HB205/D.POWER DISSIPATIONThe power dissipation of MECL functional blocks isspecified on their respective data sheets. This specificationdoes not include power dissipated in the output devices dueto output termination. The omission of internal outputpulldown resistors permits the use of external terminationsdesigned to yield best system performance. To obtain totaloperating power dissipation of a particular functional blockin a system, the dissipation of the output transistor, underload, must be added to the circuit power dissipation.Table 7 lists the power dissipation in the output transistorsplus that in the external terminating resistors, for the morecommonly used termination values and circuitconfigurations. To obtain true package power dissipation,one output–transistor power–dissipation value must beadded to the specified package power dissipation for eachexternal termination resistor used in conjunction with thatpackage. To obtain system power dissipation, the stateddissipation in the external terminating resistors must beadded as well. Unused outputs draw no power and may beignored.Table 7 – AVERAGE POWER DISSIPATION IN OUTPUTCIRCUIT WITH EXTERNAL TERMINATING RESISTORSTerminatingResistor ValueOutputTransistorPowerDissipation(mW)TerminatingResistorPowerDissipation(mW)150 ohms to –2.0 Vdc 5.0 4.3100 ohms to –2.0 Vdc 7.5 6.575 ohms to –2.0 Vdc 10 8.750 ohms to –2.0 Vdc 15 132.0 k ohms to VEE 2.5 7.71.0 k ohm to VEE 4.9 15.4680 ohms to VEE 7.2 22.6510 ohms to VEE 9.7 30.2270 ohms to VEE 18.3 57.282 ohms to VCC and 15 140CC130 ohms to VEELOADING CHARACTERISTICSThe differential input to MECL circuits offers severaladvantages. Its common–mode–rejection feature offersimmunity against power–supply noise injection, and itsrelatively high input impedance makes it possible for anycircuit to drive a relatively large number of inputs withoutdeterioration of the guaranteed noise margin. Hence, dcfanout with MECL circuits does not normally present adesign problem.Graphs showing typical output voltage levels as a functionof load current for MECL 10H, MECL 10K and MECL IIIshown in Figure 19. These graphs can be used to determinethe actual output voltages for loads exceeding normaloperation.http://onsemi.com27

While dc loading causes a change in output voltage levels,thereby tending to affect noise margins, ac loading increasesthe capacitances associated with the circuit and, therefore,affects circuit speed, primarily rise and fall times.MECL circuits typically have a 7 ohm output impedanceand a relatively unaffected by capacitive loading on apositive–going output signal. However, the negative–goingedge is dependent on the output pulldown or terminationresistor. Loading close to a MECL output pin will cause anadditional propagation delay of 0.1 ns per fanout load witha 50 ohm resistor to –2.0 Vdc or 270 ohms to –5.2 Vdc. A100 ohm resistor to –2.0 Vdc or 510 ohms to –5.2 Vdc resultsin an additional 0.2 ns propagation delay per fanout load.Terminated transmission line signal interconnections areused for best system performance. The propagation delayand rise time of a driving gate are affected very little bycapacitance loading along a matched parallel–terminatedtransmission line. However, the delay and characteristicimpedance of the transmission line itself are affected by thedistributed capacitance. Signal propagation down the linewill be increased by a factor, 21 C d C o . Here Co is thenormal intrinsic line capacitance, and Cd is the distributedcapacitance due to loading and stubs off the line.Maximum allowable stub lengths for loading off of aMECL 10K transmission line vary with the line impedance.For example, with Zo = 50 ohms, maximum stub lengthwould be 4.5 inches (1.8 in. for MECL III). But when Zo =100 ohms, the maximum allowable stub length is decreasedto 2.8 inches (1.0 in. for MECL III).The input loading capacitance of a MECL 10H and MECL10K gate is about 2.9 pF and 3.3 pF for MECL III. To allowfor the IC connector or solder connection and a short stublength, 5 to 7 pF is commonly used in loading calculations.UNUSED MECL INPUTSThe input impedance of a differential amplifier, as used inthe typical MECL input circuit, is very high when theapplied signal level is low. Under low–signal conditions,therefore, any leakage to the input capacitance of the gatecould cause a gradual buildup of voltage on the input lead,thereby adversely affecting the switching characteristics atlow repetition rates.All single–ended input MECL logic circuits contain inputpulldown resistors between the input transistor bases andVEE. As a result, unused inputs may be left unconnected (theresistor provides a sink for ICBO leakage currents, and inputsare held sufficiently negative that circuits will not triggerdue to noise coupled into such inputs). Input pulldownresistor values are typically 50 kΩ and are not to be used aspulldown resistors for preceding open–emitter outputs.Some MECL devices do not have input pulldowns.Examples are the differential line receivers. If a singledifferential receiver within a package is unused, one input ofthat receiver must be tied to the VBB pin provided, and theother input goes to VEE or is left open.MECL circuits do not operate properly when inputs areconnected to VCC for a HIGH logic level. Proper designpractice is to set a HIGH level about –0.9 volts below VCCwith a resistor divider, a diode drop, or an unused gateoutput.IOUT (mA)IOUT (mA)5040302010050403020Figure 19 – OUTPUT VOLTAGE LEVELSversus DC LOADING(LOAD LINES FOR TERMINATION TO –2.0 VDC) 25°C100 OHMS50 OHMS75 OHMSVOH minVOHmaxVIHAVBBVILAVOLmaxVOLmin0 –0.5 –1.0 –1.5 –2.0V OUT (VOLTS)(LOAD LINES FOR TERMINATION TO VEE (–5.2 VDC) 25°C200 Ohms270 OhmsVOH maxVIHAVOH minVBB–VILAVOLmaxVOLmin500 Ohms101 K Ohms2 K Ohms00 –0.5 –1.0 –1.5 –2.0V OUT (VOLTS)http://onsemi.com28

SYSTEM DESIGN CONSIDERATIONSTHERMAL MANAGEMENTCircuit performance and long–term circuit reliability areaffected by die temperature. Normally, both are improved bykeeping the IC junction temperatures low.Electrical power dissipated in any integrated circuit is asource of heat. This heat source increases the temperature ofthe die relative to some reference point, normally theambient temperature of 25°C in still air. The temperatureincrease, then, depends on the amount of power dissipatedin the circuit and on the net thermal resistance between theheat source and the reference point.The temperature at the junction is a function of thepackaging and mounting system’s ability to remove heatgenerated in the circuit – from the junction region to theambient environment. The basic formula (a) for convertingpower dissipation to estimated junction temperature is:TJ = TA + PD(θJC + θCA) (1)orTJ = TA + PD(θJA) (2)whereTJ = maximum junction temperatureTA = maximum ambient temperaturePD = calculated maximum power dissipationincluding effects of external loads (seePower Dissipation in section III).θJC = average thermal resistance, junction to caseθCA = average thermal resistance, case to ambientθJA = average thermal resistance, junction toambientThis ON Semiconductor recommended formula has beenapproved by RADC and DESC for calculating a “practical”maximum operating junction temperature forMIL–M–38510 (JAN) MECL 10K devices.Only two terms on the right side of equation (1) can bevaried by the user – the ambient temperature, and the devicecase–to–ambient thermal resistance, θCA. (To some extentthe device power dissipation can be also controlled, butunder recommended use the VEE supply and loading dictatea fixed power dissipation.) Both system air flow and thepackage mounting technique affect the θCA thermalresistance term. θJC is essentially independent of air flowand external mounting method, but is sensitive to packagematerial, die bonding method, and die area.Table 8 – THERMAL RESISTANCE VALUES FOR STANDARD MECL I/C PACKAGESThermal Resistance in Still AirPackage DescriptionθJAθJCNo.BodyBodyBodyDieDie AreaFlag Area(°C/Watt)(°C/Watt)Leads Style Material WxLBond (Sq. Mils) (Sq. Mils) Avg. Max. Avg. Max.8 DIL EPOXY 1/4″×3/8″ EPOXY 2496 8100 102 133 50 808 DIL ALUMINA 1/4″×3/8″ SILVER/GLASS 2496 N/A 140 182 35 5614 DIL EPOXY 1/4″×3/4″ EPOXY 4096 6400 84 109 38 6114 DIL ALUMINA 1/4″×3/4″ SILVER/GLASS 4096 N/A 100 130 25 4016 DIL EPOXY 1/4″×3/4″ EPOXY 4096 12100 70 91 34 5416 DIL ALUMINA 1/4″×3/4″ SILVER/GLASS 4096 N/A 100 130 25 4020 PLCC EPOXY 0.35″×0.35″ EPOXY 4096 14,400 74 82 N/A (6) N/A (6)24 DIL (4) EPOXY 1/2″×1–1/4″ EPOXY 8192 22500 67 87 31 5024 DIL (5) ALUMINA 1/2″×1–1/4″ SILVER/GLASS 8192 N/A 50 65 10 1628 PLCC EPOXY 0.45″×0.45″ EPOXY 7134 28,900 65 68 N/A (6) N/A (6)NOTES:1. All plastic packages use copper lead frames – ceramic packages use alloy 42 frames.2. Body style DIL is “Dual–In–Line.”3. Standard Mounting Methods:a. Dual–In–Line In Socket or P/C board with no contact between bottom of package and socket or P/C board.b. PLCC packages solder attached to traces on 2.24″ × 2.24″ × 0.062″ FR4 type glass epoxy board with 1 oz./S.F. copper (solder coated)mounted to tester with 3 leads of 24 gauge copper wire.4. Case Outline 6495. Case Outline 6236. JC JA–. T C –T AP D.T C = Case Temperature (determined by thermocouple)http://onsemi.com29

For applications where the case is held at essentially afixed temperature by mounting on a large ortemperature–controlled heatsink, the estimated junctiontemperature is calculated by:TJ = TC + PD (θJC) (3)where TC = maximum case temperature and the otherparameters are as previously defined.The maximum and average thermal resistance valuesfor standard MECL IC packages are given in Table 8. In ,this basic data is converted into graphs showing themaximum power dissipation allowable at various ambienttemperatures (still air) for circuits mounted in the differentpackages, taking into account the maximum permissibleoperating junction temperature for long term life (100,000 hours for ceramic packages).AIR FLOWThe effect of air flow over the packages on θJA (due to adecrease in θCA) is illustrated in the graphs of Figure 20through Figure 22. This air flow reduces the thermalresistance of the package, therefore permitting acorresponding increase in power dissipation withoutexceeding the maximum permissible operating junctiontemperature.As an example of the use of the information above, themaximum junction temperature for a 16 lead ceramicdual–in–line packaged MECL 10K quad OR/NOR gate(MC10101L) loaded with four 50 ohm loads can becalculated. Maximum total power dissipation (including 4output loads) for this quad gate is 195 mW. Assume for thisthermal study that air flow is 500 linear feet per minute.From Figure 23, θJA is 50°C/W. With TA (air flowtemperature at the device) equal to 25°C, the followingmaximum junction temperature results:TJ = PD (θJA) + TATJ = (0.195 W) (50°C/W) + 25°C = 34.8°CUnder the above operating conditions, the MECL 10Kquad gate has its junction elevated above ambienttemperature by only 9.8°C.Even though different device types mounted on a printedcircuit board may each have different power dissipations, allwill have the same input and output levels provided that eachis subject to identical air flow and the same ambient airtemperature. This eases design, since the only change inlevels between devices is due to the increase in ambienttemperatures as the air passes over the devices, ordifferences in ambient temperature between two devices.MAXIMUM ALLOWED POWER DISSIPATION (mW/Pkg)350030002500200015001000500Figure 20 – AMBIENT TEMPERATURE DERATINGCURVES (Ceramic Dual–In–Line Pkg)24 Lead14 and 16 Lead8 LeadAlumina Ceramic forAll Packages025 50 75 100 125 150 165 175 200T A , AMBIENT TEMPERATURE⎯STILL AIR (°C)MAXIMUM ALLOWED POWER DISSIPATION (mW/Pkg)20001750150012501000750500250Figure 21 – AMBIENT TEMPERATUREDERATING CURVES (Plastic Dual–In–Line Pkg)24 Lead8 Lead16 Lead14 Lead025 50 75 100 125 140 150 175 200T A , AMBIENT TEMPERATURE ⎯ STILL AIR (°C)MAXIMUM ALLOWED POWER DISSIPATION (mW/Pkg)2000175015001250100075050025000Figure 22 – AMBIENT TEMPERATUREDERATING CURVES (PLCC Pkg)20 Lead28 Lead25 50 75 100 125 150 175 200T A , AMBIENT TEMPERATURE (°C) ⎯ STILL AIRhttp://onsemi.com30

, AVERAGE THERMAL RESISTANCE ( C/W)°JAθFigure 23 – AIRFLOW versus THERMAL RESISTANCE(Ceramic Dual–In–Line Pkg)2001801601401201008060402008 Lead (Alumina)Z–Axis (Transverse)24 Lead (Alumina)Airflow Direction14 and 16 Lead (Alumina)200 400 600 800 1000, AVERAGE THERMAL RESISTANCE ( C/W) °θ JA200180160140120100806040200Figure 24 – AIRFLOW versus THERMALRESISTANCE (Plastic Dual–In–Line Pkg)8 Lead24 LeadZ–Axis (Transverse)14 Lead 16 LeadAirflow Direction200 400 600 800 1000AIRFLOW (Ifpm)Figure 25 – AIRFLOW versus THERMAL RESISTANCE(PLCC Pkg), AVERAGE THERMAL RESISTANCE ( C/W)°10080604020Z–Axis (Transverse)Airflow Direction20 Lead28 LeadJAθ0250 500 750 1000AIRFLOW (Ifpm)Table 9 – THERMAL GRADIENT OF JUNCTIONTEMPERATURE(16–Pin MECL Dual–In–Line Package)Power Dissipation(mW)Junction Temperature Gradient(°C/Package)200 0.4250 0.5300 0.63400 0.88Devices mounted on 0.062″ PC board with Z axis spacing 0.5″. Air flow is500 lfpm along the Z axis.The majority of MECL 10H, MECL 10K, and MECL IIIusers employ some form of air–flow cooling. As air passesover each device on a printed circuit board, it absorbs heatfrom each package. This heat gradient from the first packageto the last package is a function of the air flow rate andindividual package dissipations. Table 9 provides gradientdata at power levels of 200 mW, 250 mW, 300 mW, and 400mW with an air flow rate of 500 lfpm. These figures showthe proportionate increase in the junction temperature ofeach dual–in–line package as the air passes over eachdevice. For higher rates of air flow the change in junctiontemperature from package to package down the airstreamwill be lower due to greater cooling.OPTIMIZING THE LONG TERM RELIABILITY OFPLASTIC PACKAGESTodays plastic integrated circuit packages are as reliableas ceramic packages under most environmental conditions.However when the ultimate in system reliability is required,thermal management must be considered as a prime systemdesign goal.Modern plastic package assembly technology utilizesgold wire bonded to aluminum bonding pads throughout theelectronics industry. When exposed to high temperatures forprotracted periods of time an intermetallic compound canform in the bond area resulting in high impedance contactsand degradation of device performance. Since the formationof intermetallic compounds is directly related to devicejunction temperature, it is incumbent on the designer todetermine that the device junction temperatures areconsistent with system reliability goals.http://onsemi.com31

Predicting Bond Failure Time:Based on the results of almost ten (10) years of +125°Coperating life testing, a special arrhenius equation has beendeveloped to show the relationship between junctiontemperature and reliability.(1) T (6.376 10 )e* -9 11554.267273.15 T J*Where:T = Time in hours to 0.1% bond failure (1failure per 1,000 bonds).TJ = Device junction temperature, °C.And:(2) TJ = TA + PDθJA = TA + ∆TJWhere:TJ = Device junction temperature, °C.TA = Ambient temperature, °C.PD = Device power dissipation in watts.θJA = Device thermal resistance, junction to air,°C/Watt.∆TJ = Increase in junction temperature due toon–chip power dissipation.Table 10 shows the relationship between junctiontemperature, and continuous operating time to 0.1% bondfailure, (1 failure per 1,000 bonds).Table 10 – DEVICE JUNCTION TEMPERATUREversus TIME TO 0.1% BOND FAILURESJunction Temp °C Time, Hours Time, Years80 1,032,200 117.890 419,300 47.9100 178,700 20.4110 79,600 9.4120 37,000 4.2130 17,800 2.0140 8,900 1.0Table 10 is graphically illustrated in Figure 26 whichshows that the reliability for plastic and ceramic devices arethe same until elevated junction temperatures inducesintermetallic failures in plastic devices. Early and mid–lifefailure rates of plastic devices are not effected by thisintermetallic mechanism.Figure 26. FAILURE RATE versus TIMEJUNCTION TEMPERATUREMECL Junction Temperatures:Power levels have been calculated for a number of MECL10K and MECL 10H devices in 20 pin plastic leaded chipcarriers and translated to the resulting increase of junctiontemperature (∆TJ) for still air and moving air at 500 LFPMusing equation 2 and are shown in Table 11.Table 11 – INCREASE IN JUNCTION TEMPERATUREDUE TO I/C POWER DISSIPATION.20 PIN PLASTIC LEADED CHIP CARRIERMECL 10KDeviceTypeMC10101MC10102MC10103MC10104MC10105MC10106MC10107MC10109MC10110MC10111MC10113MC10114MC10115MC10116MC10117MC10121MC10123MC10124MC10125MC10131MC10133MC10134MC10135MC10136MC10138MC10141MC10153MC10158MC10159MC10160MC10161MC10162MC10164MC10165MC10166MC10168MC10170MC10171MC10172MC10173MC10174MC10175MC10176MC10178MC10186MC10188MC10189MC10192MC10195MC10197MC10198MC10210MC10211MC10212MC10216MC10231∆T J , °CStill Air21.817.617.620.817.213.019.811.724.724.722.222.616.717.216.213.537.642.9–26.934.427.031.952.337.042.734.423.925.832.040.740.731.353.743.534.429.941.141.130.531.943.749.638.149.625.424.667.046.727.721.224.524.624.324.130.6∆T J , °C500LFPMAir14.111.411.413.411.28.412.87.716.116.114.314.610.911.110.58.524.027.3–17.121.917.220.332.623.226.721.915.216.420.426.026.020.133.627.621.918.926.226.219.320.527.631.323.931.116.415.943.029.917.713.416.016.015.815.619.5MECL 10HDeviceTypeMC10H016MC10H100MC10H101MC10H102MC10H103MC10H104MC10H105MC10H106MC10H107MC10H109MC10H113MC10H115MC10H116MC10H117MC10H121MC10H123MC10H124MC10H125MC10H130MC10H135MC10H136MC10H141MC10H158MC10H159MC10H160MC10H161MC10H162MC10H164MC10H165MC10H166MC10H171MC10H172MC10H173MC10H174MC10H175MC10H176MC10H179MC10H180MC10H181 4MC10H186MC10H188MC10H189MC10H209MC10H210MC10H211MC10H330 4MC10H332MC10H334MC10H350MC10H351MC10H352MC10H424∆T J , °CStill Air48.016.622.118.018.021.017.813.220.011.922.816.717.816.713.923.144.2–28.233.261.744.325.327.332.141.541.531.956.344.441.941.932.632.545.950.935.042.464.450.225.825.818.925.025.065.852.277.8–27.227.237.7∆T J , °C500LFPMAir30.010.814.511.811.813.511.78.712.97.814.810.911.711.09.115.028.4–18.221.438.528.016.417.720.526.726.720.635.828.326.926.921.121.029.632.322.627.238.631.816.716.712.516.416.436.133.549.3–18.118.124.3NORMALIZED FAILURE RATE1.0FAILURE RATE OF PLASTIC = CERAMICUNTIL INTERMETALLICS OCCURT = 130 C°JT = 120 C°JT = 110 C°JT = 100 C°J°T = 90 CJ°T = 80 CJNOTES:(1) All ECL outputs are loaded with a 50 Ω resistor and assumed operating at 50%duty cycle.(2) ∆T J for ECL to TTL translators are excluded since the supply current to the TTLsection is dependent on frequency, duty cycle and loading.(3) Thermal Resistance (θ JA ) measured with PLCC packages solder attached totraces on 2.24″ x 2.24″ x 0.062″ FR4 type glass epoxy board with 1 oz./sq. ft.copper (solder–coated) mounted to tester with 3 leads of 24 gauge copper wire.(4) 28 lead PLCC.1 10 100 1000TIME, YEARShttp://onsemi.com32

Case Example:After the desired system failure rate has been establishedfor failure mechanisms other than intermetallics, eachplastic device in the system should be evaluated formaximum junction temperature using Table 11. Knowingthe maximum junction temperature refer to Table 10 orEquation 1 to determine the continuous operating timerequired to 0.1% bond failures due to intermetallicformation. At this time, system reliability departs from thedesired value as indicated in Figure 26.To illustrate, assume that system ambient air temperatureis 55°C (an accepted industry standard for evaluating systemfailure rates). Reference is made to Table 11 to determine themaximum junction temperature for each device for still airand transverse air flow of 500 LFPM.Adding the 55°C ambient to the highest, ∆TJ listed,77.8°C (for the MC10H334 with no air flow), gives amaximum junction temperature of 132.8°C. Reference toTable 10 indicates a departure from the desired failure rateafter about 2 years of constant exposure to this junctiontemperature. If 500 LFPM of air flow is utilized, maximumjunction temperature for this device is reduced to 104.3°Cfor which Table 10 indicates an increased failure rate inabout 15 years.Air flow is one method of thermal management whichshould be considered for system longevity. Other commonlyused methods include heat sinks for higher powered devices,refrigerated air flow and lower density board stuffing.The material presented here emphasizes the need toconsider thermal management as an integral part of systemdesign and also the tools to determine if the managementmethods being considered are adequate to produce thedesired system reliability.THERMAL EFFECTS ON NOISE MARGINThe data sheet dc specifications for standard MECL 10Kand MECL III devices are given for an operatingtemperature range from –30°C to +85°C (0° to +75°C forMECL 10H and memories). These values are based onhaving an airflow of 500 lfpm over socket or P/C boardmounted packages with no special heatsinking (i.e.,dual–in–line package mounted on lead seating plane with nocontact between bottom of package and socket or P/C boardand flat package mounted with bottom in direct contact withnon–metalized area of P/C board).The designer may want to use MECL devices underconditions other than those given above. The majority of thelow–power device types may be used without air and withhigher θJA. However, the designer must bear in mind thatjunction temperatures will be higher for higher θJA, eventhough the ambient temperature is the same. Higher junctiontemperatures will cause logic levels to shift.As an example, a 300 mW 16 lead dual–in–line ceramicdevice operated at θJA = 100°C/W (in still air) shows aHIGH logic level shift of about 21 mV above the HIGH logiclevel when operated with 500 lfpm air flow and a θJA =50°C/W. (Level shift = ∆TJ × 1.4 mV/°C).If logic levels of individual devices shift by differentamounts (depending on PD and θJA), noise margins aresomewhat reduced. Therefore, the system designer must layout his system bearing in mind that the mounting proceduresto be used should minimize thermal effects on noise margin.The following sections on package mounting andheatsinking are intended to provide the designer withsufficient information to insure good noise margins and highreliability in MECL system use.MOUNTING AND HEATSINK SUGGESTIONSWith large high–speed logic systems, the use of multilayerprinted circuit boards is recommended to provide both abetter ground plane and a good thermal path for heatdissipation. Also, a multilayer board allows the use ofmicrostrip line techniques to provide transmission lineinterconnections.Two–sided printed circuit boards may be used whereboard dimensions and package count are small. If possible,the VCC ground plane should face the bottom of the packageto form the thermal conduction plane. If signal lines must beplaced on both sides of the board, the VEE plane may be usedas the thermal plane, and at the same time may be used as apseudo ground plane. The pseudo ground plane becomes theac ground reference under the signal lines placed on thesame side as the VCC ground plane (now on the opposite sideof the board from the packages), thus maintaining amicrostrip signal line environment.Two–ounce copper P/C board is recommended forthermal conduction and mechanical strength. Also,mounting holes for low power devices may be countersunkto allow the package bottom to contact the heat plane. Thistechnique used along with thermal paste will provide goodthermal conduction.Printed channeling is a useful technique for conduction ofheat away from the packages when the devices are solderedinto a printed circuit board. As illustrated in Figure 27, thisheat dissipation method could also serve as VEE voltagedistribution or as a ground bus. The channels shouldterminate into channel strips at each side or the rear of aplug–in type printed circuit board. The heat can then beremoved from the circuit board, or board slide rack, bymeans of wipers that come into thermal contact with theedge channels.Figure 27 – CHANNEL/WIPER HEATSINKING ONDOUBLE LAYER BOARDCHANNELWIPERhttp://onsemi.com33

One major advantage of MECL over saturated logic is itscapability for driving matched–impedance transmissionlines. Use of transmission lines retains signal integrity overlong distances. The MECL 10H and MECL 10Kemitter–follower output transistors will drive a 50–ohmtransmission line terminated to –2.0 Vdc. This is theequivalent current load of 22 mA in the HIGH logic state and6 mA in the LOW state.Parallel termination of transmission lines can be done intwo ways. One, as shown in Figure 32, uses a single resistorwhose value is equal to the impedance (Zo) of the line. Aterminating voltage (VTT) of –2.0 Vdc must be supplied tothe terminating resistor.Another method of parallel termination uses a pair ofresistors, R1 and R2. Figure 33 illustrates this method. Thefollowing two equations are used to calculate the values ofR1 and R2:R1 = 1.6 ZoR2 = 2.6 ZoAnother popular approach is the series–terminatedtransmission line (see Figure 32 and Figure 33). This differsfrom parallel termination in that only one–half the logicswing is propagated through the lines. The logic swingdoubles at the end of the transmission line due to reflectionon an open line, again establishing a full logic swing.PULL–DOWN RESISTOR TECHNIQUESV LV LFigure 32 – PARALLEL TERMINATED LINEAt ot pdZ oBZ oV TT (–2.0 V)Figure 33 – PARALLEL TERMINATION – THEVENINEQUIVALENTZ ot o–5.2 VFigure 34 – SERIES TERMINATED LINER1R2–5.2 VRPFigure 29AR PR SBZ oCV EERP–2.0 V ( V TT)RDFigure 30ABCt pdt pd t pdV L50%Vt t L pd pd50%V L /2V L50%–5.2 VRPFigure 31To maintain clean wave fronts, the input impedance of thedriven gate must be much greater than the characteristicimpedance of the transmission line. This condition issatisfied by MECL circuits which have high impedanceinputs. Using the appropriate terminating resistor (RS) atpoint A (Figure 34), the reflections in the transmission linewill be terminated.The advantages of series termination include ease ofdriving multiple series–terminated lines, low powerconsumption, and low cross talk between adjacent lines. Thedisadvantage of this system is that loads may not bedistributed along the transmission line due to the one–halflogic swing present at intermediate points.For board–to–board interconnections, coaxial cable maybe used for signal conductors. The termination techniquesjust discussed also apply when using coax. Coaxial cable hashttp://onsemi.com35

the advantages of good noise immunity and low attenuationat high frequencies.Twisted pair lines are one of the most popular methods ofinterconnecting cards or panels. The complementaryoutputs of any MECL function may be connected to one endof the twisted pair line, and any MECL differential linereceiver to the other as shown in the example, Figure 35. RTis used to terminate the twisted pair line. The 1 to 1.5 Vcommon–mode noise rejection of the line receiver ignorescommon–mode cross talk, permitting multiple twisted pairlines to be tied into cables. MECL signals may be sent verylong distances (> 1000 feet) on twisted pair, although lineattenuation will limit bandwidth, degrading edge speedswhen long line runs are made.If timing is critical, parallel signals paths (shown inFigure 36) should be used when fanout to several cards isrequired. This will eliminate distortion caused by long stublengths off a signal path.Wire–wrapped connections can be used with MECL 10K.For MECL III and MECL 10H, the fast edge speeds (1 ns)create a mismatch at the wire–wrap connections which cancause reflections, thus reducing noise immunity. Themismatch occurs also with MECL 10K, but the distancebetween the wire–wrap connections and the end of the lineis generally short enough so the reflections cause noproblem.Series damping resistors may be used with wire–wrappedlines to extend permissible backplane wiring lengths.Twisted pair lines may be used for even longer distancesacross large wire–wrapped cards. The twisted pair gives amore defined characteristic impedance (than a single wire),and can be connected either single–ended, or differentiallyusing a line receiver.The recommended wire–wrapped circuit cards have aground plane on one side and a voltage plane on the otherside to insure a good ground and a stable voltage source forthe circuits. In addition, the ground plane near thewire–wrapped lines lowers the impedance of those lines andfacilitates terminating the line. Finally, the ground planeserves to minimize cross talk between parallel paths in thesignal lines. Point–to–point wire routing is recommendedbecause cross talk will be minimized and line lengths will beshortest. Commercial wire–wrap boards designed forMECL 10K are available from several vendors.Figure 35 – TWISTED PAIR LINE DRIVER/RECEIVERV EE390390Z o100 R TFigure 36 – PARALLEL FANOUT TECHNIQUES*V EER p*Multiple output gate eg MC10110Microstrip and StriplineZ oZ oZ oV TTCard ACard BCard CCard ACard BCard CR T = Z o (each)Microstrip and stripline techniques are used with printedcircuit boards to form transmission lines. Microstripconsists of a constant–width conductor on one side of acircuit board, with a ground plane on the other side (shownin Figure 37). The characteristic impedance is determinedby the width and thickness of the conductor, the thickness ofthe circuit board, and the dielectric constant of the circuitboard material.Figure 37 – PC INTERCONNECTION LINES FORUSE WITH MECL$ R = 10.0014 (AIR)0.0620.00140.008$ R = 4.5EPOXY GLASS0.008W$ R = 4.5EPOXYGLASSStripline is used with multilayer circuit boards as shownin Figure 37. Stripline consists of a constant–widthconductor between two ground planes.Refer to MECL System Design Handbook for a fulldiscussion of the properties and use of these.CLOCK DISTRIBUTIONClock distribution can be a system problem. At MECL10K speeds, either coaxial cable or twisted pair line (usinghttp://onsemi.com36

the MC10101 and MC10115) can be used to distribute clocksignals throughout a system. Clock line lengths should becontrolled and matched when timing could be critical. Oncethe clocking signals arrive on card, a tree distribution shouldbe used for large–fanouts at high frequency. An example ofthe application of the technique is shown in Figure 38.Because of the very high clock rates encountered inMECL III systems, rules for clocking are more rigorous thanin slower systems.The following guidelines should be followed for bestresults:A. On–card Synchronous Clock Distribution viaTransmission Line1. Use the NOR output in developing clock chains or trees.Do not mix OR and NOR outputs in the chain.2. Use balanced fanouts on the clock drivers.3. Overshoot can be reduced by using two parallel drivelines in place of one drive line with twice the lumpedload.Figure 38 – 64 FANOUT CLOCK DISTRIBUTION(PROPER TERMINATION REQUIRED)ONCARDFAN–OUT = 4EACH5. Parallel drive gates should be used when clockingrepetition rates are high, or when high capacitance loadsoccur. The bandwidth of a MECL III gate may beextended by paralleling both halves of a dual gate.Approximately 40 or 50 MHz bandwidth can be gainedby paralleling two or three clock driver gates.6. Fanout limits should be applied to clock distributiondrivers. Four to six loads should be the maximum loadper driver for best high speed performance. Avoid largelumped loads at the end of lines greater than 3 inches. Alumped load, if used, should be four or fewer loads.7. For wire–OR (emitter dotting), two–way lines (busses)are recommended. To produce such lines, both ends of atransmission line are terminated with 100–ohmimpedance. This method should be used when wire–ORconnections exceed 1 inch apart on a drive line.B. Off–Card Clock Distribution1. The OR/NOR outputs of an MC1660 may be used todrive into twisted pair lines or into flat, fixed–impedanceribbon cable. At the far end of the twisted pair onMC1692 differential line receiver is used. The lineshould be terminated as shown in Figure 35. This methodnot only provides high speed, board–to–board clockdistribution, but also provides system noise marginadvantages. Since the line receiver operatesindependently of the VBB reference voltage (differentialinputs) the noise margin from board to board is alsoindependent of temperature differentials.OFFCARDRT4. To minimize clock skewing problems on synchronoussections of the system, line delays should be matched towithin 1 ns.LOGIC SHORTCUTSMECL circuitry offers several logic design conveniences.Among these are:1. Wire–OR (can be produced by wiring MECL outputemitters together outside packages).2. Complementary Logic Outputs (both OR and NOR arebrought out to package pins in most cases).An example of the use of these two features to reduce gateand package count is shown in Figure 39.The connection shown saves several gate circuits overperforming the same functions with non–ECL type logic.Also, the logic functions in Figure 39 are all accomplishedwith one gate propagation delay time for best system speed.Wire–ORing permits direct connections of MECL circuitsto busses. (MECL System Design Handbook andApplication Note AN726/D).Propagation delay is increased approximately 50 ps perwire–OR connection. In general, wire–OR should be limitedto 6 MECL outputs to maintain a proper LOW logic level.The MC10123 is an exception to this rule because it has aspecial VOL level that allows very high fanout on a bus orwire–OR line. The use of a single output pull–down resistoris recommended per wire–OR, to economize on powerhttp://onsemi.com37

dissipation. However, two pull–down resistors perwired–OR can improve fall times and be used for doubletermination of busses.Wire–OR should be done between gates in a package ornearby packages to avoid spikes due to line propagationdelay. This does not apply to bus lines which activate onlyone driver at a time.ABCDEFGFigure 39 – USE OF WIRE–OR ANDCOMPLEMENTARY OUTPUTSRPRPAB + C DC + D + E + F + GA + B + E + F + GMC10105RPSYSTEM CONSIDERATIONS – A SUMMARY OF RECOMMENDATIONSMECL 10HMECL 10KPower Supply Regulation ±5% (1) 10% (2)On–Card Temperature Gradient 20°C Less Than 25°CMaximum Non–Transmission Line Length1″ 8″(No Damping Resistor)Unused Inputs Leave Open (3) Leave Open (3)PC Board Multilayer Standard 2–Sided orMultilayerCooling Requirements 500 lfpm Air 500 lfpm AirBus Connection Capability Yes (Wire–OR) Yes (Wire–OR)Maximum Twisted Pair Length(Differential Drive)The Ground Plane to Occupy PercentArea of CardLimited By CableResponse Only,Usually>1000′Limited by CableResponse Only,Usually>1000′>75% >50%Wire Wrap may be used Not Recommended YesCompatible with MECL 10,000 Yes –(1) All dc and ac parameters guaranteed for V EE = –5.2 V ± 5%.(2) At the devices (functional only).(3) Except special functions without input pull–down resistors.http://onsemi.com38

APPLICATIONS ASSISTANCE FORMIn the event that you have any questions or concerns about the performance of any ON Semiconductor device listed in thiscatalog, please contact your local ON Semiconductor sales office or the ON Semiconductor Help line for assistance. If furtherinformation is required, you can request direct factory assistance.Please fill out as much of the form as is possible if you are contacting ON Semiconductor for assistance or are sending devicesback to ON Semiconductor for analysis. Your information can greatly improve the accuracy of analysis and can dramaticallyimprove the correlation response and resolution time.Items 4 thru 8 of the following form contain important questions that can be invaluable in analyzing application or deviceproblems. It can be used as a self–help diagnostic guideline or for a baseline of information gathering to begin a dialog with ONSemiconductor representatives.ON Semiconductor Device Correlation/Component Analysis Request Form–Please fill out entire form and return with devices to ON Semiconductor, R&QA DEPT., 5005 E. McDowell Rd., Phx, AZ 85008.1) Name of Person Requesting Correlation:Phone No: Job Title: Company:2) Alternate Contact: Phone/Position:3) Device Type (user part number):4) Industry Generic Device Type:5) # of devices tested/sampled:# of devices in question*:# returned for correlation:* In the event of 100% failure, does Customer have other date codes of ON Semiconductor devices that pass inspection?Yes No Please specify passing date code(s) if applicableIf none, does customer have viable alternate vendor(s) for device type?Yes No Alternate vendor’s name6) Date code(s) and Serial Number(s) of devices returned for correlation – If possible, please provide one or two “good” units(ON Semiconductor’s and/or other vendor) for comparison:7) Describe USER process that device(s) are questionable in:Incoming component inspection {test system = ?}:Design prototyping:Board test/burn–in:Other (please describe):8) Please describe the device correlation operating parameters as completely as possible for device(s) in question:> Describe all pin conditions (e.g. floating, high, low, under test, stimulated but not under test, whatever ...), including any inputor output loading conditions (resistors, caps, clamps, driving devices or devices being driven ...). Potentially criticalinformation includes:Input waveform timing relationshipsInput edge ratesInput Overshoot or Undershoot – Magnitude and DurationOutput Overshoot or Undershoot – Magnitude and Duration> Photographs, plots or sketches of relevant inputs and outputs with voltages and time divisions clearly identified for allwaveforms are greatly desirable.> VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applications and testsystems. Dynamic characteristics of Ground and VCC during device switching can dramatically effect input and internaloperating levels. Ground & VCC measurements should be made as physically close to the device in question as possible.> Are there specific circumstances that seem to make the questionable unit(s) worse? Better?TemperatureVCCInput rise/fall timeOutput loading (current/capacitance)Others> ATE functional data should include pattern with decoding key and critical parameters such as VCC, input voltages, Func steprate, voltage expected, time to measure.http://onsemi.com39

CHAPTER 2MECL 10H Data SheetsMECL 10H Selector Guide . . . . . . . . . . . . . . . . . . . 41MECL 10H Introduction . . . . . . . . . . . . . . . . . . . . . . 42MECL 10H Data Sheets . . . . . . . . . . . . . . . . . . . . . . 45http://onsemi.com40

MECL 10HINTEGRATED CIRCUITSMC10H100 SERIES0 TO 75°CFunction Selection – (0 to +75°C)Function Device CaseFunction Device CaseNOR GateQuad 2–Input with Strobe MC10H100 620, 648, 775Quad 2–Input MC10H102 620, 648, 775Triple 4–3–3 Input MC10H106 620, 648, 775Dual 3–Input 3–Output MC10H211 620, 648, 775OR GateQuad 2–Input MC10H103 620, 648, 775Dual 3–Input 3–Output MC10H210 620, 648, 775AND GatesQuad AND MC10H104 620, 648, 775Complex GatesQuad OR/NOR MC10H101 620, 648, 775Triple 2–3–2 Input OR/NOR MC10H105 620, 648, 775Triple Exclusive OR/NOR MC10H107 620, 648, 775Dual 4–5 Input OR/NOR MC10H109 620, 648, 775Quad Exclusive OR MC10H113 620, 648, 775Dual 2–Wide OR–AND/OR–ANDMC10H117 620, 648, 775INVERT4–Wide OR–AND/OR–AND INVERT MC10H121 620, 648, 775Hex Buffer w/Enable MC10H188 620, 648, 775Hex Inverter w/Enable MC10H189 620, 648, 775TranslatorsQuad TTL to MECL MC10H124 620, 648, 775Quad MECL to TTL MC10H125 620, 648, 775Quad MECL–to–TTL Translator, SinglePower Supply (–5.2 V or +5.0 V) MC10H350 620, 648, 775Quad TTL/NMOS to MECL Translator MC10H351 732, 738, 775Quad CMOS to MECL Translator MC10H352 732, 738, 775Quad TTL to MECL, ECL Strobe MC10H424 620, 648, 7759–Bit TTL–ECL Translator MC10H/100H600 7769–Bit ECL–TTL Translator MC10H/100H601 7769–Bit Latch/TTL–ECL Translator MC10H/100H602 7769–Bit Latch/ECL–TTL Translator MC10H/100H603 776Registered Hex TTL–ECL Translator MC10H/100H604 776Registered Hex ECL–TTL Translator MC10H/100H605 776Registered Hex TTL–PECL Translator MC10H/100H606 776Registered Hex PECL–TTL Translator MC10H/100H607 776ReceiversQuad Line Receiver MC10H115 620, 648, 775Triple Line Receiver MC10H116 620, 648, 751B,775Flip–Flop LatchesDual D Latch MC10H130 620, 648, 775Dual D Master Slave Flip–Flop MC10H131 620, 648, 775Dual J–K Master Slave Flip–Flop MC10H135 620, 648, 775Hex D Flip–Flop MC10H176 620, 648, 775Quint Latch MC10H175 620, 648, 775Hex D Flip–Flop w/Common Reset MC10H186 620, 648, 775Transceivers4–Bit Differential ECL Bus to TTL BusTransceiver MC10/10H680 776Hex ECL–TTL Transceiver w/Latches MC10/10H681 776Data Selector MultiplexerQuad Bus Driver/Receiver with 2–to–1Output Multiplexers MC10H330 758, 724, 776Quad 2–Input Multiplexers(Noninverting) MC10H158 620, 648, 775Quad 2–Input Multiplexers (Inverting) MC10H159 620, 648, 7758–Line Multiplexer MC10H164 620, 648, 775Quad 2–Input Multiplexer Latch MC10H173 620, 648, 775Dual 4–1 Multiplexer MC10H174 620, 648, 775CountersUniversal Hexadecimal MC10H136 620, 648, 775Binary Counter MC10H016 620, 648, 775Arithmetic FunctionsLook Ahead Carry Block MC10H179 620, 648, 775Dual High Speed Adder/Subtractor MC10H180 620, 648, 7754–Bit ALU MC10H181 724, 758, 776Special Function4–Bit Universal Shift Register MC10H141 620, 648, 7755–Bit Magnitude Comparator MC10H166 620, 648, 775Quad Bus Driver/Receiver withTransmit and Receiver Latches MC10H334 732, 738, 775Bus Driver (25 ohm outputs)Triple 4–3–3 Input Bus Driver(25 Ohms) MC10H123 620, 648, 775Quad Bus Driver/Receiver with 2–to–1Output Multiplexers MC10H330 724, 758, 776Dual Bus Driver/Receiver with 4–to–1Output Multiplexers MC10H332 732, 738, 775Quad Bus Driver/Receiver withTransmit and Receiver Latches MC10H334 732, 738, 775OR/NOR GateDual 4–5 Input OR/NOR Gate MC10H209 620, 648, 775Clock Drivers68030/40 ECL–TTL Clock Driver MC10/100H640 776Single Supply PECL–ECL 1:9 Clock776DistributionMC10/100H64168030/40 ECL–TTL Clock Driver MC10/100H642 776Dual Supply ECT–TTL 1:8 Clock Driver MC10/100H643 77668030/40 PECL–TTL Clock Driver MC10/100H644 7751:9 TTL Clock Driver MC10H645 776PCL–TTL–TTL 1:8 Clock DistributionChip MC10/100H646 776Encoders DecodersBinary to 1–8 (Low) MC10H161 620, 648, 775Binary to 1–8 (High) MC10H162 620, 648, 775Dual Binary to 1–4 (Low) MC10H171 620, 648, 775Dual Binary to 1–4 (High) MC10H172 620, 648, 7758–Input Priority Encoder MC10H165 620, 648, 775Parity Checker12–Bit Parity Generator/Checker MC10H160 620, 648, 775http://onsemi.com41

MECL 10H INTRODUCTIONON Semiconductor’s MECL 10H family features 100%improvement in propagation delay and clock speeds whilemaintaining power supply current equal to MECL 10K. ThisMECL family is voltage compensated which allowsguaranteed dc and switching parameters over a ±5% powersupply range. Noise margins of MECL 10H are 75% betterthan the MECL 10K series over the ±5% power supplyrange. MECL 10H is compatible with MECL 10K andMECL III, a key element in allowing users to enhanceexisting systems by increasing the speed in critical timingareas. Also, many MECL 10H devices are pinout/functionalduplications of the MECL 10K series devices.FIGURE 1 – MECL 10K versus MECL 10H GATEDESIGNThe MECL 10H family is being fabricated usingMotorola’s MOSAIC I (Motorola Oxide Self AssignedImplanted Circuits). The switching transistor’s geometriesobtained in the MOSAIC I process show a two–foldimprovement in fτ, a reduction of more than 50% in parasiticcapacitance and a decrease in device area of almost 76%.FIGURE 2 – MOSAIC versus MECL 10K SWITCHINGTRANSISTOR GEOMETRYWith improved geometry, the MECL10H switchingtransistors (left) are one–seventh the size of the olderMECL 10K transistors (right). Along with the smallerarea comes an improved fT and reduced parasiticcapacitances.MECL 10HMECL 10K16µ2 MILS( 51 )37 4.0 MA4.0 MAVCSVBBThe schematics in Figure 1 compare the basic gatestructure of the MECL 10H to that of MECL 10K devices.The gate switch current is established with a current sourcein the MECL 10H family as compared to a resistor source inMECL 10K. The bias generator in the MECL 10K devicehas been replaced with a voltage regulator in the MECL 10Hseries. The advantages of these design changes are:current–sources permit–matched collector resistors thatyield correspondingly better matched delays, less variationin the output–voltage level with power supply changes, andmatched output– tracking rates with temperature. Thesecircuit changes increase complexity at the gate level;however, the added performance more than compensates.R1EMITTER 3 x 8 DEVICE AREA = 592 2f T = 3.5 GHzC CB = 0.16 pFC EB = 0.07 pFC CS = 0.18 pF3.35 (85 )EMITTER 0.15 x 0.8 MILS(4 x 20 µ)DEVICE AREA = 6.7 MIL 2(4323 2 )f T = 1.6 GHzC CB = 0.46 pFC EB = 0.18 pFC CS = 0.83 pFFigure 2 illustrates the relative size difference between thejunction isolated transistor of MECL 10K and the MOSAICI transistor of MECL 10H. This suggests that performancecould be improved twofold at lower power levels. However,at the gate level, the power of the output transistor cannot bereduced without sacrificing output characteristics becauseof the 50 ohm drive requirements of MECL. In morecomplex functions, where part of the delay is associated withinternal gates, MECL 10H devices use less power than theequivalent MECL 10K devices and provide an even moresignificant improvement in ac performance.Table 1. – TYPICAL FAMILY CHARACTERISTICS FOR10K AND 10H CIRCUITS10K 10HPropagation delay (ns) 2.0 1.0Power (mW) 25 25Power–speed product (pJ) 50 25Rise/fall times (ns) (20–80%) 2.0 1.0Temperature range (°C) –30 to +85 0 to +75Voltage regulated No YesTechnologyJunctionisolatedOxideisolatedVEE = –5.2 Vhttp://onsemi.com42

Supply & Temperature VariationMECL 10H temperature and voltage compensation isdesigned to guarantee compatibility with MECL 10K,MECL III, MECL Memories and the MC10900 andMacrocell Array products. Table 1 summarizes someperformance characteristics of the MECL 10K and 10Hlogic families in a 16–pin DIP. The MECL 10H devices offertypical propagation delays of 1.0 ns at 25 mW per gate whenoperated from a VEE of –5.2 V. The resulting speed–powerproduct of 25 picojoules is one of the best of any ECL logicfamily available today.The operating temperature range is changed from –30°Cto +85°C of the MECL 10K family to the narrower range of0°C to 75°C for MECL 10H. This change matches theconstraints established by the memory and array products.Operation at –30°C would require compromises inperformance and power. With few exceptions, commercialapplications are satisfied by 0°C min.ParameterTable 2. – MECL 10H AC SPECIFICATIONSAND TRACKING0°CMin Typ Max25°CMin Typ Max75°CMin Typ MaxUnitst PD 0.4 1.0 1.5 0.4 1.0 1.6 0.4 1.0 1.7 nsMin Max Min Max Min Maxt R (20–80%) 0.5 1.5 0.5 1.6 0.5 1.7 nst F (20–80%) 0.5 1.5 0.5 1.6 0.5 1.7 nsV EE = –5.2 V ±5%Propagationdelay (ns)*Delay variationvs temp (ps/°C)Delay variationvs supply (ps/V)ParameterTyp Max Typ Max Typ Max10K 2.0 2.9 2.0 7.0 80t PD 10H 1.0 1.5 0.5 4.0 0 0*V EE = –5.2 V, Temp = 25°CAC specifications of MECL 10H products appear in Table2. In the MECL 10H family, all ac specifications haveguaranteed minimums and maximums for extremes of bothtemperature and supply – a first in ECL logic. In addition,flip flops, latches and counters will have guaranteed limitsfor setup time, hold time, and clock pulse width. The limitsin Table 2 are guaranteed for a power supply variation of±5%. MECL 10K typically has a propagation delay (tPD)variation of 80 ps/V with no guaranteed maximum. Thetypical variation in tPD for MECL 10H circuits is only 38 pstypically over the entire specified temperature range andpower–supply tolerance, and is guaranteed not to exceed300 ps.The improved performance in temperature over MECL10K are a result of the internal voltage regulator. Theprimary difference being the flatter tracking rate of theoutput “0” level voltage (VOL). This difference does notaffect the compatibility with existing MECL families.Changes in output “1” level voltages (VOH) with supplyvariations are 10 mV/V less for the MECL 10H family. VOHvaries with the supply, primarily because of changes in chiptemperature caused by the changes in power dissipation.However, the current in the MECL 10H circuits remainsalmost constant with supply changes, since the circuits arevoltage compensated and use current sources for all internalemitter followers. Threshold voltage (VBB) and output “0”levelTable 3. – LOGIC LEVEL DC TRACKING RATE FOR10K AND 10H CIRCUITSMin Typ Max∆VOH/∆T 10H 1.2 1.3 1.5(mV/°C) 10K 1.2 1.3 1.5∆VBB/∆T 10H 0.8 1.0 1.2(mV/°C) 10K 0.8 1.0 1.2∆VOL/∆T 10H 0 0.4 0.6(mV/°C) 10K 0.35 0.5 0.750.75 1.0 1.55∆VOH/∆VEE 10H –20 0(mV/V) 10K –30 0∆VBB/∆VEE 10H 0 10 25(mV/V) 10K 110 150 190∆VOL/∆VEE 10H 0 20 50(mV/V) 10K 200 250 320voltage (VOL) variations are shown with respect to MECL10K in Table 3. In both cases voltage compensation hasreduced the variations significantly.Noise Margin ConsiderationsSpecification of input voltage levels (VIHA, VILA) arechanged from those of MECL 10K resulting in improvednoise margins for MECL 10H.The MECL 10K circuits have two sets of output voltagespecifications (VOH, VOHA, and VOL, VOLA). The firstoutput voltage specification in each set (VOH and VOL) areguaranteed maximum and minimum output levels fortypical input levels. The second specification in each set(VOHA and VOLA) is the guaranteed worst–case output levelfor input threshold voltages. System analysis for worst–casenoise margin considers VOHA and VOLA only. The MECL10H family has only one set of output voltages (VOH andVOL) with minimum and maximum values specified. Theminimum value of VOH and the maximum value for VOL ofthe MECL 10H family is synonymous with the VOHA andVOLA specifications of MECL 10K family.The VOH values for the MECL 10H circuits are equal toor better than the MECL 10K levels at all temperatures.Input threshold voltages (VIHA and VILA, which aresynonymous with VIH min and VIL max for 10H) are alsoimproved and guaranteed VIHA has been decreased by 25mV over the entire operating temperature range, resulting ina “1” level noise margin of 150 mV (compared to 125 mVfor MECL 10K circuits). VILA has been decreased by 5.0mV, providing a “0” level noise margin equal to the “1” levelnoise margin. The VOL minimum of the MECL 10H is morehttp://onsemi.com43

negative than for MECL 10K (–1950 mV instead of –1850mV). The VOL level for the MECL 10K family was selectedto ensure that the gate would not saturate at hightemperatures and high supply voltages. The reduction inoperating temperature range for the MECL 10H family andthe improvement in tracking rate allow the lower VOL level.The change in this level does not affect system noisemargins. Although some of the interface levels change withtemperature, the changes in voltage levels are well withinthe tolerance ranges that would keep the familiescompatible. Table 4 lists some noise margins for VEE supplyvariations.Table 4. – NOISE MARGIN versusPOWER–SUPPLY CONDITIONSV EE–10%V EEV EE–5% V EE +5%Parameter Typ Min Typ Min Typ Min Typ MinNoise Margin 10H 224 150 227 150 230 150 233 150HighV NH (mV) 10K 127 47 166 86 205 125 241 164Noise Margin 10H 264 150 267 150 270 150 273 150LowV NL (mV) 10K 223 103 249 129 275 155 301 181*Temp = 0 to 75°CThe compatibility of MECL 10H with MECL 10K may bedemonstrated by applying the tracking rates in Table 3 to thedc specifications. The method for determining compatibilityis to show acceptable noise margins for MECL 10H, MECL10K and mixed MECL 10K/MECL 10H systems. Theassumption is that the families are compatible if the noisemargin for a mixed system is equal to or better than the samesystem using only the MECL 10K series.Using an all MECL 10K system as a reference, threepossible logic mixes must be considered: MECL 10Kdriving MECL 10H; MECL 10H driving MECL 10K; andMECL 10H driving MECL 10H. The system noise marginfor the three configurations can now be calculated for thefollowing cases (See Figure 3):In Case 1, the system uses multiple power supplies, eachindependently voltage regulated to some percentagetolerance. Worst–case is where one device is at the plusextreme and the other device is at the minus extreme of thesupply tolerance.In Case 2, a system operates on a single supply or severalsupplies slaved to a master supply. The entire system candrift, but all devices are at the same supply voltage.In Case 3, a system has excessive supply dropsthroughout. Supply gradients are due to resistive drops inVEE bus.The analysis indicates that the noise margins for a MECL10K/10H system equal or exceed the margins for an all 10Ksystem for supply tolerance up to ±5%. The results of theanalysis are shown in Figure 3.FIGURE 3 – NOISE MARGIN versus POWER–SUPPLY VARIATIONCase 1 Case 2 Case 3WORST CASEV NH OR V NL — MV1501301109070503010A & CBAC±5% ±7.5%D±10%WORST CASEV NH OR V NL — MV1501301109070503010> 5%A & CBDWORST CASEV NH OR V NL — MV1501301109070503010A & CB5%BADC0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0ABSOLUTE VALUE OF V EE GRADIENT ⎯ V0 –2 –4 –6 –8 –10V EE REGULATION RELATIVE TO –5.2 V ⎯ %0 –2 –4 –6 –8 –10V EE GRADIENT RELATIVE TO –5.2 V – %A = MECL 10K DRIVING MECL 10KB = MECL 10K DRIVING MECL 10HC = MECL 10H DRIVING MECL 10KD = MECL 10H DRIVING MECL 10Hhttp://onsemi.com44

The MC10H016 is a high–speed synchronous, presettable,cascadable 4–bit binary counter. It is useful for a large number ofconversion, counting and digital integration applications.• Counting Frequency, 200 MHz Minimum• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible• Positive Edge TriggeredVCC1Q1Q0TCPECEPOVEEDIPPIN ASSIGNMENT12345678161514131211109VCC2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.Q2Q3CPMRP3P2P1http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H016LAWLYYWWMC10H016PAWLYYWW110H016AWLYYWWORDERING INFORMATIONDevice Package ShippingTRUTH TABLECE PE MR CP FunctionLHLHXXLLHHXXLLLLLHZZZZZZXLoad Parallel (P n to Q n )Load Parallel (P n to Q n )CountHoldMasters Respond;Slaves HoldReset (Q n = LOW,T C = HIGH)MC10H016L CDIP–16 25 Units/RailMC10H016P PDIP–16 25 Units/RailMC10H016FN PLCC–20 46 Units/RailZ = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low)Features include assertion inputs and outputs on eachof the four master/slave counting flip–flops. Terminalcount is generated internally in a manner that allowssynchronous loading at nearly the speed of the basiccounter.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 745 Publication Order Number:MC10H016/D

MC10H016MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– Ceramic–55 to +150–55 to +165ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 126 – 115 – 126 mAIinH Input Current HighAll Except MRPin 12 MR––4501190––265700––265700µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdtsettholdPropagation DelaySet–up TimeHold TimeClock to QClock to TCMR to QPn to ClockCE or PE to ClockClock to PnClock to CE or PE1.00.70.72.02.51.00.5fcount Counting Frequency 200 – 200 – 200 – MHztr Rise Time 0.5 2.0 0.5 2.1 0.5 2.2 nstf Fall Time 0.5 2.0 0.5 2.1 0.5 2.2 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.42.42.4––––1.00.70.72.02.51.00.52.52.52.5––––1.00.70.72.02.51.00.52.72.62.6––––°Cnsnsnshttp://onsemi.com46

4–Bit Binary Counter Logic DiagramPEQ0 Q1 Q2 Q3P0MASTERQSLAVEMASTER Q SLAVEMASTER Q SLAVEP1 P2 P3QQQMRQQQQCECPTChttp://onsemi.com471/2 10H109Note that this diagram is provided for understanding of logic operation only. It should not be used for evaluation ofpropagation delays as many gate functions are achieved internally without incurring a full gate delay.MC10H016Q0–Q3Q0–Q3Q0–Q3Q0–Q3Q0–Q3FOCEMRLSBPECEMRPECEMRPECEMRPECEMRMSBPECTcCTcCTcCTcCTcP0–P3P0–P3P0–P3P0–P3P0–P31/2 10H1091/2 10H1091/2 10H109CLOCK÷N Counter 1 to 16 5MC10H016 Cascaded for 5 Stage Presettable CounterMax freq. is only OR gate delay below max when counting alone.

The MC10H100 is a quad NOR gate. Each gate has 3 inputs, two ofwhich are independent and one of which is tied common to all fourgates.• Propagation Delay, 1.0 ns Typical• 25 mW Typ/Gate (No Load)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible45679101112132 = 4 + 5 + 9LOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT231415http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H100LAWLYYWWMC10H100PAWLYYWW110H100AWLYYWWVCC1116VCC2ORDERING INFORMATIONAOUT215DOUTDevice Package ShippingBOUT314COUTMC10H100L CDIP–16 25 Units/RailAIN413DINMC10H100P PDIP–16 25 Units/RailAIN512DINMC10H100FN PLCC–20 46 Units/RailBIN611CINBINVEE78109CINCOMMONINPUT(A, B, C, D)Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 648 Publication Order Number:MC10H100/D

MC10H100MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic–55 to +150 °C– Ceramic–55 to +165ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 29 – 26 – 29 mAIinH Input Current HighPin 9All Other Inputs––900500––560310––560310µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayPin 9 OnlyExclude Pin 90.650.4tr Rise Time 0.5 2.0 0.5 2.1 0.5 2.2 nstf Fall Time 0.5 2.0 0.5 2.1 0.5 2.2 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.61.30.70.451.71.350.70.51.81.5nshttp://onsemi.com49

The MC10H101 is a quad 2–input OR/NOR gate with one inputfrom each gate common to pin 12. This MECL 10H part is afunctional/pinout duplication of the standard MECL 10K family part,with 100% improvement in propagation delay, and no increases inpower–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 25 mW/Gate (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H101LAWLYYWW425736101411131512 9PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H101PAWLYYWW110H101AWLYYWWVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONVCC1AOUT121615VCC2DOUTDevice Package ShippingMC10H101L CDIP–16 25 Units/RailBOUT314COUTMC10H101P PDIP–16 25 Units/RailAINAOUT451312DINCOMMONINPUTMC10H101FN PLCC–20 46 Units/RailBOUT611COUTBIN710CINVEE89DOUTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 650 Publication Order Number:MC10H101/D

MC10H101MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 29 – 26 – 29 mAIinH Input Current High– 425 – 265 – 265 µA(Pin 12 only)– 850 – 535 – 535IinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayPin 12 OnlyExclude Pin 120.50.5tr Rise Time 0.5 2.1 0.5 2.2 0.5 2.3 nstf Fall Time 0.5 2.1 0.5 2.2 0.5 2.3 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.61.450.50.51.61.50.50.51.71.6°C°Cnshttp://onsemi.com51

The MC10H102 is a quad 2–input NOR gate. The MC10H102provides one gate with OR/NOR outputs. This MECL 10H part is afunctional/pinout duplication of the standard MECL 10K family part,with 100% improvement in propagation delay, and no increases inpower– supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 25 mW/Gate (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H102LAWLYYWW4567101112132314159PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H102PAWLYYWW110H102AWLYYWWVCC1AOUTBOUTAINAINVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT123451615141312VCC2DOUTCOUTDINDINA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H102L CDIP–16 25 Units/RailMC10H102P PDIP–16 25 Units/RailMC10H102FN PLCC–20 46 Units/RailBIN611CINBIN710CINVEE89DOUTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 652 Publication Order Number:MC10H102/D

MC10H102MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 29 – 26 – 29 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.4 1.25 0.4 1.25 0.4 1.4 nstr Rise Time 0.5 1.5 0.5 1.6 0.55 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.55 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com53

The MC10H103 is a quad 2–input OR gate. The MC10H103provides one gate with OR/NOR outputs. This MECL 10H part is afunctional/pinout duplication of the standard MECL 10K family part,with 100% improvement in propagation delay, and no increases inpower– supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 25 mW/Gate (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible456712131011LOGIC DIAGRAM2315914http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H103LAWLYYWWMC10H103PAWLYYWW110H103AWLYYWWVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONVCC1AOUT121615VCC2COUTDevice Package ShippingMC10H103L CDIP–16 25 Units/RailBOUT314DOUTMC10H103P PDIP–16 25 Units/RailAIN413CINMC10H103FN PLCC–20 46 Units/RailAIN512CINBIN611DINBIN710DINVEE89COUTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 654 Publication Order Number:MC10H103/D

MC10H103MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 29 – 26 – 29 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.4 1.3 0.4 1.3 0.45 1.45 nstr Rise Time 0.5 1.7 0.5 1.8 0.5 1.9 nstf Fall Time 0.5 1.7 0.5 1.8 0.5 1.9 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com55

The MC10H104 is a quad 2–input AND gate. One of the gates hasboth AND/NAND outputs available. This MECL 10H part is afunctional/pinout duplication of the standard MECL 10K family part,with 100% improvement in propagation delay, and no increase inpower– supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 25 mW/Gate (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible456710111213LOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT2314915http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATION116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H104LAWLYYWWMC10H104PAWLYYWW110H104AWLYYWWVCC1116VCC2Device Package ShippingAOUT215DOUTMC10H104L CDIP–16 25 Units/RailBOUT314COUTMC10H104P PDIP–16 25 Units/RailAIN413DINMC10H104FN PLCC–20 46 Units/RailAIN512DINBIN611CINBIN710CINVEE89DOUTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 756 Publication Order Number:MC10H104/D

MC10H104MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 39 – 35 – 39 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.4 1.6 0.45 1.75 0.45 1.9 nstr Rise Time 0.5 1.6 0.5 1.7 0.5 1.8 nstf Fall Time 0.5 1.6 0.5 1.7 0.5 1.8 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com57

The MC10H105 is a triple 2–3–2–input OR/NOR gate. This MECL10H part is a functional/pinout duplication of the standard MECL 10Kfamily part, with 100% improvement in propagation delay, and noincreases in power–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 25 mW/Gate (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAM4 35 29101113 1412 1567http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H105LAWLYYWWMC10H105PAWLYYWW110H105AWLYYWWVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingVCC1AOUTAOUTAIN123416151413VCC2COUTCOUTCINMC10H105L CDIP–16 25 Units/RailMC10H105P PDIP–16 25 Units/RailMC10H105FN PLCC–20 46 Units/RailAIN512CINBOUT611BINBOUT710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 658 Publication Order Number:MC10H105/D

MC10H105MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 23 – 21 – 23 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.43 1.2 0.4 1.2 0.4 1.3 nstr Rise Time 0.5 1.5 0.5 1.6 0.5 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.5 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com59

The MC10H106 is a triple 4–3–3 input NOR gate. This 10H part is afunctional/pinout duplication of the standard MECL 10K family part,with 100% improvement in propagation delay and no increase inpower– supply current.• Propagation Delay, 1.0 ns Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H106LAWLYYWW45367910 2111213 1514PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H106PAWLYYWW110H106AWLYYWWVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONVCC1BOUT121615VCC2COUTDevice Package ShippingMC10H106L CDIP–16 25 Units/RailAOUT314CINMC10H106P PDIP–16 25 Units/RailAIN413CINMC10H106FN PLCC–20 46 Units/RailAIN512CINAIN611BINAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 760 Publication Order Number:MC10H106/D

MC10H106MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 23 – 21 – 23 mAIinH Input Current High – 500 – 310 – 310 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.5 1.3 0.5 1.5 0.55 1.55 nstr Rise Time 0.5 1.7 0.5 1.8 0.55 1.9 nstf Fall Time 0.5 1.7 0.5 1.8 0.55 1.9 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com61

The MC10H107 is a triple 2–input exclusive OR/NOR gate. ThisMECL 10H part is a functional/pinout duplication of the standardMECL 10K family part, with 100% improvement in propagationdelay, and no increase in power–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 35 mW/Gate Typical (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible4597LOGIC DIAGRAM231110http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10H107LAWLYYWWMC10H107PAWLYYWW1141215 13PLCC–20FN SUFFIXCASE 77510H107AWLYYWWVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONVCC1116VCC2Device Package ShippingAOUT215CINMC10H107L CDIP–16 25 Units/RailAOUT314CINMC10H107P PDIP–16 25 Units/RailAINAIN451312COUTCOUTMC10H107FN PLCC–20 46 Units/Rail*NC611BOUTBIN710BOUTVEE89BIN*NC = No ConnectionPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 662 Publication Order Number:MC10H107/D

MC10H107MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 31 – 28 – 31 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.4 1.5 0.4 1.6 0.4 1.7 nstr Rise Time 0.5 1.5 0.5 1.6 0.5 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.5 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com63

The MC10H109 is a dual 4–5–input OR/NOR gate. This MECL10H part is a functional/pinout duplication of the standard MECL 10Kfamily part, with 100% improvement in propagation delay, and noincrease in power–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 35 mW/Gate Typical (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible4LOGIC DIAGRAM5 3627910111213VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT1415http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATION116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H109LAWLYYWWMC10H109PAWLYYWW110H109AWLYYWWVCC1AOUTAOUTAIN123416151413VCC2BOUTBOUTBINDevice Package ShippingMC10H109L CDIP–16 25 Units/RailMC10H109P PDIP–16 25 Units/RailMC10H109FN PLCC–20 46 Units/RailAIN512BINAIN611BINAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 664 Publication Order Number:MC10H109/D

MC10H109MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 15 – 14 – 15 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.4 1.3 0.4 1.3 0.45 1.45 nstr Rise Time 0.5 2.0 0.5 2.1 0.5 2.2 nstf Fall Time 0.5 2.0 0.5 2.1 0.5 2.2 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com65

The MC10H113 is a Quad Exclusive OR Gate with an enablecommon to all four gates. The outputs may be wire–ORed together toperform a 4–bit comparison function (A = B). The enable is activeLOW.• Propagation Delay, 1.3 ns Typical• Power Dissipation 175 mW Typ/Pkg (No Load)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible456710111213LOGIC DIAGRAME 92 TRUTH TABLEIN E OUTPUTLLLHLLLH3H L L HH H L LX X H L1415VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H113LAWLYYWWMC10H113PAWLYYWW110H113AWLYYWWVCC1AOUTBOUTAINAINBINBINVEEDIPPIN ASSIGNMENT12345678161514131211109VCC2DOUTCOUTDINDINCINCINENABLEORDERING INFORMATIONDevice Package ShippingMC10H113L CDIP–16 25 Units/RailMC10H113P PDIP–16 25 Units/RailMC10H113FN PLCC–20 46 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 766 Publication Order Number:MC10H113/D

MC10H113MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 46 – 42 – 46 mAIinH Input Current HighPins 5, 7, 11, 13Pins 4, 6, 10, 12Pin 9–––4305101100–––270320740–––270320740µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayDataEnable0.40.5tr Rise Time 0.5 1.8 0.6 1.9 0.6 2.0 nstf Fall Time 0.5 1.8 0.6 1.9 0.6 2.0 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.72.30.40.51.82.40.50.61.92.5°C°Cnshttp://onsemi.com67

The MC10H115 is a quad differential amplifier designed for use insensing differential signals over long lines. This 10H part is afunctional/ pinout duplication of the standard MECL 10K family part,with 100% improvement in counting frequency and no increase inpower–supply current.The base bias supply (VBB) is made available at Pin 9 to make thedevice useful as a Schmitt trigger, or in other applications where astable reference voltage is necessary. Active current sources providethe MC10H115 with excellent common mode rejection. If anyamplifier in a package is not used, one input of that amplifier must beconnected to VBB (Pin 9) to prevent upsetting the current source biasnetwork.• Propagation Delay, 1.0 ns Typical• Power Dissipation 110 mW Typ/Pkg (No Load)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible457610111312V BB *V CC1 = Pin 1V CC2 = Pin 16V EE = Pin 82314159When input pin with bubblegoes positive its respectiveoutput pin with bubble goespositive.LOGIC DIAGRAM*V BB to be used to supply bias to the MC10H115 only and bypassed(when used) with 0.01 µF to 0.1 µF capacitor to ground (0 V). V BBcan source < 1.0 mA.The MC10H115 is designed to be used in sensing differentialsignals over long lines. The bias supply (V BB ) is made available tomake the device useful as a Schmitt trigger, or in other applicationswhere a stable reference voltage is necessary.Active current sources provide these receivers with excellentcommon–mode noise rejection. If any amplifier in a package is notused, one input of that amplifier must be connected to V BB toprevent unbalancing the current–source bias network.The MC10H115 does not have internal–input pull– downresistors. This provides high impedance to the amplifier input andfacilitates differential connections.Applications:• Low Level Receiver • Voltage Level• Schmitt TriggerInterfaceDIPPIN ASSIGNMENThttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10H115L CDIP–16 25 Units/RailMC10H115P PDIP–16 25 Units/RailMC10H115FN PLCC–20 46 Units/Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H115LAWLYYWWMC10H115PAWLYYWW110H115AWLYYWWVCC1AOUTBOUTAINAINBINBINVEE12345678161514131211109VCC2DOUTCOUTDINDINCINCINVBBPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 668 Publication Order Number:MC10H115/D

MC10H115MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (Note 2.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 29 – 26 – 29 mAIinH Input Current High – 150 – 95 – 95 µAICBO Input Leakage Current – 1.5 – 1.0 – 1.0 µAVBB Reference Voltage –1.38 –1.27 –1.35 –1.25 –1.31 –1.19 VdcVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage (Note 1.) –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage (Note 1.) –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcVCMR Common ModeRange (Note 3.)– – –2.85 to –0.8 – – VdcVPP Input Sensitivity (Note 4.) – – 150 typ – – mVPPAC PARAMETERStpd Propagation Delay 0.4 1.3 0.4 1.3 0.45 1.45 nstr Rise Time 0.5 1.4 0.5 1.5 0.5 1.6 nstf Fall Time 0.5 1.4 0.5 1.5 0.5 1.6 ns1. When VBB is used as the reference voltage.2. Each MECL 10H series circuit has been designed to meet the specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.3. Differential input not to exceed 1.0 Vdc.4. 150 mVp–p differential input required to obtain full logic swing on output.°C°Chttp://onsemi.com69

The MC10H116 is a functional/pinout duplication of the MC10116,with 100% improvement in propagation delay and no increase inpower–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 85 mW Typ/Pkg (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible459101213V BB *V CC1 = Pin 1V CC2 = Pin 16V EE = Pin 8When input pin withbubble goes positiveit’s respective outputpin with bubble goespositive.2367141511LOGIC DIAGRAM*V BB to be used to supply bias to the MC10H115 only and bypassed(when used) with 0.01 µF to 0.1 µF capacitor to ground (0 V). V BBcan source < 1.0 mA.The MC10H115 is designed to be used in sensing differentialsignals over long lines. The bias supply (V BB ) is made available tomake the device useful as a Schmitt trigger, or in other applicationswhere a stable reference voltage is necessary.Active current sources provide these receivers with excellentcommon–mode noise rejection. If any amplifier in a package is notused, one input of that amplifier must be connected to V BB toprevent unbalancing the current–source bias network.The MC10H115 does not have internal–input pull– downresistors. This provides high impedance to the amplifier input andfacilitates differential connections.Applications:• Low Level Receiver • Voltage Level• Schmitt TriggerInterfaceDIP PIN ASSIGNMENThttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1161MARKINGDIAGRAMSMC10H116LAWLYYWWMC10H116PAWLYYWW110H116AWLYYWWVCC1AOUTAOUTAINAINBOUTBOUTVEE12345678161514131211109VCC2COUTCOUTCINCINVBBBINBINORDERING INFORMATIONDevice Package ShippingMC10H116L CDIP–16 25 Units/RailMC10H116P PDIP–16 25 Units/RailMC10H116FN PLCC–20 46 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 770 Publication Order Number:MC10H116/D

MC10H116MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (Note 2.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 23 – 21 – 23 mAIinH Input Current High – 150 – 95 – 95 µAICBO Input Leakage Current – 1.5 – 1.0 – 1.0 µAVBB Reference Voltage –1.38 –1.27 –1.35 –1.25 –1.31 –1.19 VdcVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage (Note 1.) –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage (Note 1.) –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcVCMR Common ModeRange (Note 4.)– – –2.85 to –0.8 – – VdcVPP Input Sensitivity (Note 3.) – – 150 typ – – mVPPAC PARAMETERStpd Propagation Delay 0.4 1.3 0.4 1.3 0.45 1.45 nstr Rise Time 0.5 1.5 0.5 1.6 0.5 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.5 1.7 ns1. When VBB is used as the reference voltage.2. Each MECL 10H series circuit has been designed to meet the specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.3. Differential input not to exceed 1.0 Vdc.4. 150 mVp–p differential input required to obtain full logic swing on output.°C°Chttp://onsemi.com71

The MC10H117 dual 2–wide 2–3–input OR–AND/OR–AND–Invert gate is a general purpose logic element designed foruse in data control, such as digital multiplexing or data distribution.Pin 9 is common to both gates. This MECL 10H part is afunctional/pinout duplication of the standard MECL 10K family part,with 100% improvement in propagation delay, and no increase inpower–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 100 mW/Gate Typical (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible45679LOGIC DIAGRAM32http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H117LAWLYYWWMC10H117PAWLYYWW110H117AWLYYWW10111213VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 81415A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDIPPIN ASSIGNMENTDevice Package ShippingMC10H117L CDIP–16 25 Units/RailVCC1116VCC2MC10H117P PDIP–16 25 Units/RailAOUT215BOUTMC10H117FN PLCC–20 46 Units/RailAOUT314BOUTA1IN413B1INA1IN512B1INA2IN611B2INA2IN710B2INVEE89A2IN, B2INPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 672 Publication Order Number:MC10H117/D

MC10H117MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current — Continuous50mA— Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range — Plastic— CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current — 29 — 26 — 29 mAIinH Input Current HighPins 4, 5, 12, 13Pins 6, 7, 10, 11Pin 9———465545710———275320415———275320415µAIinL Input Current Low 0.5 — 0.5 — 0.3 — µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.45 1.35 0.45 1.35 0.5 1.5 nstr Rise Time 0.5 1.5 0.5 1.6 0.5 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.5 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com73

The MC10H121 is a basic logic building block providing thesimultaneous OR–AND/OR–AND–Invert function, useful in datacontrol and digital multiplexing applications. This MECL 10H part isa functional/pinout duplication of the standard MECL 10K familypart, with 100% improvement in propagation delay, and no increase inpower– supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation 100 mW/Gate Typical (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible4567910LOGIC DIAGRAM23http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H121LAWLYYWWMC10H121PAWLYYWW110H121AWLYYWW1112131415VCC1AOUTVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT121615VCC2A4INA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H121L CDIP–16 25 Units/RailMC10H121P PDIP–16 25 Units/RailMC10H121FN PLCC–20 46 Units/RailAOUT314A4INA1IN413A4INA1IN512A3INA1IN611A3INA2IN710A2IN, A3INVEE89A2INPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 674 Publication Order Number:MC10H121/D

MC10H121MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current — Continuous50mA— Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range — Plastic— CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current — 29 — 26 — 29 mAIinH Input Current HighPins 3, 4, 5, 6, 7, 911, 12, 13, 14, 15Pin 10——500610——295360——295360µAIinL Input Current Low 0.5 — 0.5 — 0.3 — µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayPin 10 OnlyExclude Pin 100.450.55tr Rise Time 0.5 1.7 0.5 1.8 0.5 1.9 nstf Fall Time 0.5 1.7 0.5 1.8 0.5 1.9 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.81.950.450.61.82.00.550.72.22.4°C°Cnshttp://onsemi.com75

The MC10H123 is a triple 4–3–3–Input Bus Driver.The MC10H123 consists of three NOR gates designed for busdriving applications on card or between cards. Output low logic levelsare specified with VOL = –2.1 Vdc so that the bus may be terminated to–2.0 Vdc. The gate output, when low, appears as a high impedance tothe bus, because the output emitter–followers of the MC10H123 are“turned–off.” This eliminates discontinuities in the characteristicimpedance of the bus.The VOH level is specified when driving a 25–ohm load terminatedto –2.0 Vdc, the equivalent of a 50–ohm bus terminated at both ends.Although 25 ohms is the lowest characteristic impedance that can bedriven by the MC10H123, higher impedance values may be used withthis part. A typical 50–ohm bus is shown in Figure 1.• Propagation Delay, 1.5 ns Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAM456791011121314DIP PIN ASSIGNMENT32VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 815http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10H123L CDIP–16 25 Units/RailMC10H123P PDIP–16 25 Units/Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H123LAWLYYWWMC10H123PAWLYYWW110H123AWLYYWWVCC1116VCC2MC10H123FN PLCC–20 46 Units/RailBOUT215COUTAOUT314CINAIN413CINAIN512CINAIN611BINAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 676 Publication Order Number:MC10H123/D

MC10H123MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current — Continuous50mA— Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range — Plastic— CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current — 60 — 56 — 60 mAIinH Input Current High — 495 — 310 — 310 µAIinL Input Current Low 0.5 — 0.5 — 0.3 — µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –2.1 –2.03 –2.1 –2.03 –2.1 –2.03 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.7 1.5 0.7 1.6 0.7 1.7 nstr Rise Time 0.7 1.6 0.7 1.7 0.7 1.8 nstf Fall Time 0.7 1.6 0.7 1.7 0.7 1.8 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.1 volts.FIGURE 1 — 50–OHM BUS DRIVER (25–OHM LOAD)°C°C1/3 MC10H123 1/3 MC10H123 1/3 MC10H123ZO = 50 Ω50 Ω50 Ω–2.0VDCRECEIVERS (MECL GATES)–2.0VDChttp://onsemi.com77

The MC10H124 is a quad translator for interfacing data and controlsignals between a saturated logic section and the MECL section ofdigital systems. The 10H part is a functional/pinout duplication of thestandard MECL 10K family part, with 100% improvement inpropagation delay, and no increase in power–supply current.• Propagation Delay, 1.5 ns Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAM5 4627 3110 121511 1314GND = PIN 16VCC ( +5.0 VDC)= PIN 9VEE ( –5.2 VDC) = PIN 8http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H124LAWLYYWWMC10H124PAWLYYWW110H124AWLYYWWBOUTAOUTBOUTAOUTDIPPIN ASSIGNMENT123416151413GNDCOUTDOUTDOUTORDERING INFORMATIONDevice Package ShippingMC10H124L CDIP–16 25 Units/RailMC10H124P PDIP–16 25 Units/RailMC10H124FN PLCC–20 46 Units/RailAIN512COUTCOMMONSTROBEBIN671110DINCINVEE89VCCPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 778 Publication Order Number:MC10H124/D

MC10H124MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 5.0 V) –8.0 to 0 VdcVCC Power Supply (VEE = –5.2 V) 0 to +7.0 VdcVI Input Voltage (VCC = 5.0 V) TTL 0 to VCC VdcIout Output Current — Continuous50mA— Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range — Plastic–55 to +150°C— Ceramic–55 to +165ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%, VCC = 5.0 V ± 5.0%)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Negative Power— 72 — 66 — 72 mASupply DrainCurrentICCH Positive Power Supply — 16 — 16 — 18 mAICCLDrain Current— 25 — 25 — 25 mAIR Reverse CurrentµAPin 6— 200 — 200 — 200Pin 7— 50 — 50 — 50IFV(BR)inForward CurrentPin 6Pin 7Input BreakdownVoltage——–12.8–3.2——–12.8–3.2——–12.8–3.25.5 — 5.5 — 5.5 — VdcVI Input Clamp Voltage — –1.5 — –1.5 — –1.5 VdcVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage 2.0 — 2.0 — 2.0 — VdcVIL Low Input Voltage — 0.8 — 0.8 — 0.8 Vdc1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%, VCC = 5.0 V ± 5.0%)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitAC PARAMETERStpd Propagation Delay 0.55 2.25 0.55 2.4 0.85 2.95 nstr Rise Time 0.5 1.5 0.5 1.6 0.5 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.5 1.7 nsAPPLICATIONS INFORMATIONmAThe MC10H124 has TTL–compatible inputs and MECLcomplementary open–emitter outputs that allow use as aninverting/non–inverting translator or as a differential linedriver. When the common strobe input is at the low–logiclevel, it forces all true outputs to a MECL low–logic stateand all inverting outputs to a MECL high–logic state.An advantage of this device is that TTL–level informationcan be transmitted differentially, via balanced twisted pairlines, to MECL equipment, where the signal can be receivedby the MC10H115 or MC10H116 differential line receivers.The power supply requirements are ground, +5.0 volts, and–5.2 volts.http://onsemi.com79

The MC10H125 is a quad translator for interfacing data and controlsignals between the MECL section and saturated logic section ofdigital systems. The 10H part is a functional/pinout duplication of thestandard MECL 10K family part, with 100% improvement inpropagation delay, and no increase in power–supply current.Outputs of unused translators will go to low state when their inputsare left open.• Propagation Delay, 2.5 ns Typical• Voltage Compensated• Improved Noise Margin 150 mV(Over Operating Voltage and Temperature Range)• MECL 10K–Compatible236710111415LOGIC DIAGRAMVBB*GND = PIN 16VCC ( +5.0 VDC)= PIN 9VEE ( –5.2 VDC) = PIN 8DIP PIN ASSIGNMENT4512131*V BB to be used to supply bias to the MC10H125only and bypassed (when used) with 0.01 µF to0.1 µF capacitor to ground (0 V). V BB can source < 1.0 mA.http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10H125L CDIP–16 25 Units/Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H125LAWLYYWWMC10H125PAWLYYWW110H125AWLYYWWVBB116GNDMC10H125P PDIP–16 25 Units/RailAIN215DINMC10H125FN PLCC–20 46 Units/RailAIN314DINAOUT413DOUTBOUT512COUTBIN611CINBIN710CINVEE89VCCPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 780 Publication Order Number:MC10H125/D

MC10H125MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 5.0 V) –8.0 to 0 VdcVCC Power Supply (VEE = –5.2 V) 0 to +7.0 VdcVI Input Voltage (VCC = 5.0 V) 0 to VEE VdcTA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range — Plastic— CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%; VCC = 5.0 V ± 5.0 %) (See Note)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Negative Power— 44 — 40 — 44 mASupply DrainCurrentICCH Positive Power Supply — 63 — 63 — 63 mAICCLDrain Current — 40 — 40 — 40 mAIinH Input Current — 225 — 145 — 145 µAICBO Input Leakage Current — 1.5 — 1.0 — 1.0 µAVOHVOLHigh Output VoltageIOH = –1.0 mALow Output VoltageIOL = +20 mA2.5 — 2.5 — 2.5 — Vdc°C°C— 0.5 — 0.5 — 0.5 VdcVIH High Input Voltage(1) –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage(1) –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcIOS Short Circuit Current 60 150 60 150 50 150 mAVBB Reference Voltage –1.38 –1.27 –1.35 –1.25 –1.31 –1.19 VdcVCMR Common Mode— — –2.85 to +0.3 VRange (3)TypicalVPP Input Sensitivity (4) 150 mVAC PARAMETERStpd Propagation Delay 0.8 3.3 0.85 3.35 0.9 3.4 nstr Rise Time(5) 0.3 1.2 0.3 1.2 0.3 1.2 nstf Fall Time(5) 0.3 1.2 0.3 1.2 0.3 1.2 ns1. When VBB is used as the reference voltage.2. Each MECL 10H series circuit has been designed to meet the specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained.3. Differential input not to exceed 1.0 Vdc.4. 150 mVp–p differential input required to obtain full logic swing on output.5. 1.0 V to 2.0 V w/25 pF into 500 .APPLICATION INFORMATIONThe MC10H125 incorporates differential inputs andSchottky TTL “totem pole” outputs. Differential inputsallow for use as an inverting/non–inverting translator or asa differential line receiver. The VBB reference voltage isavailable on Pin 1 for use in single–ended input biasing. Theoutputs of the MC10H125 go to a low–logic level wheneverthe inputs are left floating, and a high–logic output level isachieved with a minimum input level of 150 mVp–p.An advantage of this device is that MECL–levelinformation can be received, via balanced twisted pair lines,in the TTL equipment. This isolates the MECL–logic fromthe noisy TTL environment. Power supply requirements areground, +5.0 volts and –5.2 volts.http://onsemi.com81

The MC10H130 is a MECL 10H part which is a functional/pinoutduplication of the standard MECL 10K family part, with 100%improvement in clock speed and propagation delay and no increase inpower–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation, 155 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleS1 5LOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H130LAWLYYWWD1 7CE1 6R1 4C 9R2 13CE2 11D2 10Q1Q1Q2VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8Q2231415PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H130PAWLYYWW110H130AWLYYWWS2 12TRUTH TABLED C CE Q n+1LHXLLLLLHLHQ nXXHHLHQ nQ nDIP PIN ASSIGNMENTVCC1Q1Q1R1S1CE1D1VEE12345678161514131211109VCC2Q2Q2R2S2CE2D2CA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H130L CDIP–16 25 Units/RailMC10H130P PDIP–16 25 Units/RailMC10H130FN PLCC–20 46 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 682 Publication Order Number:MC10H130/D

MC10H130MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 38 – 35 – 38 mAIinH Input Current HighPins 6, 11Pins 7, 9, 10Pins 4, 5, 12, 13–––468545434–––275320255–––275320255µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayDataSet, ResetClock, CE0.40.60.5tr Rise Time 0.5 1.6 0.5 1.7 0.5 1.8 nstf Fall Time 0.5 1.6 0.5 1.7 0.5 1.8 nstset Set–up Time 2.2 – 2.2 – 2.2 – nsthold Hold Time 0.7 – 0.7 – 0.7 – ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.61.71.60.40.70.5APPLICATION INFORMATION1.71.81.70.40.80.61.81.91.8°C°CnsThe MC10H130 is a clocked dual D type latch. Each latchmay be clocked separately by holding the commonclock in the low state, and using the clock enable inputs forthe clocking function. If the common clock is to be used toclock the latch, the clock enable (CE) inputs must be in thelow state. In this mode, the enable inputs perform thefunction of controlling the common clock (C).Any change at the D input will be reflected at the outputwhile the clock is low. The outputs are latched on thepositive transition of the clock. While the clock is in the highstate, a change in the information present at the data inputswill not affect the output information.The set and reset inputs do not override the clock and Dinputs. They are effective only when either C or CE or bothare high.http://onsemi.com83

The MC10H131 is a MECL 10H part which is a functional/pinoutduplication of the standard MECL 10K family part, with 100%improvement in clock speed and propagation delay and no increase inpower–supply current.• Propagation Delay, 1.0 ns Typical• Power Dissipation, 235 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleS1 5D1 7CE1 6R1 4C C 9R2 13CE2 11D2 10S2 12RS TRUTH TABLELOGIC DIAGRAMQ1Q1Q2Q223VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 81415CLOCKED TRUTH TABLEhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H131LAWLYYWWMC10H131PAWLYYWW110H131AWLYYWWR S Q n+1LLHHLHLHQ nHLN.D.N.D. = Not DefinedC D Q n+1LHHXLHQ nLHC = CE + C CA clock H is a clock transitionfrom a low to a high state.ORDERING INFORMATIONDevice Package ShippingMC10H131L CDIP–16 25 Units/RailVCC1Q1Q1R1S1CE1D1VEEDIPPIN ASSIGNMENT12345678161514131211109VCC2Q2Q2R2S2CE2D2CCMC10H131P PDIP–16 25 Units/RailMC10H131FN PLCC–20 46 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 684 Publication Order Number:MC10H131/D

MC10H131MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 62 – 56 – 62 mAIinH Input Current HighµAPins 6, 11– 530 – 310 – 310Pin 9Pins 7, 10Pins 4, 5, 12, 13–––660485790–––390285465–––390285465IinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayClock, CESet, Reset0.80.6tr Rise Time 0.6 2.0 0.6 2.0 0.6 2.2 nstf Fall Time 0.6 2.0 0.6 2.0 0.6 2.2 nstset Set–up Time 0.7 – 0.7 – 0.7 – nsthold Hold Time 0.8 – 0.8 – 0.8 – nsftog Toggle Frequency 250 – 250 – 250 – MHz1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.61.60.80.7APPLICATION INFORMATION1.71.70.80.71.81.8°C°CnsThe MC10H131 is a dual master–slave type D flip–flop.Asynchronous Set (S) and Reset (R) override Clock (CC)and Clock Enable (CE) inputs. Each flip–flop may beclocked separately by holding the common clock in the newlow state and using the enable inputs for the clockingfunction. If the common clock is to be used to clock theflip–flop, the Clock Enable inputs must be in the low state.In this case, the enable inputs perform the function ofcontrolling the common clock.The output states of the flip–flop change on the positivetransition of the clock. A change in the information presentat the data (D) input will not affect the output information atany other time due to master slave construction.http://onsemi.com85

The MC10H135 is a dual J–K master–slave flip–flop. The device isprovided with an asynchronous set(s) and reset(R). These set and resetinputs overide the clock.A common clock is provided with separate J–K inputs. When theclock is static, the JK inputs do not effect the output. The output statesof the flip flop change on the positive transition of the clock.• Propagation delay, 1.5 ns Typical• Power Dissipation, 280 mW Typical/Pkg. (No Load)• ftog 250 MHz Max• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleS1 5J1 7K1 6R1 4C 9S2 12J2 10K2 11R2 13Q1Q1Q2Q2LOGIC DIAGRAM23VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 81514DIPPIN ASSIGNMENTRS TRUTH TABLER S Q n + 1LLHHLHLHQ nHLN.D.N.D. = Not DefinedCLOCK J–K TRUTH TABLE*J K Q n + 1LHLHLLHHQ nLHQ n*Output states change onpositive transition of clockfor J–K input conditionpresent.http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10H135L CDIP–16 25 Units/Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H135LAWLYYWWMC10H135PAWLYYWW110H135AWLYYWWVCC1Q1121615VCC2Q2MC10H135P PDIP–16 25 Units/RailMC10H135FN PLCC–20 46 Units/RailQ1314Q2R1413R2S1512S2K1611K2J1710J2VEE89CPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 786 Publication Order Number:MC10H135/D

MC10H135MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 75 – 68 – 75 mAIinH Input Current HighPins 6, 7, 10, 11Pins 4, 5, 12, 13Pin 9–––460800675–––285500420–––285500420µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelaySet, Reset, Clock0.7 2.6 0.7 2.6 0.7 2.6 nstr Rise Time 0.7 2.2 0.7 2.2 0.7 2.2 nstf Fall Time 0.7 2.2 0.7 2.2 0.7 2.2 nstset Set–up Time 1.5 – 1.5 – 1.5 – nsthold Hold Time 1.0 – 1.0 – 1.0 – nsftog Toggle Frequency 250 – 250 – 250 – MHz1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com87

The MC10H136 is a high speed synchronous hexadecimal counter.This 10H part is a functional/pinout duplication of the standard MECL10K family part, with 100% improvement in counting frequency andno increase in power-supply current.• Counting Frequency, 250 MHz Minimum• Power Dissipation, 625 mW Typical• Improved Noise Margin 150 mV(Over Operating Voltage and Temperature Range)• Voltage Compensated• MECL 10K-CompatibleCINXLHLHXLLLLFUNCTION SELECT TABLES1 S2 Operating ModeL L Preset (Program)L H Increment (Count Up)L H Hold CountH L Decrement (Count Down)H L Hold CountH H Hold (Stop Count)S1 S2 D0 D1 D2SEQUENTIAL TRUTH TABLE *INPUTSOUTPUTSDIP PIN ASSIGNMENTVCC1Q2Q3COUTD3D2S2VEED3CarryIn12345678Clock* *161514131211109Q0 Q1 Q2 Q3VCC2Q1Q0CLOCKD0D1CINS1CarryOutL L L H H X H L L H H LH X X X X L H H L H H HH X X X X L H L H H H HH X X X X L H H H H H LL H X X X XL H X X X XH H X X X XL L H H L LH L X X X XH L X X X XH L X X X XH L X X X XHHXXLLLLLHHHHHHHHHHHHHHHHHHLHHHLHHHLHHL H L LH L L LL L L L LH H H H H* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.** A clock H is defined as a clock input transition from a low to a high logic level.http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10H136L CDIP–16 25 Units/RailMC10H136P PDIP–16 25 Units/RailMC10H136FN PLCC–20 46 Units/Rail1161MC10H136LAWLYYWWMC10H136PAWLYYWW110H136AWLYYWWPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 788 Publication Order Number:MC10H136/D

MC10H136MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 165 – 150 – 165 mAIinH Input Current HighµAPins 5, 6, 11, 12, 13– 430 – 275 – 275Pin 9Pin 7Pin 10–––670535380–––420335240–––420335240IinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdtsettholdPropagation DelayClock to QClock to Carry OutCarry in to CarryOutSet-up TimeData (D0 to C)Select (S to C)Carry In (Cin to C)(C to Cin)Hold TimeData (C to D0)Select (C to S)Carry In (C to Cin)(Cin to C)0.71.00.72.03.52.000–0.502.2fcount Counting Frequency 250 – 250 – 250 – MHztr Rise Time 0.5 2.3 0.5 2.4 0.5 2.5 nstf Fall Time 0.5 2.3 0.5 2.4 0.5 2.5 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts.2.34.82.5––––––––0.71.00.72.03.52.000–0.502.22.44.92.6––––––––0.71.00.72.03.52.000–0.502.22.55.02.7––––––––°C°Cnsnsnshttp://onsemi.com89

MC10H136LOGIC DIAGRAMS1 9S2 7Carry In10TTQ0Q0CT Q1T Q1T CTTTQ2T Q3TT Q3C T T CT Q2 V CC1 = Pin 1Clock13V CC2 = Pin 16V EE = Pin 812D014Q011D115Q16D22Q25D33Q34Carry OutNOTE: FLIP-FLOPS WILL TOGGLE WHEN ALL T INPUTS ARE LOW.APPLICATION INFORMATIONThe MC10H136 is a high speed synchronous counter thatoperates at 250 MHz. Counter operating modes includecount up, count down, pre-set and hold count. This deviceallows the designer to use one basic counter for manyapplications.The S1, S2, control lines determine the operating modesof the counter. In the pre-set mode, a clock pulse is necessaryto load the counter with the information present on the datainputs (D0, D1, D2, and D3). Carry out goes low on theterminal count or when the counter is being pre-set.http://onsemi.com90

The MC10H141 is a four–bit universal shift register. This device is afunctional/pinout duplication of the standard MECL 10K part with100% improvement in propagation delay and operation frequency andno increase in power supply current.• Shift frequency, 250 MHz Min• Power Dissipation, 425 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatiblehttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H141LAWLYYWWTRUTH TABLESELECT OUTPUTSOPERATINGS1 S2 MODE Q0 n + 1 Q1 n + 1 Q2 n + 1 Q3 n + 1L L Parallel Entry D0 D1 D2 D3L H Shift Right* Q1 n Q2 n Q3 n DRH L Shift Left* DL Q0 n Q1 n Q2 nH H Stop Shift Q0 n Q1 n Q2 n 32 n* Outputs as exist after pulse appears at “C” input withinput conditions as shown (Pulse Positive transition ofclock input).PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H141PAWLYYWW110H141AWLYYWWVCC1DIPPIN ASSIGNMENT116VCC2A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekQ2Q3CDRD3S2234567151413121110Q1Q0DLD0D1S1ORDERING INFORMATIONDevice Package ShippingMC10H141L CDIP–16 25 Units/RailMC10H141P PDIP–16 25 Units/RailMC10H141FN PLCC–20 46 Units/RailVEE89D2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 791 Publication Order Number:MC10H141/D

MC10H141MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%, See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 112 – 102 – 112 mAIinH Input Current HighPins 5,6,9,11,12,13Pins 7,10Pin 4–––405416510–––255260320–––255260320µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 1.0 2.0 1.0 2.0 1.1 2.1 nsthold Hold Time –1.0 – 1.0 – 1.0 – nsData, SelecttsetSet–up TimeDataSelect1.53.0tr Rise Time 0.5 2.4 0.5 2.4 0.5 2.4 nstf Fall Time 0.5 2.4 0.5 2.4 0.5 2.4 nsfshift Shift Frequency 250 – 250 – 250 – MHz1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50 ohm resistor to –2.0 volts.––1.53.0––1.53.0––°C°Cnshttp://onsemi.com92

MC10H141LOGIC DIAGRAMS1S21 OF 4DECODERD3PARALLEL ENTERSHIFT RIGHTD2 D1 D0DRSHIFT LEFTHOLDDLDQDQDQDQCCCCCQ3Q2 Q1 Q0VCC1 = PIN 1SCC2 = PIN 16VEE = PIN 8APPLICATION INFORMATIONThe MC10H141 is a four–bit universal shift registerwhich performs shift left, or shift right, serial/parallel in, andserial/parallel out operations with no external gating. InputsS1 and S2 control the four possible operations of the registerwithout external gating of the clock. The flip–flops shiftinformation on the positive edge of the clock. The fouroperations are stop shift, shift left, shift right, and parallelentry of data. The other six inputs are all data type inputs;four for parallel entry data, and one for shifting in from theleft (DL) and one for shifting in from the right (DR).http://onsemi.com93

(Non–Inverting)The MC10H158 is a quad two channel multiplexer with commoninput select. A “high” level select enables input D00, D10, D20 andD30 and a “low” level select enables input D01, D11, D21 and D31.This MECL 10H part is a functional/pinout duplication of the standardMECL 10K family part, with 100% improvement in propagation delayand no increase in power–supply current.• Propagation Delay, 1.5 ns Typical• Power Dissipation, 197 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleTRUTH TABLESelect D0 D1 QL X L LL X H HH L X LH H X Hhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H158LAWLYYWWMC10H158PAWLYYWW110H158AWLYYWWQ0DIPPIN ASSIGNMENT116VCCA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekQ1215Q2ORDERING INFORMATIOND11314Q3Device Package ShippingD10413D20MC10H158L CDIP–16 25 Units/RailD01D00NC567121110D21D30D31MC10H158P PDIP–16 25 Units/RailMC10H158FN PLCC–20 46 Units/RailVEE89SELECTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 694 Publication Order Number:MC10H158/D

MC10H158MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 53 – 48 – 53 mAIinH Input Current HighPin 9Pins 3–6 and 10–13––475515––295320––295320µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayDataSelect0.51.0tr Rise Time 0.7 2.2 0.7 2.2 0.7 2.2 nstf Fall Time 0.7 2.2 0.7 2.2 0.7 2.2 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.LOGIC DIAGRAMSELECT 91.92.90.51.01.92.90.51.02.02.9°C°CnsD0 1 51 Q0D0 0 6D1 1 32 Q1D1 0 4D2 1 1215 Q2D2 0 13D3 1 1014 Q3D3 0 11VCC = PIN 16VEE = PIN 8http://onsemi.com95

(Inverting)The MC10H159 is a quad 2–input multiplexer with enable. ThisMECL 10H part is a functional/pinout duplication of the standardMECL 10K family part, with 100% improvement in propagation delayand no increase in power–supply current.• Propagation Delay, 1.5 ns Typical• Power Dissipation, 218 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatiblehttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H159LAWLYYWWEnableTRUTH TABLESelect D0 D1 QL L X L HL L X H LL H L X HL H H X LH X X X LPDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H159PAWLYYWW110H159AWLYYWWQ0Q1DIPPIN ASSIGNMENT121615VCCQ2A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIOND11314Q3Device Package ShippingD10413D20MC10H159L CDIP–16 25 Units/RailD01512D21MC10H159P PDIP–16 25 Units/RailD00ENABLE671110D30D31MC10H159FN PLCC–20 46 Units/RailVEE89SELECTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 696 Publication Order Number:MC10H159/D

MC10H159MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 58 – 53 – 58 mAIinH Input Current HighPin 9Pins 3–7 and 10–13––475515––295320––295320µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayDataSelectEnable0.51.01.0tr Rise Time 0.5 2.2 0.5 2.2 0.5 2.2 nstf Fall Time 0.5 2.2 0.5 2.2 0.5 2.2 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.23.23.20.51.01.02.23.23.20.51.01.02.23.23.2°C°Cnshttp://onsemi.com97

MC10H159APPLICATION INFORMATIONThe MC10H159 is a quad two channel multiplexer withenable. It incorporates common enable and common dataselect inputs. The select input determines which data inputsare enabled. A high (H) level enables data inputs D0 0, D10, D2 0, and D3 0. A low (L) level enables data inputs D01, D1 1, D2 1, and D3 1. Any change on the data inputs willbe reflected at the outputs while the enable is low. Inputlevels are inverted at the output.LOGIC DIAGRAMSELECT 9D0 1 51 Q0D0 0 6D1 1 32 Q1D1 0 4ENABLE 7D2 1 1215 Q2D2 0 13D3 1 1014 Q3D3 0 11VCC PIN 16VEE PIN 8http://onsemi.com98

The MC10H160 is a 12–bit parity generator–checker. The outputgoes high when an odd number of inputs are high providing the oddparity function. Unconnected inputs are pulled to a logic low allowingparity detection and generation for less than 12 bits. The MC10H160is a functional pin duplication of the standard 10K family part with100% improvement in propagation delay and no increase inpower–supply current.• Propagation Delay, 2.5 ns Typical• Power Dissipation, 320 mW Typical• Improved Noise Margin 150 mV(Over Operating Voltage and Temperature Range)• Voltage Compensated• MECL 10K–Compatible345679101112131415LOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT2TRUTH TABLEINPUTSum ofHigh LevelInputsEvenOddOUTPUTPin 2LowHighhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATION116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H160LAWLYYWWMC10H160PAWLYYWW110H160AWLYYWWVCC1OUT121615VCC2IN12Device Package ShippingMC10H160L CDIP–16 25 Units/RailIN1314IN11MC10H160P PDIP–16 25 Units/RailIN2IN3451312IN10IN9MC10H160FN PLCC–20 46 Units/RailIN4611IN8IN5710IN7VEE89IN6Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 699 Publication Order Number:MC10H160/D

MC10H160MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 88 – 78 – 88 mAIinH Input Current HighPins 3,5,7,10,12,14Pins 4,6,9,11,13,15––391457––246285––246285µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 1.1 3.1 1.1 3.3 1.2 3.5 nstr Rise Time 0.55 1.5 0.55 1.6 0.75 1.7 nstf Fall Time 0.55 1.5 0.55 1.6 0.75 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com100

The MC10H161 provides parallel decoding of a three bit binaryword to one of eight lines. The MC10H161 is useful in high–speedmultiplexer/demultiplexer applications.The MC10H161 is designed to decode a three bit input word to oneof eight output lines. The MC10H161 output will be low whenselected while all other output are high. The enable inputs, when eitheror both are high, force all outputs high.The MC10H161 is a true parallel decoder. This eliminates unequalparallel path delay times found in other decoder designs. Thesedevices are ideally suited for multiplexer/demultiplexer applications.• Propagation Delay, 1.0 ns Typical• Power Dissipation, 315 mW Typical (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleE0 2E1 15V CC1 = Pin 1V CC2 = Pin 16V EE = Pin 8A 7B 9C 14E0LLLLLLLLXHDIP PIN ASSIGNMENTLOGIC DIAGRAMQ4HHHHLHHHHH6 Q05 Q14 Q23 Q313 Q412 Q511 Q610 Q7TRUTH TABLEENABLEINPUTS INPUTS OUTPUTSE1 C B A Q0 Q1 Q2 Q3 Q5 Q6 Q7LLLLLLLLHXLLLLHHHHXXLLHHLLHHXXLHLHLHLHXXLHHHHHHHHHHLHHHHHHHHHHLHHHHHHHHHHLHHHHHHHHHHHLHHHHHHHHHHLHHHHHHHHHHLHHhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10H161L CDIP–16 25 Units/RailMC10H161P PDIP–16 25 Units/RailMC10H161FN PLCC–20 46 Units/Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H161LAWLYYWWMC10H161PAWLYYWW110H161AWLYYWWVCC1E0Q3Q2Q1Q0AVEE12345678161514131211109VCC2E1CQ4Q5Q6Q7BPin assignment is for Dual–in–LinePackage. For PLCC pin assignment, seethe Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6101 Publication Order Number:MC10H161/D

MC10H161MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 84 – 76 – 84 mAIinH Input Current High – 465 – 275 – 275 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayDataEnable0.60.8tr Rise Time 0.55 1.7 0.65 1.8 0.7 1.9 nstf Fall Time 0.55 1.7 0.65 1.8 0.7 1.9 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.02.30.650.82.12.40.70.92.22.5°C°Cnshttp://onsemi.com102

MC10H161Control SelectionTYPICAL APPLICATIONSHIGH SPEED 16–BIT MULTIPLEXER/DEMULTIPLEXERS0S1MC10H136C RA B C D15 14 13 12 11 10 9 87 6 5 4 3 2 1 0E1CBAMC10H164D0E1CBAMC10H164D0S0S1S0S1MC10H136C RA B C DC RStart/StopE1CBAE0MC10H161E1CBAE0MC10H16115 14 1312 11 10 9 87 6 5 4 3 2 1 01–OF–64 LINE MULTIPLEXEREA B CMC10H164D outEA B CMC10H164D outEA B CMC10H164D out1497MSBLSBMC10H161Q7Q6Q5Q4Q3Q2Q1Q0EEA B CMC10H164A B CMC10H164D outD outEA B CMC10H164D outEA B CThe Bit chosen is dependent on six–bitcode present on inputs 7, 9, 14 of theMC10H161 and the A, B, C inputs of theMC10H164.EMC10H164A B CD outMC10H164D outhttp://onsemi.com103

The MC10H162 provides parallel decoding of a three bit binaryword to one of eight lines. The MC10H162 is useful in high–speedmultiplexer/ demultiplexer applications.The MC10H162 is designed to decode a three bit input word to oneof eight output lines. The MC10H162 output will be high whenselected while all other output are low. The enable inputs, when eitheror both are high, force all outputs low.The MC10H162 is a true parallel decoder. This eliminates unequalparallel path delay times found in other decoder designs. Thesedevices are ideally suited for multiplexer/demultiplexer applications.• Propagation Delay, 1.0 ns Typical• Power Dissipation, 315 mW Typical (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleE0 2E1 15V CC1 = Pin 1V CC2 = Pin 16V EE = Pin 8A 7B 9C 14LOGIC DIAGRAMVCC1E0Q3Q2Q1Q0AVEEDIPPIN ASSIGNMENT12345678161514131211109VCC2E1CQ4Q5Q6Q7B6 Q05 Q14 Q23 Q313 Q412 Q511 Q610 Q7Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.E1LLLLLLLLXHINPUTShttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekTRUTH TABLEORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10H162L CDIP–16 25 Units/RailMC10H162P PDIP–16 25 Units/RailMC10H162FN PLCC–20 46 Units/Rail1161OUTPUTSMC10H162LAWLYYWWMC10H162PAWLYYWW110H162AWLYYWWE0 C B A Q0 Q1 Q2 Q3 Q5 Q6 Q7LLLLLLLLHXLLLLHHHHXXLLHHLLHHXXLHLHLHLHXXHLLLLLLLLLLHLLLLLLLLLLHLLLLLLLLLLHLLLLLLQ4LLLLHLLLLLLLLLLHLLLLLLLLLLHLLLLLLLLLLHLL© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6104 Publication Order Number:MC10H162/D

MC10H162MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 84 – 76 – 84 mAIinH Input Current High – 465 – 275 – 275 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayPins 7, 9, 14 OnlyPins 2, 15 Only0.70.8tr Rise Time 0.6 1.8 0.6 1.9 0.6 2.0 nstf Fall Time 0.6 1.8 0.6 1.9 0.6 2.0 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.02.30.70.82.12.40.80.92.52.6°C°Cnshttp://onsemi.com105

MC10H162TYPICAL APPLICATIONSFIGURE 1 – HIGH SPEED 16-BIT MULTIPLEXER/DEMULTIPLEXERControl SelectionS0S1MC10H136C RA B C D15 14 13 12 11 10 9 87 6 5 4 3 2 1 0E1CBAMC10H164D0E1CBAMC10H164D0S0S1S0S1MC10H136C RA B C DC RStart/StopE1CBAE0MC10H162E1CBAE0MC10H16215 14 13 12 11 10 9 87 6 5 4 3 2 1 0http://onsemi.com106

The MC10H164 is a MECL 10H part which is a functional/pinoutduplication of the standard MECL 10K family part, with 100%improvement in propagation delay, and no increase in power supplycurrent.The MC10H164 is designed to be used in data multiplexing andparallel to serial conversion applications. Full parallel gating providesequal delays through any data path. The MC10H164 incorporates anoutput buffer, eight inputs and an enable. A high on the enable forcesthe output low. The open emitter output allows the MC10H164 to beconnected directly to a data bus. The enable line allows an easy meansof expanding to more than 8 lines using additional MC10H164’s.• Propagation Delay, 1.0 ns Typical• Power Dissipation, 310 mW Typical (same as MECL 10K)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10H164LAWLYYWWMC10H164PAWLYYWW1A 7B 9C 10Enable 2X0 6X1 5X2 4X3 3VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8Z15PLCC–20FN SUFFIXCASE 775A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week10H164AWLYYWWX4 11X5 12X6 13X7 14DIP PIN ASSIGNMENTVCC1ENABLEX3X2X1X0AVEE12345678161514131211109VCC2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.ZX7X6X5X4CBTRUTH TABLEADDRESS INPUTSENABLE C B A ZLLLLLLLLLLHHLHLHX0X1X2X3LLLLHHHHLLHHLHLHX4X5X6X7H X XXLORDERING INFORMATIONDevice Package ShippingMC10H164L CDIP–16 25 Units/RailMC10H164P PDIP–16 25 Units/RailMC10H164FN PLCC–20 46 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7107 Publication Order Number:MC10H164/D

MC10H164MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 83 – 75 – 83 mAIinH Input Current High – 512 – 320 – 320 µAIinL Input Current Low 0.7 – 0.7 – 0.7 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayEnableDataAddress0.40.71.0tr Rise Time 0.5 1.5 0.5 1.6 0.5 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.5 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.452.42.80.40.81.11.52.52.90.50.91.21.72.63.2°C°Cnshttp://onsemi.com108

MC10H164TYPICAL APPLICATIONSFIGURE 1 – HIGH SPEED 16–BIT MULTIPLEXER/DEMULTIPLEXERControl SelectionS015 14 13 12 11 10 9 87 6 5 4 3 2 1 0S1MC10H136C RA B C DE1CBAMC10H164D0E1CBAMC10H164D0S0S1S0S1MC10H136C RA B C DC RStart/StopE1CBAE0MC10H161MC10H162E1CBAE0MC10H161MC10H16415 14 1312 11 10 9 8FIGURE 2 – 1–OF–64 LINE MULTIPLEXERA B CED outMC10H1647 6 5 4 3 2 1 0EA B CMC10H164D outEA B CMC10H164D out1497MSBLSBMC10H161Q7Q6Q5Q4Q3Q2Q1Q0EEA B CMC10H164A B CMC10H164D outD outThe Bit chosen is dependent on six–bitcode present on inputs 7, 9, 14 of theMC10H161 and the A, B, C inputs of theMC10H164.EEA B CMC10H164A B CD outMC10H164D outEA B CMC10H164D outhttp://onsemi.com109

The MC10H165 is an 8–Input Priority Encoder. This 10H part is afunctional/pinout duplication of the standard MECL 10K family part,with 100% improvement in propagation delay, and no increases inpower–supply current.• Propagation Delay, Data–to–Output, 2.2 ns Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleD0HLLLLLLLLD1XHLLLLLLLD2XXHLLLLLLDATA INPUTSD3XXXHLLLLLTRUTH TABLED4XXXXHLLLLD5XXXXXHLLLD6XXXXXXHLLD7XXXXXXXHLQ3HHHHHHHHLDIPPIN ASSIGNMENTOUTPUTSQ2LLLLHHHHLQ1LLHHLLHHLQ0LHLHLHLHLhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H165LAWLYYWWMC10H165PAWLYYWW110H165AWLYYWWVCC1Q1Q0123161514VCC2Q2Q3A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekCLOCKD0D7D1VEE45678Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.131211109D2D5D4D3D6ORDERING INFORMATIONDevice Package ShippingMC10H165L CDIP–16 25 Units/RailMC10H165P PDIP–16 25 Units/RailMC10H165FN PLCC–20 46 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6110 Publication Order Number:MC10H165/D

MC10H165MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic–55 to +150°C– Ceramic–55 to +165ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 144 – 131 – 144 mAIinH Input Current HighPin 4Data Inputs––510600––320370––320370µAdcIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation DelaynsData Input Output0.7 3.4 0.7 3.4 0.7 3.4Clock Input Output0.7 2.2 0.7 2.2 0.7 2.2tset Set–up Time 3.0 – 3.0 – 3.0 – nsthold Hold Time 0.5 – 0.5 – 0.5 – nstr Rise Time 0.5 2.4 0.5 2.4 0.5 2.4 nstf Fall Time 0.5 2.4 0.5 2.4 0.5 2.4 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.http://onsemi.com111

MC10H1658–INPUT PRIORITY ENCODERThe MC10H165 is a device designed to encode eightinputs to a binary coded output. The output code is that of thehighest order input. Any input of lower priority is ignored.Each output incorporates a latch allowing synchronousoperation. When the clock is low the outputs follow theinputs and latch when the clock goes high. This device isvery useful for a variety of applications in checking systemstatus in control processors, peripheral controllers, andtesting systems.The input is active when high, (e.g., the three binaryoutputs are low when input D0 is high). The Q3 output ishigh when any input is high. This allows direct extensioninto another priority encoder when more than eight inputsare necessary. The MC10H165 can also be used to developbinary codes from random logic inputs, for addressingROMs, RAMs, or for multiplexing data.LOGIC DIAGRAMC 4D0 5VCC1 = PIN 1VCC2 = PIN 16. VEE = PIN 8D1 7D2 133 Q0D3 10D4 112 Q1D5 1215 Q2D6 9D7 614 Q3Numbers at ends of terminals denote pin numbers for L and P packages.http://onsemi.com112

MC10H165APPLICATION INFORMATIONA typical application of the MC10H165 is the decoding ofsystem status on a priority basis. A 64–line priority encoderis shown in the figure below. System status lines areconnected to this encoder such that, when a given conditionexists, the respective input will be at a logic high level. Thisscheme will select the one of 64 different system conditions,as represented at the encoder inputs, which has priority indetermining the next system operation to be performed. Thebinary code showing the address of the highest priority inputpresent will appear at the encoder outputs to control othersystem logic functions.64–LINE PRIORITY ENCODERLSBZ Z ZMC10H164 MC10H164 MC10H164SystemClockHighestPriorityInput1/2 MC10H101CD0D7CD0D7MC10H165 MC10H165Q0Q1Q2Q3Q0Q1Q2Q3X0. . . . . . . X7 A B CX0. . . . . . . X7 A B C X0 . . . . . . . X7 A B CCD0D7Q0Q1Q2MSBSix bit outputword yieldingnumber ofhighest prioritychannel presentat inputCD0D7MC10H165Q0Q1Q2Q3CD0D7MC10H165Q0Q1Q2Q3CD0D7MC10H165Q0Q1Q2Q3CD0D7MC10H165Q0Q1Q2Q3CD0D7MC10H165Q0Q1Q2Q3LowestPriorityInputCD0D7MC10H165Q0Q1Q2Q3http://onsemi.com113

The MC10H166 is a 5–Bit Magnitude Comparator and is afunctional/ pinout duplication of the standard MECL 10K part with100% improvement in propagation delay and no increase inpower–supply current.The MC10H166 is a high–speed expandable 5–bit comparator forcomparing the magnitude of two binary words. Two outputs areprovided: AB. The A = B function can be obtained bywire–ORing these outputs (a low level indicates A = B) or bywire–NORing the outputs (a high level indicates A = B). A high levelon the enable function forces both outputs low.• Propagation Delay, Data–to–Output, 2.0 ns Typical• Power Dissipation 440 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleTRUTH TABLEInputsOutputsE A B A < B A > BHLLLX X LWORD A = WORD B LWORD A > WORD B LWORD A < WORD BHDIPPIN ASSIGNMENTLLHLhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATION116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10h166LAWLYYWWMC10h166PAWLYYWW110h166AWLYYWWVCC1A>BA

MC10H166MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 117 – 106 – 117 mAIinH Input Current High – 350 – 220 – 220 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayData–to–OutputEnable–to–Output1.10.6tr Rise Time 0.6 1.5 0.6 1.6 0.6 1.7 nstf Fall Time 0.6 1.5 0.6 1.6 0.6 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.3.51.71.10.73.71.71.20.74.11.8°C°Cnshttp://onsemi.com115

MC10H166LOGIC DIAGRAMA4 9B4 10A3 12B3 112 A > BA2 13B2 143 A < BA1 6B1 7A0 5B0 4E 15VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8FIGURE 1 – 9–BIT MAGNITUDE COMPARATORA0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8A0 A1 A2 A3 A4B0 B1 B2 B3 B4A0 A1 A2 A3 A4B0 B1 B2 B3 B4MC10H166A > BA < BA > BA < BA>B A B andA < B outputs are fed to the A0 and B0 inputs respectivelyof the next device. The connection for an A = B output is alsoshown. The worst case delay time of serial expansion isequal to the number of comparators times thedata–to–output delay.http://onsemi.com116

MC10H166FIGURE 2 – 25–BIT MAGNITUDE COMPARATORB24A24B23A23B22A22B21A21B20A20B4A4B3A3B2A2B1A1B0A0A < BA > BB19A19B18A18B17A17B16A16B15A15B4A4B3A3B2A2B1A1B0A0A < BA > BB14A14B13A13B12A12B11A11B10A10B4A4B3A3B2A2B1A1B0A0A < BA > BB4A4B3A3 A < BB2A2B1 A > BA1B0A0A = BA < BA > BB9A9B8A8B7A7B6A6B5A5B4A4B3A3B2A2B1A1B0A0B4A4B3A3B2A2B1A1B0A0B4A4B3A3B2A2B1A1B0A0A < BA > BA < BA > BFor shorter delay times than possible with serial expansion,devices can be cascaded. Figure 2 shows a 25–bit cascadedcomparator whose worst case delay is two data–to–output delays.The cascaded scheme can be extended to longer word lengths.http://onsemi.com117

The MC10H171 is a binary coded 2 line to dual 4 line decoder withselected outputs low. With either E0 or E1 high, the correspondingselected 4 outputs are high. The common enable E, when high, forcesall outputs high.• Propagation Delay, 2 ns Typical• Power Dissipation 325 mW Typical (same as MECL 10K)• Improved Noise Margin 150 mV (over operating voltage andtemperature range)• Voltage Compensated• MECL 10K–CompatibleE0 14A 9B 7LOGIC DIAGRAM10 Q0 311 Q0 212 Q0 113 Q0 03 Q1 34 Q1 2http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H171LAWLYYWWMC10H171PAWLYYWW110H171AWLYYWWE 15E1 2VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT5 Q1 16 Q1 0A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingVCC1116VCC2MC10H171L CDIP–16 25 Units/RailE1215EMC10H171P PDIP–16 25 Units/RailQ13314E0MC10H171FN PLCC–20 46 Units/RailQ12413Q00Q11512Q01Q10611Q02B710Q03VEE89APin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6118 Publication Order Number:MC10H171/D

MC10H171MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic–55 to +150°C– Ceramic–55 to +165ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 85 – 77 – 85 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERS0° 25° 75°Symbol Characteristic Min Max Min Max Min Max Unittpd Propagation DelaynsDataSelect0.50.52.02.60.50.52.12.70.50.52.22.8tr Rise Time 0.5 1.7 0.5 1.8 0.5 1.9 nstf Fall Time 0.5 1.7 0.5 1.8 0.5 1.9 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.TRUTH TABLEEnable Inputs Inputs OutputsE E0 E1 A B Q10 Q11 Q12 Q13 Q00 Q01 Q02 Q03L L L L L L H H H L H H HL L L L H H L H H H L H HL L L H L H H L H H H L HL L L H H H H H L H H H LL L H L L H H H H L H H HL H L L L L H H H H H H HH X X X X H H H H H H H Hhttp://onsemi.com119

The MC10H172 is a binary coded 2 line to dual 4 line decoder withselected outputs high. With either E0 or E1 low, the correspondingselected 4 outputs are low. The common enable E, when high, forcesall outputs low.• Propagation Delay, 2 ns Typical• Power Dissipation 325 mW Typical (same as MECL 10K)• Improved Noise Margin 150 mV (over operating voltage andtemperature range)• Voltage Compensated• MECL 10K–CompatibleE0 14A 9B 7LOGIC DIAGRAM10 Q0 311 Q0 212 Q0 113 Q0 03 Q1 34 Q1 2http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H172LAWLYYWWMC10H172PAWLYYWW110H172AWLYYWWE 15E1 2VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT5 Q1 16 Q1 0A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingVCC1116VCC2MC10H172L CDIP–16 25 Units/RailE1215EMC10H172P PDIP–16 25 Units/RailQ13314E0MC10H172FN PLCC–20 46 Units/RailQ12413Q00Q11512Q01Q10611Q02B710Q03VEE89APin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6120 Publication Order Number:MC10H172/D

MC10H172MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIoutOutput Current – Continuous– Surge50100mATA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– Ceramic–55 to +150–55 to +165°CELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 85 – 77 – 85 mAIinH Input Current High – 425 – 265 – 265 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERS0° 25° 75°Symbol Characteristic Min Max Min Max Min Max Unittpd Propagation DelaynsDataSelect0.50.52.02.60.50.52.12.70.50.52.22.8tr Rise Time 0.5 1.7 0.5 1.8 0.5 1.9 nstf Fall Time 0.5 1.7 0.5 1.8 0.5 1.9 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.TRUTH TABLEEnable Inputs Inputs OutputsE E1 E0 A B Q1 0 Q1 1 Q1 2 Q1 3 Q0 0 Q0 1 Q0 2 Q0 3L H H L L H L L L H L L LL H H L H L H L L L H L LL H H H L L L H L L L H LL H H H H L L L H L L L HL L H L L L L L L H L L LL H L L L H L L L L L L LH X X X X L L L L L L L LX = Don’t Carehttp://onsemi.com121

The MC10H173 is a quad 2–input multiplexer with latch. Thisdevice is a functional/pinout duplication of the standard MECL 10Kpart, with 100% improvement in propagation delay and no increase inpower supply current.• Data Propagation Delay, 1.5 ns Typical• Power Dissipation, 275 mW Typical• Improved Noise Margin 150 mV (overoperating voltage and temperature range)• Voltage Compensated• MECL 10K–CompatibleTRUTH TABLESELECT CLOCK Q0n + 1HLXLLHD00D01Q0nhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10H173LAWLYYWWMC10H173PAWLYYWW1DIPPIN ASSIGNMENTPLCC–20FN SUFFIXCASE 77510H173AWLYYWWQ0Q1D11D10123416151413VCCQ2Q3D20A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekD01D00CLOCKVEE56781211109D21D30D31SELECTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.ORDERING INFORMATIONDevice Package ShippingMC10H173L CDIP–16 25 Units/RailMC10H173P PDIP–16 25 Units/RailMC10H173FN PLCC–20 46 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6122 Publication Order Number:MC10H173/D

MC10H173MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 73 – 66 – 73 mAIinH Input Current HighµAPins 3–7 & 10–13– 510 – 320 – 320Pin 9– 475 – 300 – 300IinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdtsettholdPropagation DelayDataClockSelectSet–up TimeDataSelectHold TimeDataSelect0.71.01.00.71.00.71.0tr Rise Time 0.7 2.4 0.7 2.4 0.7 2.4 nstf Fall Time 0.7 2.4 0.7 2.4 0.7 2.4 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.33.73.6––––0.71.01.00.71.00.71.02.33.73.6––––0.71.01.00.71.00.71.02.33.73.6––––°C°Cnsnsnshttp://onsemi.com123

MC10H173APPLICATION INFORMATIONThe MC10173 is a quad two–channel multiplexer withlatch. It incorporates common clock and common dataselect inputs. The select input determines which data inputis enabled. A high (H) level enables data inputs D00, D10,D20, and D30 and a low (L) level enables data inputs D01,D11, D21, D31. Any change on the data inputwill be reflected at the outputs while the clock is low. Theoutputs are latched on the positive transition of the clock.While the clock is in the high state, a change in theinformation present at the data inputs will not affect theoutput information.LOGIC DIAGRAMSELECT 9D00 61 Q0D01 5D10 42 Q1D11 3D20 1315 Q2D21 12D30 1114 Q3D31 10CLOCK 7VCC = PIN 16VEE = PIN 8http://onsemi.com124

The MC10H174 is a Dual 4–to–1 Multiplexer. This device is afunctional/ pinout duplication of the standard MECL 10K part, with100% improvement in propagation delay and no increase in powersupply current.• Propagation Delay, 1.5 ns Typical• Power Dissipation, 305 mW Typical• Improved Noise Margin 150 mV (over operating voltage andtemperature range)• Voltage Compensated• MECL 10K–CompatibleX0 3LOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H174LAWLYYWWX1 5X2 4X3 62 ZPDIP–16P SUFFIXCASE 648161MC10H174PAWLYYWW1A 7B 9VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8PLCC–20FN SUFFIXCASE 77510H174AWLYYWWENABLE 14Y0 13Y1 1115 WA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekY2 12TRUTH TABLEY3 10ENABLE ADDRESS INPUTS OUTPUTSE B A Z WDIP PIN ASSIGNMENTH XX L LVCC1116VCC2L L L X0 Y0L L H X1 Y1Q0215Q1L H L X2 Y2DO0314ENABLEL H H X3 Y3DO2413D10DO1512D12ORDERING INFORMATIONDO3611D11Device Package ShippingA710D13MC10H174L CDIP–16 25 Units/RailVEE89BMC10H174P PDIP–16 25 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.MC10H174FN PLCC–20 46 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7125 Publication Order Number:MC10H174/D

MC10H174MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 80 – 73 – 80 mAIinH Input Current HighPins 3–7 & 9–13Pin 14––475670––300420––300420µAdcIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayDataSelect (A, B)Enable0.71.00.4tr Rise Time 0.5 1.5 0.5 1.6 0.5 1.7 nstf Fall Time 0.5 1.5 0.5 1.6 0.5 1.7 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.42.81.450.81.10.42.52.91.50.91.20.52.63.21.7°C°Cnshttp://onsemi.com126

The MC10H175 is a quint D type latch with common reset andclock lines. This MECL 10KH part is a functional/pinout duplicationof the standard MECL 10K family part, with 100% improvement inpropagation delay and no increase in power–supply current.• Propagation Delay, 1.2 ns Typical• Power Dissipation, 400 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleTRUTH TABLED C0 C1 Reset Qn+1LHXXXXLLHXHXLLXHXHXXLLHHLHQnQnLLhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10H175LAWLYYWWMC10H175PAWLYYWW1VCC1Q2DIPPIN ASSIGNMENT121615VCC2Q1PLCC–20FN SUFFIXCASE 775A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week10H175AWLYYWWQ3Q4D4C0345614131211Q0D2D1RESETORDERING INFORMATIONDevice Package ShippingMC10H175L CDIP–16 25 Units/RailC1710D0MC10H175P PDIP–16 25 Units/RailVEE89D3MC10H175FN PLCC–20 46 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6127 Publication Order Number:MC10H175/D

MC10H175MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 107 – 97 – 107 mAIinH Input Current HighPins 5,6,7,9,10,12,13Pin 11––5651120––335660––335660µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayDataClockReset0.60.71.0tset Set–up Time 1.5 – 1.5 – 1.5 – nsthold Hold Time 0.8 – 0.8 – 0.8 – nstr Rise Time 0.5 1.8 0.5 1.9 0.5 2.0 nstf Fall Time 0.5 1.8 0.5 1.9 0.5 2.0 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.1.61.92.20.60.71.01.62.02.30.60.81.01.72.12.4°C°Cnshttp://onsemi.com128

MC10H175APPLICATION INFORMATIONThe MC10H175 is a high speed, low power quint latch. Itfeatures five D type latches with common reset and acommon two–input clock. Data is transferred on thenegative edge of the clock and latched on the positive edge.The two clock inputs are “OR”ed together.Any change on the data input will be reflected at theoutputs while the clock is low. The outputs are latched on thepositive transition of the clock. While the clock is in the highstate, a change in the information present at the data inputswill not affect the output information. THE RESET INPUTIS ENABLED ONLY WHEN THE CLOCK IS IN THEHIGH STATE.LOGIC DIAGRAMD0 10DQ14 Q0CRD1 12DQ15 Q1CRD2 13DQ2 Q2CRD3 9DQ3 Q3CRD4 5DQ4 Q4C0 6C1 7CRRESET 11VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8http://onsemi.com129

The MC10H176 contains six master slave type D flip–flops with acommon clock. This MECL 10H part is a functional/pinoutduplication of the standard MECL 10K family part, with 100%improvement in clock frequency and propagation delay and noincrease in power–supply current.• Propagation Delay, 1.7 ns Typical• Power Dissipation, 460 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatiblehttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H176LAWLYYWWCLOCKED TRUTH TABLECLH *H *QXLHQn+1QnLH* A clock H is a clock transition froma low to a high state.PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H176PAWLYYWW110H176AWLYYWWVCC1Q0DIPPIN ASSIGNMENT121615VCC2Q5A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONQ1314Q4Device Package ShippingQ2413Q3MC10H176L CDIP–16 25 Units/RailD0D1D2567121110D5D4D3MC10H176P PDIP–16 25 Units/RailMC10H176FN PLCC–20 46 Units/RailVEE89CLOCKPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6130 Publication Order Number:MC10H176/D

MC10H176MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 123 – 112 – 123 mAIinH Input Current HighPins 5,6,7,10,11,12Pin 9––425670––265420––265420µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.9 2.1 0.9 2.2 1.0 2.4 nstset Set–up Time 1.5 – 1.5 – 1.5 – nsthold Hold Time 0.9 – 0.9 – 1.0 – nstr Rise Time 0.5 1.8 0.5 1.9 0.5 2.0 nstf Fall Time 0.5 1.8 0.5 1.9 0.5 2.0 nsftog Toggle Frequency 250 – 250 – 250 – MHz1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com131

MC10H176APPLICATION INFORMATIONThe MC10H176 contains six high–speed, master slavetype “D” flip–flops. Data is entered into the master when theclock is low. Master–to–slave data transfer takes place onthe positive–going Clock transition. Thus, outputs maychange only on a positive–going Clock transition. A changein the information present at the data (D) input will not affectthe output information any other time due to themaster–slave construction of this device.LOGIC DIAGRAMD052Q0D163 Q1D274 Q2D31013 Q3D41114 Q4D51215 Q5CLOCK 9VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8http://onsemi.com132

The MC10H179 is a functional/pinout duplication of the standardMECL 10K part, with 100% improvement in propagation delay andno increase in power supply current.• Power Dissipation, 300 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleVCC1GGCN+4G0G3DIPPIN ASSIGNMENT123451615141312VCC2PGP0P3P2http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10H179LAWLYYWWMC10H179PAWLYYWW1CN+2G1VEE67811109CNP1G2PLCC–20FN SUFFIXCASE 77510H179AWLYYWWPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H179L CDIP–16 25 Units/RailMC10H179P PDIP–16 25 Units/RailMC10H179FN PLCC–20 46 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6133 Publication Order Number:MC10H179/D

MC10H179MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIoutOutput Current – Continuous– Surge50100mATA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– Ceramic–55 to +150–55 to +165°C°CELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 79 – 72 – 79 mAIinH Input Current HighPins 5 and 9Pins 4, 7 and 11Pin 14Pin 12Pins 10 and 13–––––465545705790870–––––275320415465510–––––275320415465510µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation DelaynsP to PGG, P, Cn toCn or GG0.40.61.42.30.40.71.52.40.50.81.72.6tr Rise Time 0.5 1.7 0.5 1.8 0.5 1.9 nstf Fall Time 0.5 1.7 0.5 1.8 0.5 1.9 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.http://onsemi.com134

MC10H179LOGIC DIAGRAMG3 5P3 13G2 93 CN+4P2 122 GGCN 1115 PGG1 7P1 10G0 46 CN+2P0 14PG = P0 + P1 + P2 + P3GG = (G0 + P1 + P2 + P3) (G1 + P2 + P3) (G2 + P3) G3CN+2 = (CN + P0 + P1) (G0 + P1) G1CN+4 = (CN + P0 + P1 + P2 + P3) (G0 + P1 + P2 + P3) (G1 + P2 + P3)(G2 + P3) G3VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8TYPICAL APPLICATIONSThe MC10H179 is a high–speed, low–power, standardMECL complex function that is designed to perform thelook–ahead carry function. This device can be used with theMC10H181 4–bit ALU directly, or with the MC10H180dual arithmetic unit in any computer, instrumentation ordigital communication application requiring high speedarithmetic operation on long words.When used with the MC10H181, the MC10H179performs a second order or higher look–ahead. Figure 2shows a 16–bit look–ahead carry arithmetic unit. Secondorder carry is valuable for longer binary words. As anexample, addition of two 32–bit words is improved from 30nanoseconds with ripple–carry techniques. A block diagramof a 32–bit ALU is shown in Figure 1. The MC10H179 mayalso be used in many other applications. It can, for example,reduce system package count when used to generatefunctions of several variables.FIGURE 1 – 32–BIT ALU WITH CARRY LOOK–AHEADC inALUALUALUALUALUALUALUC n C n+4 C nC n C n+4 C nC n C n+4 C nC n C n+4P GP GP GP GP GP GP GALUC nP GAdd Time =18 ns typC n+2C n+2C n MC10H179C n+4 C n MC10H179C n+4C outhttp://onsemi.com135

MC10H179FIGURE 2 – 16–BIT FULL LOOK–AHEAD CARRY ARITHMETIC LOGIC UNITA0A1B0B1A2B2A3B3A4A5B4B5A6B6A7B7A8A9B8B9A10B10A11B11A13B12A12B13A14B14A15B15C in 0A B A B A B A0 0 1 1 2 2 3C nMS0 MC10H181S1 4-BIT ARITHMETICS2LOGIC UNITS3F0 F1 F2 F3B3GPA B A B A B A B0 0 1 1 2 2 3 3C nC n + 4MS0 MC10H181 GS1 4-BIT ARITHMETICS2LOGIC UNITPS3F0 F1 F2 F3A B A B A B A B0 0 1 1 2 2 3 3C nC n + 4MS0 MC10H181 GS1 4-BIT ARITHMETICS2LOGIC UNITPS3F0 F1 F2 F3A B A B A B A B0 0 1 1 2 2 3 3C nC n + 4MS0 MC10H181 GS1 4-BIT ARITHMETICS2LOGIC UNITPS3F0 F1 F2 F3MS0S1S2S3F0F1 F2 F3C n + 4P0 G0 P1 G1 P2 G2 P3 G3F4 F5 F6 F7F8 F9 F10 F11F12 F13 F14 F15C nMC10H179CARRY LOOK-AHEADC n + 2 C n + 4GPC15http://onsemi.com136

The MC10H180 is a high–speed, low–power, general–purposeadder/ subtractor. It is designed to be used in special purposeadders/subtractors or in high–speed multiplier arrays.Inputs for each adder are Carry–in, Operand A, and Operand B;outputs are Sum, Sum and Carry–out. The common select inputs serveas a control line to Invert A for subtract, and a control line to Invert B.• Propagation Delay, 1.8 ns Typical, Operand and Select to Output• Power Dissipation, 360 mW Typicalh180• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible79564111012LOGIC DIAGRAMSELASELBAOBOCINSELASELBA1B1CINS0S0COUTS1S1COUTVCC = PIN 16VEE = PIN 8POSITIVE LOGIC ONLYA’ = A SELA = ASELAB’ = B SELB = BSELBS = CIN (A’ B’ + A’ B’) +CIN(A’ B’ + A’ B’)COUT = CINA’ + CINB’ + A’ B’DIP PIN ASSIGNMENT152314113http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10H180L CDIP–16 25 Units/RailMC10H180P PDIP–16 25 Units/Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H180LAWLYYWWMC10H180PAWLYYWW110H180AWLYYWWS1S0121615VCCS0MC10H180FN PLCC–20 46 Units/RailCOUT314S1CIN413COUTA0512CINB0611A1SELA710B1VEE89SELBPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6137 Publication Order Number:MC10H180/D

MC10H180MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 95 – 86 – 95 mAIinH Input Current HighPins 4, 12Pins 7, 9Pins 5, 6, 10, 11–––665515410–––417320255–––417320255µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage (1) –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage (1) –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayOperand to OutputSelect to OutputCarry–in to Output0.60.60.4tr Rise Time 0.5 2.0 0.5 2.1 0.5 2.2 nstf Fall Time 0.5 2.0 0.5 2.1 0.5 2.2 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.42.21.6FUNCTION SELECT TABLESelA SelB FunctionH H S = A plus BHLLLHL0.70.70.4S = A minus BS = B minus AS = 0 minus A minus B2.52.31.70.80.80.42.82.61.8°C°CnsTRUTH TABLEFUNCTIONADDSUBTRACTINPUTSSel A Sel B A0 B0 C in S0 S0 C outHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLHHHHLLLLHHHHLLHHLLHHLLHHLLHHLHLHLHLHLHLHLHLHLHHLHLLHHLLHLHHLHLLHLHHLLHHLHLLHLLLHLHHHLHLLHHLHFUNCTIONREVERSESUBTRACTINPUTSSel A Sel B A0 B0 C in S0 S0 C outLLLLLLLLLLLLLLLLHHHHHHHHLLLLLLLLLLLLHHHHLLLLHHHHLLHHLLHHLLHHLLHHLHLHLHLHLHLHLHLHHLLHLHHLLHHLHLLHLHHLHLLHHLLHLHHLLHHHLLLHHHLHLHLLhttp://onsemi.com138

The MC10H181 is a high–speed arithmetic logic unit capable ofperforming 16 logic operations and 16 arithmetic operations on twofour–bit words. Full internal carry is incorporated for ripple throughoperation.Arithmetic logic operations are selected by applying the appropriatebinary word to the select inputs (S0 through S3) as indicated in thetables of arithmetic/logic functions. Group carry propagate (PG) andcarry generate (GG) are provided to allow fast operations on very longwords using a second order look–ahead. The internal carry is enabledby applying a low level voltage to the mode control input (M).When used with the MC10H179, full–carry look–ahead, as a secondorder look–ahead block, the MC10H181 provides high–speedarithmetic operations on very long words.This 10H part is a functional/pinout duplication of the standardMECL 10K family part with 100% improvement in propagation delayand no increase in power supply current.• Improved Noise Margin, 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K – Compatiblehttp://onsemi.comCDIP–24L SUFFIXCASE 758PDIP–24P SUFFIXCASE 724PLCC–28FN SUFFIXCASE 776241241MARKINGDIAGRAMSMC10H181LAWLYYWWMC10H181PAWLYYWW110H181AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H181L CDIP–24 15 Units/RailMC10H181P PDIP–24 15 Units/RailMC10H181FN PLCC–28 37 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7139 Publication Order Number:MC10H181/D

MC10H181S3 13S2 15S1 17LOGIC DIAGRAMS0 142 F0B0 20A0 213 F1B1 19A1 187 F2B2 11A2 166 F3B3 98 P GA3 104 G G5 C n+4C n 22M 23V CC1 = Pin 1V CC2 = Pin 24V EE = Pin 12http://onsemi.com140

MC10H181FUNCTION SELECT TABLELOGIC DIAGRAMLogic Functions Arithmetic OperationFunction SelectM is High C = DC D.C.M is Low C n is lowS3 S2 S1 S0FF13L L L L F = A F = A15L L L H F = A + B F = A plus (A • B)17L L H L F = A + B F = A plus (A • B)14L L H H F = Logical “1” F = A times 2S0 S1 S2 S3L H L L F = A • B F = (A + B) plus 021 A0 F0 2 L H L H F = B F = (A + B) plus (A • B)20 B0L H H L F = A B F = A plus BF1318 A1L H H H F = A + B F = A plus (A + B)19 B1 F2 7 H L L L F = A • B F = (A + B) plus 016A2H L L H F = A B F = A minus B minus 1F3611 B2H L H L F = B F = (A + B) plus (A • B)10 A3GG4H L H H F = A + B F = A plus (A + B)9 B3H H L L F = Logical “0” F = minus 1 (two’s complement)P G 822 C H H L H F = A • B F = (A • B) minus 1n23 M C n+4 5 H H H L F = A • B F = (A • B) minus 1H H H H F = A F = A minus 1DIPPIN ASSIGNMENTVCC1124VCC2F0223MF1322CNGG421A0CN + 4520B0F3619B1F2718A1PG817S1B3916A2A31015S2B21114S0VEE1213S3Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– Ceramic–55 to +150–55 to +165°C°Chttp://onsemi.com141

MC10H181ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5.0%) (See Note 1.)0° +25° +75°Characteristic Symbol Min Max Min Max Min Max UnitPower Supply Current I E – 159 – 145 – 159 mAInput Current HighPin 22Pins 14,23Pins 13,15,17Pins 10,16,18,21Pins 9,11,19,20I inH–––––720405515475465–––––450255320300275–––––450255320300275µAInput Current LowPins 9–11, 13–22I inL 0.5 – 0.5 – 0.3 – µAHigh Output Voltage V OH –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcLow Output Voltage V OL –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcHigh Input Voltage V IH –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcLow Input Voltage V IL –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.AC PARAMETERSAC Switching Characteristics0°C +25°C +75°CCharacteristic Symbol Input Output Conditions Min Max Min Max Min Max UnitPropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall Timet+ +, t– –t+, t–t+ +, t+ –,t– +, t– –t+, t–t+ +, t+ –,t– +, t– –t+, t–t+ +, t– –t+, t–t+ +, t– –t+, t–t+ –, t– +t+, t–t+ +, t– +t+, t–t+ +, t– –t+, t–t+ +, t– –t+, t–t+ –, t– +t+, t–t+ +, t+ –t+, t–t+ –, t– +t+, t–t– +, t+ –t+, t–t+ –, t– +t+, t–t+ –, t– +t+, t–C nC nC n+4C n+4C nC nC nA1A1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1MMS1S1S1S1S1S1S1S1F1F1F1F1F1F1P GP GG GG GC n+4C n+4F1FP GP GG GG GC n+4C n+4F1F1F1F1P GP GC n+4C n+4G GG GA0,A1,A2,A3A0,A1,A2,A3A0S0,S3S0,S30.70.61.00.71.50.71.50.9A0,A2,A3,C n 1.5A0,A2,A3,C n 0.7A0,A2,A3,C n 1.5A0,A2,A3,C n 0.5S3,C n 2.0S3,C n 0.7S0,A1S0,A11.50.7S3,C n 1.5S3,C n 0.7S3,C n 2.0S3,C n 0.5––A1,B1A1,B1A3,B3A3,B3A3,B3A3,B3A3,B3A3,B31.50.81.50.71.50.71.50.71.30.52.02.03.02.23.72.03.72.43.72.23.62.04.52.33.82.23.72.24.02.04.22.34.52.04.02.04.12.24.53.20.70.61.00.71.50.71.50.91.50.71.50.52.00.71.50.71.50.72.00.51.50.81.50.71.50.71.50.71.30.52.02.03.02.23.72.03.72.43.72.23.62.04.52.33.82.23.72.24.02.24.22.34.52.04.02.24.12.24.53.20.70.71.20.71.60.71.60.91.60.71.60.52.10.71.60.71.60.72.10.51.60.81.60.71.60.71.60.71.40.52.22.23.32.44.02.24.02.63.92.43.92.24.82.54.02.44.02.44.32.24.52.54.82.24.32.44.42.44.83.4nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns† Logic high level (+1.11 Vdc) applied to pins listed. All other input pins are left floating or tied to +0.31 Vdc.VCC1 = VCC2 = +2.0 Vdc, VEE = –3.2 Vdchttp://onsemi.com142

The MC10H186 is a hex D type flip–flop with common reset andclock lines. This MECL 10H part is a functional/pinout duplication ofthe standard MECL 10K family part, with 100% improvement in clocktoggle frequency and propagation delay and no increase inpower–supply current.• Propagation Delay, 1.7 ns Typical• Power Dissipation, 460 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatiblehttp://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10H186LAWLYYWWCLOCKED TRUTH TABLERLLLHCLH *H *LDXLHXQn+1QnLHL* A clock H is a clock transition froma low to a high state.PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10H186PAWLYYWW110H186AWLYYWWRESETQ0DIPPIN ASSIGNMENT121615VCCQ5A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekQ1314Q4ORDERING INFORMATIONQ2D0D1D2VEE45678131211109Q3D5D4D3CLOCKDevice Package ShippingMC10H186L CDIP–16 25 Units/RailMC10H186P PDIP–16 25 Units/RailMC10H186FN PLCC–20 46 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6143 Publication Order Number:MC10H186/D

MC10H186MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous– Surge50100mATA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 121 – 110 – 121 mAIinH Input Current HighµAPins 5,6,7,10,11,12– 430 – 265 – 265Pin 9Pin 1––6701250––420765––420765IinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.7 3.0 0.7 3.0 0.7 3.0 nstset Set–up Time 1.5 – 1.5 – 1.5 – nsthold Hold Time 1.0 – 1.0 – 1.0 – nstr Rise Time 0.7 2.6 0.7 2.6 0.7 2.6 nstf Fall Time 0.7 2.6 0.7 2.6 0.7 2.6 nsftog Toggle Frequency 250 – 250 – 250 – MHztrr Reset Recovery Time3.0 – 3.0 – 3.0 – ns(t1–9+)1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com144

MC10H186APPLICATION INFORMATIONThe MC10H186 contains six high–speed, master slavetype “D” flip–flops. Data is entered into the master when theclock is low. Master–to–slave data transfer takes place onthe positive–going Clock transition. Thus outputs maychange only on a positive–going Clock transition. A changein the information present at the data (D) input will not affectthe output information any other time due to themaster–slave construction of this device. A common Resetis included in this circuit. THE RESET ONLYFUNCTIONS WHEN THE CLOCK IS LOW.LOGIC DIAGRAMD052Q0D163 Q1D274 Q2D31013 Q3D41114 Q4D51215 Q5CLOCK9RESET 1VCC = PIN 16VEE = PIN 8http://onsemi.com145

The MC10H188 is a high–speed Hex Buffer with a common Enableinput. When Enable is in the high–state, all outputs are in thelow–state. When Enable is in the low–state, the outputs take the samestate as the inputs.This MECL 10H part is a functional/pinout duplication of thestandard MECL 10K family part, with 100% improvement inpropagation delay and no increase in power–supply current.• Propagation Delay, 1.3 ns Typical Data–to–Output• Power Dissipation 180 mW Typ/Pkg (No Load)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible9567101112XYLOGIC DIAGRAMOUT234131415TRUTH TABLEInputs OutputX Y OUTL L LL H HH L LH H LV CC1 = Pin 1V CC2 = Pin 16V EE = Pin 8http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H188LAWLYYWWMC10H188PAWLYYWW110H188AWLYYWWDIPPIN ASSIGNMENTORDERING INFORMATIONDevice Package ShippingVCC1116VCC2MC10H188L CDIP–16 25 Units/RailAOUTBOUTCOUT234151413FOUTEOUTDOUTMC10H188P PDIP–16 25 Units/RailMC10H188FN PLCC–20 46 Units/RailAIN512FINBIN611EINCIN710DINVEE89COMMONPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6146 Publication Order Number:MC10H188/D

MC10H188MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 46 – 42 – 46 mAIinH Input Current High – 495 – 310 – 310 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayEnableData0.70.7tr Rise Time 0.7 2.4 0.7 2.4 0.7 2.4 nstf Fall Time 0.7 2.4 0.7 2.4 0.7 2.4 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.21.90.70.72.21.90.70.72.21.9°C°Cnshttp://onsemi.com147

The MC10H189 is a Hex Inverter with a common Enable input. Thehex inverting function is provided when Enable is in the low–state.When Enable is in the high–state, all outputs are low.This MECL 10H part is a functional/pinout duplication of thestandard MECL 10K family part, with 100% improvement inpropagation delay and no increase in power–supply current.• Propagation Delay, 1.3 ns Typical Data–to–Output• Power Dissipation 180 mW Typ/Pkg (No Load)• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible9567101112LOGIC DIAGRAMXYVCC1AOUTBOUTCOUTAINBINCINVEEOUTDIPPIN ASSIGNMENT12345678234131415161514131211109VCC2FOUTEOUTDOUTFINEINDINCOMMONTRUTH TABLEInputs OutputX Y OUTL L HL H LH L LH H LV CC1 = Pin 1V CC2 = Pin 16V EE = Pin 8http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10H189L CDIP–16 25 Units/RailMC10H189P PDIP–16 25 Units/RailMC10H189FN PLCC–20 46 Units/Rail1161MC10H189LAWLYYWWMC10H189PAWLYYWW110H189AWLYYWWPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7148 Publication Order Number:MC10H189/D

MC10H189MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 46 – 42 – 46 mAIinH Input Current High – 495 – 310 – 310 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayEnableData0.70.7tr Rise Time 0.7 2.4 0.7 2.4 0.7 2.4 nstf Fall Time 0.7 2.4 0.7 2.4 0.7 2.4 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.2.21.90.70.72.21.90.70.72.31.9°C°Cnshttp://onsemi.com149

The MC10H209 is a Dual 4–5–input OR/NOR gate. This MECLpart is a functional/pinout duplication of the MECL III part MC1688.• Propagation Delay Average, 0.75 ns Typical• Power Dissipation 125 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–Compatible4567LOGIC DIAGRAM910141112 1513VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT32http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H209LAWLYYWWMC10H209PAWLYYWW110H209AWLYYWWVCC1116VCC2ORDERING INFORMATIONAOUT215BOUTDevice Package ShippingAOUT314BOUTMC10H209L CDIP–16 25 Units/RailAIN413BINMC10H209P PDIP–16 25 Units/RailAIN512BINMC10H209FN PLCC–20 46 Units/RailAIN611BINAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6150 Publication Order Number:MC10H209/D

MC10H209MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – – – 30 – – mAIinH Input Current High – 640 – 400 – 400 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.4 1.15 0.4 1.15 0.4 1.15 nstr Rise Time 0.4 1.5 0.4 1.5 0.4 1.6 nstf Fall Time 0.4 1.5 0.4 1.5 0.4 1.6 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.°C°Chttp://onsemi.com151

The MC10H210 is designed to drive up to six transmission linessimultan– eously. The multiple outputs of this device also allow thewire “OR”–ing of several levels of gating for minimization of gate andpackage count.The ability to control three parallel lines with minimum propagationdelay from a single point makes the MC10H210 particularly useful inclock distribution applications where minimum clock skew is desired.• Propagation Delay Average, 1.0 ns Typical• Power Dissipation, 160 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAM56710 9 121113234http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10H210LAWLYYWWMC10H210PAWLYYWW110H210AWLYYWW14VCC1 = PINS 1, 15VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONVCC1AOUT121615VCC2VCC1Device Package ShippingMC10H210L CDIP–16 25 Units/RailAOUT314BOUTMC10H210P PDIP–16 25 Units/RailAOUT413BOUTMC10H210FN PLCC–20 46 Units/RailAIN512BOUTAIN611BINAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6152 Publication Order Number:MC10H210/D

MC10H210MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 42 – 38 – 42 mAIinH Input Current High – 720 – 450 – 450 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.5 1.55 0.55 1.55 0.6 1.7 nstr Rise Time 0.75 1.8 0.75 1.9 0.8 2.0 nstf Fall Time 0.75 1.8 0.75 1.9 0.8 2.0 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Note: If crosstalk is present, double bypass capacitor to 0.2µF.°C°Chttp://onsemi.com153

The MC10H211 is designed to drive up to six transmission linessimultan– eously. The multiple outputs of this device also allow thewire “OR”–ing of several levels of gating for minimization of gate andpackage count.The ability to control three parallel lines with minimum propagationdelay from a single point makes the MC10H211 particularly useful inclock distribution applications where minimum clock skew is desired.• Propagation Delay, 1.0 ns Typical• Power Dissipation, 160 mW Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleLOGIC DIAGRAM567VCC1 = PINS 1, 15VCC2 = PIN 16VEE = PIN 81210 9 131411234http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H211LAWLYYWWMC10H211PAWLYYWW110H211AWLYYWWDIPPIN ASSIGNMENTORDERING INFORMATIONDevice Package ShippingVCC1116VCC2MC10H211L CDIP–16 25 Units/RailAOUT215VCC1MC10H211P PDIP–16 25 Units/RailAOUT314BOUTMC10H211FN PLCC–20 46 Units/RailAOUT413BOUTAIN512BOUTAIN611BINAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6154 Publication Order Number:MC10H211/D

MC10H211MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 42 – 38 – 42 mAIinH Input Current High – 720 – 450 – 450 µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpd Propagation Delay 0.7 1.6 0.7 1.6 0.7 1.7 nstr Rise Time 0.9 2.0 0.9 2.2 0.9 2.4 nstf Fall Time 0.9 2.0 0.9 2.2 0.9 2.4 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm ismaintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Note: If crosstalk is present, double bypass capacitor to 0.2µF.°C°Chttp://onsemi.com155

The MC10H330 is a Quad Bus Driver/Receiver with two–to–oneoutput multiplexers. These multiplexers have a common select andoutput enable. When disabled, (OE = high) the bus outputs go to –2.0V. Their output can be brought to a low state (VOL) by applying a highlevel to the receiver enable (RE = High). The parameters specified arewith 25 Ω loading on the bus drivers and 50 Ω loads on the receivers.• Propagation Delay, 1.5 ns Typical Data–to–Output• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleVCCXBUSWBUSDIPPIN ASSIGNMENT123242322VCC0YBUSZBUShttp://onsemi.comCDIP–24L SUFFIXCASE 758PDIP–24P SUFFIXCASE 724PLCC–28FN SUFFIXCASE 776241241MARKINGDIAGRAMSMC10H330LAWLYYWWMC10H330PAWLYYWW110H330AWLYYWWVCC0421OEX1X0W1567201918Y0Y1Z0A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekW0S891716Z1REORDERING INFORMATIONWIN1015ZINDevice Package ShippingXIN1114YINMC10H330L CDIP–24 15 Units/RailVEE1213VCC0MC10H330P PDIP–24 15 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.MC10H330FN PLCC–28 37 Units/RailNOTE:Each MECL 10H series circuit has been designedto meet the dc specifications shown in the test table,after thermal equilibrium has been established. Thecircuit is in a test socket or mounted on a printedcircuit board and transverse air flow greater than500 Ifpm is maintained. Receiver outputs areterminated through a 50–ohm resistor to –2.0 voltsdc. Bus outputs are terminated through a 25–ohmresistor to –2.0 volts dc.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6156 Publication Order Number:MC10H330/D

MC10H330MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 157 – 143 – 157 mAIinH Input Current HighPins 5–8, 17–20Pins 16, 21Pin 9–––667514475–––417321297–––417321297µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelaySelect–to–InputData–to–Bus OutputSelect–to–BusOutputOE–to–Bus OutputBus–to–InputRE–to–InputData–to–ReceiverInput1.80.51.00.80.80.51.3 4.0 1.3 4.0 1.3 4.0tr Rise Time 0.5 2.0 0.5 2.0 0.5 2.0 nstf Fall Time 0.5 2.0 0.5 2.0 0.5 2.0 ns5.32.03.22.22.12.21.80.51.00.80.80.55.32.03.22.22.12.21.80.51.00.80.80.55.32.03.22.22.42.2°C°Cnshttp://onsemi.com157

MC10H330LOGIC DIAGRAMOESW02198VCC0 = PIN 24VCC = PIN 1VCC0 = PIN 13VCC0 = PIN 4VEE = PIN 123WBUSW17WIN10X062XBUSX15XIN11Y02023YBUSY119YIN14Z01822ZBUSZ117ZIN15RE16MULTIPLEXER TRUTH TABLERECEIVER TRUTH TABLEOE S WBus XBus YBus ZBus RE Win Xin Yin ZinHLLXLH–2.0 VW0W1–2.0 VX0X1–2.0 VY0Y1–2.0 VZ0Z1HLLWBusLXBusLYBusLZBushttp://onsemi.com158

The MC10H332 is a Dual Bus Driver/Receiver with four–to–oneoutput multiplexers. These multiplexers have common selects andoutput enable. When disabled, (OE = high) the bus outputs go to –2.0V. The parameters specified are with 25 Ω loading on the bus driversand 50 Ω loads on the receivers.• Propagation Delay, 1.5 ns Typical Data–to–Output• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleVCCXBUSX0X1DIP & PLCCPIN ASSIGNMENT123420191817VCC02YBUSOEY0http://onsemi.comCDIP–20L SUFFIXCASE 732PDIP–20P SUFFIXCASE 738PLCC–20FN SUFFIXCASE 775201201MARKINGDIAGRAMSMC10H332LAWLYYWWMC10H332PAWLYYWW110H332AWLYYWWX2X3S0S1567816151413Y1Y2Y3REA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekXINVEE9101211YINVCC01Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.ORDERING INFORMATIONDevice Package ShippingMC10H332L CDIP–20 18 Units/RailMC10H332P PDIP–20 18 Units/RailNOTE:Each MECL 10H series circuit has been designedto meet the dc specifications shown in the test table,after thermal equilibrium has been established. Thecircuit is in a test socket or mounted on a printedcircuit board and transverse air flow greater than500 Ifpm is maintained. Receiver outputs areterminated through a 50–ohm resistor to –2.0 voltsdc. Bus outputs are terminated through a 25–ohmresistor to –2.0 volts dc.MC10H332FN PLCC–20 46 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6159 Publication Order Number:MC10H332/D

MC10H332MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note 1.)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 115 – 110 – 115 mAIinH Input Current HighPins 3,4,5,6,14,15,16,17Pins 7,8Pins 13, 18–––667437456–––417273285–––417273285µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayData–to–Bus OutputSelect–to–BusOutputOE–to–Bus OutputBus–to–ReceiverSelect–to–ReceiverRE–to–ReceiverData–to–Receiver0.80.80.80.81.80.81.3tr Rise Time 0.5 2.0 0.5 2.0 0.5 2.1 nstf Fall Time 0.5 2.0 0.5 2.0 0.5 2.1 ns1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts.3.03.42.42.14.52.24.00.80.80.80.81.80.81.33.03.42.42.14.52.24.00.80.80.80.81.80.81.33.23.82.62.45.02.54.5°C°Cnshttp://onsemi.com160

MC10H332MULTIPLEXER TRUTH TABLEOE S1 S0 XBus YBusHLLLLXLLHHXLHLH–2.0VX0X1X2X3–2.0VY0Y1Y2Y3RECEIVER TRUTHTABLERE Xin YinHLLXBusLYBusLOGIC DIAGRAMOE18X03X14X252XBUSX36S07S18Y017Y116Y21519YBUSY314XINREYIN91312VCC = PIN 1VCC01 = PIN 11VCC02 = PIN 20VEE = PIN 10http://onsemi.com161

The MC10H334 is a Quad Bus Driver/Receiver with transmit andreceiver latches. When disabled, (OE = high) the bus outputs will fallto –2.0 V. Data to be transmitted or received is passed through itsrespective latch when the respective latch enable (DLE and RLE) is ata low level. Information is latched on the positive transition of DLEand RLE. The parameters specified are with 25 Ω loading on the busdrivers and 50 Ω loads on the receivers.• Propagation Delay, 1.6 ns Typical Data–to–Output• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K–CompatibleDIP & PLCCPIN ASSIGNMENThttp://onsemi.comCDIP–20L SUFFIXCASE 732PDIP–20P SUFFIXCASE 738201201MARKINGDIAGRAMSMC10H334LAWLYYWWMC10H334PAWLYYWW1VCCBUS1BUS0123201918VCC03BUS2BUS3PLCC–20FN SUFFIXCASE 77510H334AWLYYWWVCC02D1D0456171615OED2D3A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDLE714RLER0813R3ORDERING INFORMATIONR1912R2Device Package ShippingVEE1011VCC02MC10H334L CDIP–20 18 Units/RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.MC10H334P PDIP–20 18 Units/RailMC10H334FN PLCC–20 46 Units/RailNOTE:Each MECL 10H series circuit has been designedto meet the dc specifications shown in the test table,after thermal equilibrium has been established. Thecircuit is in a test socket or mounted on a printedcircuit board and transverse air flow greater than500 Ifpm is maintained. Receiver outputs areterminated through a 50–ohm resistor to –2.0 voltsdc. Bus outputs are terminated through a 25–ohmresistor to –2.0 volts dc.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6162 Publication Order Number:MC10H334/D

MC10H334MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 0) –8.0 to 0 VdcVI Input Voltage (VCC = 0) 0 to VEE VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstgStorage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)–55 to +150–55 to +1650° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Power Supply Current – 161 – 161 – 161 mAIinH Input Current HighPins 5,6,15,16Pins 7,14Pin 17–––397460520–––273297357–––273297357µAIinL Input Current Low 0.5 – 0.5 – 0.3 – µAVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERStpdPropagation DelayData–to–Bus OutputDLE–to–Bus OutputOE–to–Bus OutputBus–to–R0RLE–to–R0Data–to–Receiver R00.51.00.50.50.51.0tr Rise Time 0.5 2.2 0.5 2.2 0.5 2.2 nstf Fall Time 0.5 2.2 0.5 2.2 0.5 2.2 ns2.52.72.51.92.13.80.51.00.50.50.51.02.52.72.51.92.13.80.51.00.50.50.51.02.52.72.51.92.13.8°C°Cnshttp://onsemi.com163

MC10H334LOGIC DIAGRAM17OE7DLEG6D0DQBUS035D1DQBUS1216D2DQBUS21915D3DQBUS31814RLEOUTPUTLATCHG8R0QD9R1QD12R2QD13R3QD10141120VEEVCCVCC01VCC02VCC03RECEIVERLATCHDRIVER TRUTH TABLED DLE OE Busn+1X X H –2.0 VD L L DRECEIVER TRUTH TABLEBus RLE Rn+1Bus L BusX H RnX H L Busnhttp://onsemi.com164

(+5 Vdc Power Supply Only)The MC10H350 is a member of Motorola’s 10H family of highperformance ECL logic. It consists of 4 translators with differentialinputs and TTL outputs. The 3–state outputs can be disabled byapplying a HIGH TTL logic level on the common OE input.The MC10H350 is designed to be used primarily in systemsincorporating both ECL and TTL logic operating off a common powersupply. The separate VCC power pins are not connected internally andthus isolate the noisy TTL VCC runs from the relatively quiet ECLVCC runs on the printed circuit board. The differential inputs allow theH350 to be used as an inverting or noninverting translator, or adifferential line receiver. The H350 can also drive CMOS with theaddition of a pullup resistor.• Propagation Delay, 3.5 ns Typical• MECL 10K–CompatibleLOGIC DIAGRAM9http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10H350LAWLYYWWMC10H350PAWLYYWW1345627PLCC–20FN SUFFIXCASE 77510H350AWLYYWW11121314VCC (+5.0 VDC) = PINS 1 AND 16GND = PIN 8DIP PIN ASSIGNMENT1015A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H350L CDIP–16 25 Units/RailECL VCC116TTL VCCMC10H350P PDIP–16 25 Units/RailAOUT215COUTMC10H350FN PLCC–20 46 Units/RailAIN314CINAIN413CINBIN512DINBIN611DINBOUT710DOUTGND89OEPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7165 Publication Order Number:MC10H350/D

MC10H350MAXIMUM RATINGSSymbol Characteristic Rating UnitVCC Power Supply (VEE = Gnd) 7.0 VdcTA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic– CeramicELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±5%) (See Note 1.)–55 to +150–55 to +165TA = 0°C to 75°CSymbol Characteristic Min Max UnitICC Power Supply Current TTLECL––2012mAIIHIINHIILIINLInput Current High Pin 9OthersInput Current Low Pin 9OthersVIH Input Voltage High Pin 9 2.0 – VdcVIL Input Voltage Low Pin 9 – 0.8 VdcVDIFF Differential Input Voltage (Note 1.)350 – mVPins 3–6, 11–14 (1)VCMVOHVOLIOSIOZHIOZLVoltage Common ModeOutput Voltage HighIOH = 3.0 mAOutput Voltage LowIOL = 20 mAShort Circuit CurrentVOUT = 0 VOutput Disable Current HighVOUT = 2.7 VOutput Disable Current LowVOUT = 0.5 VPins 3–6, 11–14––––2050–0.650°C°CµAmAµA2.8 VCC Vdc2.7 – Vdc– 0.5 Vdc–60 –150 mA– 50 µA– –50 µA1. Common mode input voltage to pins 3–4, 5–6, 11–12, 13–14 must be between the values of 2.8 V and 5.0 V. This common mode input voltagerange includes the differential input swing.2. For single ended use, apply 3.75 V (VBB) to either input depending on output polarity required. Signal level range to other input is 3.3 V to 4.2 V.3. Any unused gates should have the inverting inputs tied to VCC and the non–inverting inputs tied to ground to prevent output glitching.4. 1.0 V to 2.0 V w/50 pF into 500 ohms.*Positive Emitter Coupled Logichttp://onsemi.com166

MC10H350ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±5%) (See Notes 1 & 4)TA = 0°C to 75°CSymbol Characteristic Min Max UnitAC PARAMETERS (CL = 50 pF) (VCC = 5.0 ± 5%) (TA = 0°C to 75°C)tpd Propagation Delay Data (50% to 1.5V) 1.5 5.0 nstr Rise Time (Note 4.) 0.3 1.6 nstf Fall Time (Note 4.) 0.3 1.6 nstpdLZ Output Disable Time 2.06.0 nstpdHZ2.06.0tpdZLtpdZHOutput Enable Time 2.02.03–STATE SWITCHING WAVEFORMS8.08.0nsOE3–STATE OUTPUT LOW ENABLE ANDDISABLE TIMESOE3–STATE OUTPUT HIGH ENABLE ANDDISABLE TIMES1.5 V1.5 V1.5 V1.5 VTPZLTPLZTPZHTPHZVOUT1.5 VVOLVOUT1.5 V0.3 V VOH ≈ 3.5 V0.3 VTEST LOAD+7.0 V OPENTPZL, TPLZ, O, C,ALL OTHERD.U.T.500 Ω50 PF500 Ω*INCLUDES JIG AND PROBE CAPACITANCEApplication Note: Pin 9 is an OE and the 10H350 is disabled when OE is at V IH or higher.http://onsemi.com167

The MC10H351 is a quad translator for interfacing data between asaturated logic section and the PECL section of digital systems whenonly a +5.0 Vdc power supply is available. The MC10H351 hasTTL/NMOS compatible inputs and PECL complementaryopen–emitter outputs that allow use as an inverting/non–invertingtranslator or as a differential line driver. When the common strobeinput is at a low logic level, it forces all true outputs to the PECL lowlogic state (≈ +3.2 V) and all inverting outputs to the PECL high logicstate (≈ +4.1 V).The MC10H351 can also be used with the MC10H350 to transmitand receive TTL/NMOS information differentially via balancedtwisted pair lines.• Single +5.0 Power Supply• All VCC Pins Isolated On Chip• Differentially Drive Balanced Lines• tpd = 1.3 nsec TypicalB OUTB OUTN.C.A OUTA OUTVCCB INA INCOMMONSTROBEGNDLOGIC DIAGRAMB IN 7 12A IN 8 54D IN 12 1617C IN 14 19COMMONSTROBE918VCC (+5.0 VDC) = PINS 6, 11, 15, 20GND = PIN 10DIP PIN ASSIGNMENT1234567891020191817161514131211ECL VCCC OUTC OUTD OUTD OUTVCC 2C INN.C.D INB OUTB OUTA OUTA OUTD OUTD OUTC OUTC OUTTTL VCChttp://onsemi.comCDIP–20L SUFFIXCASE 732PDIP–20P SUFFIXCASE 738PLCC–20FN SUFFIXCASE 77520A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10H351L CDIP–20 18 Units/RailMC10H351P PDIP–20 18 Units/RailMC10H351FN PLCC–20 46 Units/Rail1201MC10H351LAWLYYWWMC10H351PAWLYYWW110H351AWLYYWWPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6168 Publication Order Number:MC10H351/D

MC10H351MAXIMUM RATINGSSymbol Characteristic Rating UnitVCC Power Supply 0 to +7.0 VdcVI Input Voltage (VCC = 5.0 V) 0 to VCC VdcIout Output Current – Continuous50mA– Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic–55 to +150°C– Ceramic–55 to +165ELECTRICAL CHARACTERISTICS (VCC = VCC1 = VCC2 = 5.0 V ± 5.0%)†0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitECL Power Supply – 50 – 45 – 50 mATTLCurrent– 20 – 15 – 20 mAIRIINHReverse CurrentPins 7, 8, 12, 14Pin 9––25100––2080––25100µAIFIINLV(BR)inVIVOHVOLForward CurrentPins 7, 8, 12, 14Pin 9Input BreakdownVoltageInput Clamp Voltage(Iin = –18 mA)High OutputVoltage (Note 1.)Low OutputVoltage (1)–––0.8–3.2–––0.6–2.4–––0.8–3.25.5 – 5.5 – 5.5 – Vdc– –1.5 – –1.5 – –1.5 Vdc3.98 4.16 4.02 4.19 4.08 4.27 Vdc3.05 3.37 3.05 3.37 3.05 3.37 VdcVIH High Input Voltage 2.0 – 2.0 – 2.0 – VdcVIL Low Input Voltage – 0.8 – 0.8 – 0.8 Vdc1. With VCC at 5.0 V. VOH/VOL change 1:1 with VCC.*Positive Emitter Coupled LogicAC PARAMETERS0° 25° 75°Symbol Characteristic Min Max Min Max Min Max Unittpd Propagation Delay (Note 2) 0.4 2.2 0.4 2.2 0.4 2.1 nstr Rise Time (20% to 80%) 0.4 1.9 0.4 2.0 0.4 2.1 nstf Fall Time (80% to 20%) 0.4 1.9 0.4 2.0 0.4 2.1 nsfmax Maximum Operating Frequency 150 – 150 – 150 – MHz2. Propagation delay is measured on this circuit from +1.5 volts on the input waveform to the 50% point on the output waveform.†Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.Outputs are terminated through a 50–ohm resistor to VCC –2.0 Vdc.mAhttp://onsemi.com169

The MC10H352 is a quad translator for interfacing data between aCMOS logic section and the PECL section of digital systems whenonly a +5.0 Vdc power supply is available. The MC10H352 hasCMOS compatible inputs and PECL complementary open–emitteroutputs that allow use as an inverting/non–inverting translator or as adifferential line driver. When the common strobe input is at a low logiclevel, it forces all true outputs to the PECL low logic state (≈ +3.2 V)and all inverting outputs to the PECL high logic state (≈ +4.1 V).The MC10H352 can also be used with the MC10H350 to transmitand receive CMOS information differentially via balanced twistedpair lines.• Single +5.0 V Power Supply• All VCC Pins Isolated On Chip• Differentially Drive Balanced Lines• tpd = 1.3 nsec TypicalLOGIC DIAGRAMB IN 7 1 B OUT2 B OUTA IN 8 5 A OUT4 A OUTD IN 12 16 D OUT17 D OUTC IN 14 19 C OUTCOMMON 918 C OUTSTROBEVCC (+5.0 VDC) = PINS 6, 11, 15, 20GND = PIN 10B OUTB OUTN.C.A OUTDIP PIN ASSIGNMENT123420191817ECL VCCC OUTC OUTD OUThttp://onsemi.comCDIP–20L SUFFIXCASE 732PDIP–20P SUFFIXCASE 738PLCC–20FN SUFFIXCASE 77520ORDERING INFORMATIONDevice Package ShippingMC10H352L CDIP–20 18 Units/RailMC10H352P PDIP–20 18 Units/RailMC10H352FN PLCC–20 46 Units/Rail120A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10H352LAWLYYWWMC10H352PAWLYYWW110H352AWLYYWWA OUT516D OUTVCC615VCC 2B IN714C INA INCOMMONSTROBEGND8910131211N.C.D INCMOS VCCPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6170 Publication Order Number:MC10H352/D

MC10H352MAXIMUM RATINGSSymbol Characteristic Rating UnitVCC Power Supply 0 to +7.0 VdcVI Input Voltage (VCC = 5.0 V) 0 to VCC VdcIout Output Current — Continuous50mA— Surge100TA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range — Plastic–55 to +150°C— Ceramic–55 to +165ELECTRICAL CHARACTERISTICS (VCC = VCC1 = VCC2 = 5.0 V ± 5.0%)†0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitECL Power Supply — 50 — 45 — 50 mATTLCurrent— 20 — 15 — 20 mAIR Reverse CurrentPins 7, 8, 12, 14Pin 9——25100——2080——25100µAIFV(BR)inVIVOHVOLForward CurrentPins 7, 8, 12, 14Pin 9Input VoltageBreakdownInput Clamp Voltage(Iin = –18 mA)High OutputVoltage (Note 1.)Low OutputVoltage (Note 1.)——–0.8–3.2——–0.6–2.4——–0.8–3.25.5 — 5.5 — 5.5 — Vdc— –1.5 — –1.5 — –1.5 Vdc3.98 4.16 4.02 4.19 4.08 4.27 Vdc3.05 3.37 3.05 3.37 3.05 3.37 VdcVIH High Input Voltage 3.15 — 3.15 — 3.15 — VdcVIL Low Input Voltage — 1.5 — 1.5 — 1.5 Vdc1. With VCC at 5.0 V. VOH/VOL change 1:1 with VCC.**Positive Emitter Coupled LogicAC PARAMETERS0° 25° 75°Symbol Characteristic Min Max Min Max Min Max Unittpd Propagation Delay (Note 2.) 0.4 1.9 0.4 2.0 0.4 2.1 nstr Rise Time (20% to 80%) 0.4 1.9 0.4 2.0 0.4 2.1 nstf Fall Time (80% to 20%) 0.4 1.9 0.4 2.0 0.4 2.1 nsfmax Maximum Operating Frequency 150 — 150 — 150 — MHz2. Propagation delay is measured on this circuit from VCC/2 on the input waveform to the 50% point on the output waveform.†Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.Outputs are terminated through a 50–ohm resistor to VCC – 2.0 Vdc.mAhttp://onsemi.com171

The MC10H424 is a Quad TTL–to–ECL translator with an ECLstrobe. Power supply requirements are ground, +5.0 volts, and –5.2volts.• Propagation Delay, 1.5 ns Typical• Improved Noise Margin 150 mV (Over Operating Voltage andTemperature Range)• Voltage Compensated• MECL 10K – CompatibleBOUTAOUTBOUTAOUTAINCOMMONSTROBEBINLOGIC DIAGRAM5 4627 3110 121511 1314GND = PIN 16VCC (+5.0 VDC) = PIN 9VEE (–5.2 VDC) = PIN 8DIPPIN ASSIGNMENT123456716151413121110GNDCOUTDOUTDOUTCOUTDINCINhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10H424L CDIP–16 25 Units/RailMC10H424P PDIP–16 25 Units/RailMC10H424FN PLCC–20 46 Units/Rail1161MC10H424LAWLYYWWMC10H424PAWLYYWW110H424AWLYYWWVEE89VCCPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6172 Publication Order Number:MC10H424/D

MC10H424MAXIMUM RATINGSSymbol Characteristic Rating UnitVEE Power Supply (VCC = 5.0 V) –8.0 to 0 VdcVCC Power Supply (VEE = – 5.2 V) 0 to +7.0 VdcVI Input Voltage (ECL) 0 to VEE VdcVI Input Voltage (TTL) 0 to VCC VdcIout Output Current – Continuous– Surge50100mATA Operating Temperature Range 0 to +75 °CTstg Storage Temperature Range – Plastic–55 to +150°C– Ceramic–55 to +165ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ± 5%, VCC = 5.0 V ± 5.0%)0° 25° 75°Symbol Characteristic Min Max Min Max Min Max UnitIE Negative Power Supply– 72 – 66 – 72 mAdcDrain CurrentICCH Positive Power Supply – 16 – 16 – 18 mAdcICCLDrain Current– 25 – 25 – 25 mAdcIR Reverse Current Pin5,7,10,11– 50 – 50 – 50 µAdcIFForward Current Pin5,7,10,11– –3.2 – –3.2 – –3.2 mAdcIinH Input HIGH Current Pin 6 – 450 – 310 – 310 µAdcIinL Input LOW Current Pin 6 0.5 – 0.5 – 0.3 – µAdcV(BR)in Input Breakdown Voltage 5.5 – 5.5 – 5.5 – VdcVI Input Clamp Voltage – –1.5 – –1.5 – –1.5 VdcVOH High Output Voltage –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 VdcVOL Low Output Voltage –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 VdcVIH High Input Voltage Pin2.0 – 2.0 – +2.0 – Vdc5,7,10,11VILLow Input Voltage Pin5,7,10,11– 0.8 – 0.8 – 0.8 VdcVIH High Input Voltage Pin 6 –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 VdcVIL Low Input Voltage Pin 6 –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 VdcAC PARAMETERSPropagationDelaytpdData0.5Strobe0.52.22.20.50.52.32.30.50.52.42.4Rise Time tr 0.5 2.0 0.5 2.0 0.5 2.2 nsFall Time tf 0.5 2.0 0.5 2.0 0.5 2.2 nsnsNOTE:Each MECL 10H series circuit has been designed to meet the dcspecifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuitboard and transverse air flow greater than 500 Ifpm is maintained. Outputsare terminated through a 50–ohm resistor to –2.1 volts.APPLICATIONS INFORMATIONThe MC10H424 has TTL–compatible inputs, an ECLstrobe and MECL complementary open–emitter outputs thatallow use as an inverting/non–inverting translator or as adifferential line driver. When the common strobe input is atthe low–logic level, it forces all true outputs to a MECLlow–logic state and all inverting outputs to a MECLhigh–logic state.An advantage of this device is that TTL–level informationcan be transmitted differentially, via balanced twisted pairlines, to MECL equipment, where the signal can be receivedby the MC10H115 or MC10H116 differential line receivers.http://onsemi.com173

The MC10H/100H600 is a 9–bit, dual supply TTL to ECLtranslator. Devices in the Motorola 9–bit translator series utilize the28–lead PLCC for optimal power pinning, signal flow–through andelectrical performance.The H600 features both ECL and TTL logic enable controls formaximum flexibility.The 10H version is compatible with MECL 10H ECL logic levels.The 100H version is compatible with 100K levels.• 9–Bit Ideal for Byte–Parity Applications• Flow–Through Configuration• Extra TTL and ECL Power/Ground Pins to Minimize SwitchingNoise• ECL and TTL Enable Inputs• Dual Supply• 3.5 ns Max D to Q• PNP TTL Inputs for Low Loading• Choice of ECL Compatibility: MECL 10H (10Hxxx) or 100K(100Hxxx)LOGIC SYMBOLENECLENTTLD0D1D2Q0Q1Q2PIN NAMESPINGNDVCCEVCCOVCCTVEED0–D8Q0 –Q8ENECLENTTLhttp://onsemi.comPLCC–28FN SUFFIXCASE 776MARKINGDIAGRAM10H600AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekPinout: 28–Lead PLCC (Top View)1FUNCTIONTTL Ground (0 V)ECL VCC (0 V)ECL VCC (0 V) — OutputsTTL Supply (+ 5.0 V)ECL Supply (– 5.2/–4.5 V)Data Inputs (TTL)Data Outputs (ECL)Enable Control (ECL)Enable Control (TTL)TTLD3D4Q3Q4ECLD6D72627D5 D4 V CCT D3 D2 D1 D025 24 23 22 21 20 191817Q0Q1TRUTH TABLEENECLHHXXLENTTLXXHHLDHLHLXQHLHLLD5D6D7D8Q5Q6Q7Q8D8GNDENTTLNCENECL2823416151413125 6 7 8 9 10 11Q8 Q7 V CCO Q6 V EE Q5 Q4V CCEV CCOQ2V CCOQ3ORDERING INFORMATIONDevice Package ShippingMC10H600FN PLCC–28 37 Units/RailMC100H600FN PLCC–28 37 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6174 Publication Order Number:MC10H600/D

MC10H600, MC100H600DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditionPower Supply CurrentIEE ECL 10H100H–125–122–125–123–125–132mAICCHICCLTTL 485048504850mAAC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = –4.2 V to – 5.5 V (100H version)0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditiontPLHtPHLPropagation Delayto OutputtD 1.4 3.0 1.5 3.2 1.7 3.5 ns 50 Ω to – 2.0 VENECL/ENTTL1.8 3.7 1.9 3.9 2.0 4.1 ns 50 Ω to – 2.0 VtRtFOutput Rise/Fall Time20%–80%0.5 1.5 0.5 1.5 0.5 1.5 ns 50 Ω to – 2.0 V10H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5%0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIIHIILInput HIGH CurrentInput LOW Current 0.52250.51450.5145 µAµAVIHVILInput HIGH VoltageInput LOW Voltage–1170–1950–840–1480–1130–1950–810–1480–1070–1950–735–1450mVVOHVOLOutput HIGH VoltageOutput LOW Voltage–1020–1950–840–1630–980–1950–810–1630–920–1950–735–1600mV50 Ω to – 2.0 V100H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 4.2 V to – 5.5 V0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIIHIILInput HIGH CurrentInput LOW Current 0.52250.51450.5145 µAµAVIHVILInput HIGH VoltageInput LOW Voltage–1165–1810–880–1475–1165–1810–880–1475–1165–1810–880–1475mVVOHVOLOutput HIGH VoltageOutput LOW Voltage–1025–1810–880–1620–1025–1810–880–1620–1025–1810–880–1620mV50 Ω to – 2.0 VTTL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage2.00.82.00.82.00.8VVIIH Input HIGH Current 201002010020100µA VIN = 2.7 VVIN = 7.0 VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 VVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18 mAhttp://onsemi.com175

The MC10H/100H601 is a 9–bit, dual supply ECL to TTLtranslator. Devices in the Motorola 9–bit translator series utilize the28–lead PLCC for optimal power pinning, signal flow–through andelectrical performance.The devices feature a 48 mA TTL output stage, and ACperformance is specified into both a 50 pF and 200 pF loadcapacitance. For the 3–state output disable, both ECL and TTL controlinputs are provided, allowing maximum design flexibility.The 10H version is compatible with MECL 10H ECL logic levels.The 100H version is compatible with 100K levels.• 9–Bit Ideal for Byte–Parity Applications• 3–State TTL Outputs• Flow–Through Configuration• Extra TTL and ECL Power Pins to Minimize Switching Noise• ECL and TTL 3–State Control Inputs• Dual Supply• 4.8 ns Max Delay into 50 pF, 9.6 ns into 200 pF (all outputsswitching)• PNP TTL Inputs for Low LoadingOEECLOETTLD0D1Q0Q1TRUTH TABLEOEECLLLHXOETTLLLXHDLHXXQLHZZPLCC–28FN SUFFIXCASE 776PIN NAMESPINGNDVCCEVCCTVEED0–D8Q0 –Q8OEECLOETTLhttp://onsemi.comMARKINGDIAGRAMA = Assembly LocationWL = Wafer LotYY = YearWW = Work Week110H601AWLYYWWFUNCTIONTTL Ground (0 V)ECL VCC (0 V)TTL Supply (+ 5.0 V)ECL Supply (– 5.2/–4.5 V)Data Inputs (ECL)Data Outputs (TTL)3–State Control (ECL)3–State Control (TTL)Q5 GND V CCT Q6 GND Q7 Q8D2Q2Q42625 24 23 22 21 20 1918D8D3Q3Q3V CCT27281716D7V CCEECLD4Q4TTLQ2GND21514D6D5D5Q5Q1Q0345 6 7 8 9 10 111312D4D3D6Q6OETTL NC OEECL V EE D0 D1 D2D7D8Q7Q8Pinout: 28–Lead PLCC (Top View)ORDERING INFORMATIONDevice Package ShippingFigure 1. Logic DiagramMC10H601FN PLCC–28 37 Units/RailMC100H601FN PLCC–28 37 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 8176 Publication Order Number:MC10H601/D

MC10H601, MC100H60110H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5%0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIEE Power Supply Current –51 –51 –51 mAIINH Input HIGH Current225145145 µAIINL Input LOW Current 0.50.50.5µAVIHVILInput HIGH VoltageInput LOW Voltage–1170–1950–840–1480–1130–1950–810–1480–1060–1950–720–1445mV100H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 4.2 V to – 5.5 V0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIEE Power Supply Current –51 –51 –53 mAIINHIINLVIHVILInput HIGH CurrentInput LOW Current 0.5Input HIGH VoltageInput LOW Voltage–1165–1810TTL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%;225–880–14750.5–1165–1810145–880–14750.5–1165–1810VEE = – 5.2 V ± 5% (10H version);VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 85°C145 µAµA–880–1475Symbol Parameter Min Max Min Max Min Max Unit ConditionICCH Power Supply Current 110 110 110 mAICCL 110 110 110ICCZ Power Supply Current 105 105 105IIH Input HIGH Current 201002010020100mVµA VIN = 2.7 VVIN = 7.0 VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 VIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0 VIOZHIOZLOutput Disable Current HIGHOutput Disable Current LOW –50VIHTVILTInput HIGH VoltageInput LOW Voltage2.0VOHT Output HIGH Voltage 2.52.0500.8–502.02.52.0500.8–502.02.52.050 µA VOUT = 2.7 VVOUT = 0.5 V0.8VVIOH = – 3.0 mAIOH = –15 mAVOLT Output LOW Voltage 0.55 0.55 0.55 V IOL = 48 mAVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18 mAAC CHARACTERISTICS: VCCT = 5.0 V ± 10%;VEE = – 5.2 V ± 5% (10H version);VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditiontPLHtPHLtPLZtPHZtPLZtPHZtPZLtPZHtPZLtPZHtRtFPropagation Delayto Output1.73.4Output Disable Time OEECL 3.75.4OETTL 4.37.0Output Enable Time OEECL 3.55.0Output Rise/Fall Time1.0 V –2.0 VOETTL 4.26.04.89.66.5137.5156.0127.0141.23.01.73.43.75.44.37.03.55.04.26.04.89.66.5137.5156.0127.0141.23.01.73.43.75.44.37.03.55.04.26.04.89.66.5137.5156.0127.0141.23.0nsnsnsnsnsnsnsnsnsnsnsnsCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFhttp://onsemi.com177

The MC10H/100H602 is a 9–bit, dual supply TTL to ECL translatorwith latch. Devices in the Motorola 9–bit translator series utilize the28–lead PLCC for optimal power pinning, signal flow–through andelectrical performance.The H602 features D–type latches. Latching is controlled by LatchEnable (LEN), while the Master Reset input resets the latches. Apost–latch logic enable is also provided (ENECL), allowing control ofthe output state without destroying latch data. All control inputs areECL level.The 10H version is compatible with MECL 10H ECL logic levels.The 100H version is compatible with 100K levels.• 9–Bit Ideal for Byte–Parity Applications• Flow–Through Configuration• Extra TTL and ECL Power/Ground Pins to Minimize SwitchingNoise• Dual Supply• 3.5 ns Max D to Q• PNP TTL Inputs for Low LoadingENECLD0D1DQENDQENLOGIC SYMBOLQ0Q1PLCC–28FN SUFFIXCASE 776PIN NAMESPINGNDVCCEVCCOVCCTVEED0–D8Q0 –Q8ENECLLENMRhttp://onsemi.comMARKINGDIAGRAM10H602AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1FUNCTIONTTL Ground (0 V)ECL VCC (0 V)ECL VCC (0 V) — OutputsTTL Supply (+ 5.0 V)ECL Supply (– 5.2/–4.5 V)Data Inputs (TTL)Data Outputs (ECL)Enable Control (ECL)Latch Enable (ECL)Master Reset (ECL)D2D3DQENDQENQ2Q3Pinout: 28–Lead PLCC (Top View)D5 D4 V CCT D3 D2 D1 D025 24 23 22 21 20 19D6 2618 Q0TTLD4DQENQ4ECLD7D827281716Q1V CCED5D6D7D8LENMRDQENDQENDQENDQENQ5Q6Q7Q8TRUTH TABLEDLHXXXLENLLHXXMRLLLHXENECLHHHHLQLHQ0LLGND15 V CCOMR 214 Q2LEN 313 V CCOENECL 412 Q35 6 7 8 9 10 11Q8 Q7 V CCO Q6 V EEQ5 Q4ORDERING INFORMATIONDevice Package ShippingMC10H602FN PLCC–28 37 Units/RailMC100H602FN PLCC–28 37 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6178 Publication Order Number:MC10H602/D

MC10H602, MC100H602DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditionPower Supply CurrentIEE ECL 10H100HICCHICCL–125–122TTL 4850AC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to – 5.5 V (100H version)–125–12348500°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditiontPLHtPHLPropagation Delayto OutputDLENMRENECL1.42.02.01.63.03.43.43.21.52.12.11.73.23.53.53.31.72.42.51.8–125–132ts Set–Up Time, D to LEN 2.0 2.0 2.0 nsth Hold Time, D to LEN 1.0 1.0 1.0 nstw(L) LEN Pulse Width, LOW 2.0 2.0 2.0 nstRtFOutput Rise/Fall Time20%–80%48503.53.73.93.70.5 1.5 0.5 1.5 0.5 1.5 ns10H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5%0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIINHIINLVIHVILVOHVOLInput HIGH CurrentInput LOW Current 0.5Input HIGH VoltageInput LOW VoltageOutput HIGH VoltageOutput LOW Voltage–1170–1950–1020–1950225–840–1480–840–16300.5–1130–1950–980–1950145–810–1480–810–1630100H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 4.2 V to – 5.5 V0.5–1070–1950–920–19500°C 25°C 75°CmAmAns145 µAµA–735–1450–735–1600mVmV50 Ω to – 2.0 VSymbol Parameter Min Max Min Max Min Max Unit ConditionIINHIINLVIHVILVOHVOLInput HIGH CurrentInput LOW Current 0.5Input HIGH VoltageInput LOW VoltageOutput HIGH VoltageOutput LOW Voltage–1165–1810–1025–1810225–880–1475–880–16200.5–1165–1810–1025–1810145–880–1475–880–16200.5–1165–1810–1025–1810145 µAµA–880–1475–880–1620mVmV50 Ω to – 2.0 VTTL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 75°CSymbol Parameter Min Max Min Max Min Max Unit ConditionVIH Input HIGH Voltage2.0VIL Input LOW Voltage0.8IIH Input HIGH Current 201002.00.8201002.00.820100VVµA VIN = 2.7 VVIN = 7.0 VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 VVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18 mAhttp://onsemi.com179

The MC10H/100H603 is a 9–bit, dual supply ECL to TTLtranslator. Devices in the Motorola 9–bit translator series utilize the28–lead PLCC for optimal power pinning, signal flow–through andelectrical performance.The devices feature a 48 mA TTL output stage, and ACperformance is specified into both a 50 pF and 200 pF loadcapacitance. Latching is controlled by Latch Enable (LEN), andMaster Reset (MR) resets the latches. A HIGH on OEECL sends theoutputs into the high impedance state. All control inputs are ECLlevel.The 10H version is compatible with MECL 10H ECL logic levels.The 100H version is compatible with 100K levels.• 9–Bit Ideal for Byte–Parity Applications• 3–State TTL Outputs• Flow–Through Configuration• Extra TTL and ECL Power Pins to Minimize Switching Noise• Dual Supply• 6.0 ns Max Delay into 50 pF, 12 ns into 200 pF (all outputsswitching)• PNP TTL Inputs for Low LoadingECLOEECLD0D1D2D3D4D5DQENDQENDQENDQENDQENDQENQ0Q1Q2Q3Q4Q5TRUTH TABLEDLHXXXTTLLENLLHXXMRLLLHXOEECLLLLLHQLHQ0LZPLCC–28FN SUFFIXCASE 776PIN NAMESPINGNDVCCEVCCTVEED0–D8Q0 –Q8OEECLLENMRQ4Q3V CCTQ2GNDQ1Q0262728234http://onsemi.comMARKINGDIAGRAM10H603AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1FUNCTIONTTL Ground (0 V)ECL VCC (0 V)TTL Supply (+ 5.0 V)ECL Supply (– 5.2/–4.5 V)Data Inputs (ECL)Data Outputs (TTL)3-State Control (ECL)Latch Enable (ECL)Master Reset (ECL)Q5 GND V CCT Q6 GND Q7 Q825 24 23 22 21 20 19125 6 7 8 9 10 11181716151413D8D7V CCED6D5D4D3D6DQENQ6MR LEN OEECL V EE D0 D1 D2Figure 1. 28–Lead Pinout (Top View)D7D8LENMRDQENDQENFigure 2. Logic DiagramQ7Q8ORDERING INFORMATIONDevice Package ShippingMC10H603FN PLCC–28 37 Units/RailMC100H603FN PLCC–28 37 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7180 Publication Order Number:MC10H603/D

MC10H603, MC100H60310H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5%0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIEE Power Supply Current –64 –64 –64 mAIINH Input HIGH Current225145145 µAIINL Input LOW Current 0.50.50.5µAVIHVILInput HIGH VoltageInput LOW Voltage–1170–1950–840–1480–1130–1950–810–1480–1060–1950–720–1445mV100H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 4.2 V to – 5.5 V0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIEE Power Supply Current –63 –64 –68 mAIINHIINLVIHVILInput HIGH CurrentInput LOW Current 0.5Input HIGH VoltageInput LOW Voltage–1165–1810TTL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%;225–880–14750.5–1165–1810145–880–14750.5–1165–1810VEE = – 5.2 V ± 5% (10H version);VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 85°C145 µAµA–880–1475Symbol Parameter Min Max Min Max Min Max Unit ConditionICCH Power Supply Current 110 110 110 mAICCL 110 110 110ICCZ Power Supply Current 110 110 110IOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0 VIOZHIOZLOutput Disable Current HIGHOutput Disable Current LOWVOHT Output HIGH Voltage 2.52.050–502.52.050–502.52.050–50mVµA VOUT = 2.7 VVOUT = 0.5 VVIOH = – 3.0 mAIOH = –15 mAVOLT Output LOW Voltage 0.55 0.55 0.55 V IOL = 48 mAAC CHARACTERISTICS: VCCT = 5.0 V ± 10%;VEE = – 5.2 V ± 5% (10H version);VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditiontPLHtPHLtPLZtPHZtPZLtPZHPropagation Delayto OutputD 3.06.4LEN 3.57.0MR 3.06.0Output Disable Time 2.54.2Output Enable Time 2.04.0ts Setup Time D to LEN 1.5 1.5 1.5 nsth Hold Time D to LEN 0.8 0.8 0.8 nstw(L) LEN Pulse Width, LOW 2.0 2.0 2.0 nstRtFOutput Rise/Fall Time1.0 V –2.0 V0.20.26.0126.5136.0126.5135.0101.23.03.06.43.57.03.06.02.54.22.04.00.20.26.0126.5136.0126.5135.0101.23.03.06.43.57.03.06.02.54.22.04.00.20.26.0126.5136.0126.5135.0101.23.0nsnsnsnsnsnsnsnsnsnsnsnsCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFCL = 50 pFCL = 200 pFhttp://onsemi.com181

The MC10H/100H604 is a 6–bit, registered, dual supply TTL toECL translator. The device features differential ECL outputs as wellas a choice between either a differential ECL clock input or a TTLclock input. The asynchronous master reset control is an ECL levelinput..With its differential ECL outputs and TTL inputs the H604 device isideally suited for the transmit function of a HPPI bus typeboard–to–board interface application. The on chip registers simplifythe task of synchronizing the data between the two boards.The device is available in either ECL standard: the 10H device iscompatible with MECL 10KH logic levels while the 100H device iscompatible with 100K logic levels.• Differential 50Ω ECL Outputs• Choice Between Differential ECL or TTL Clock Input• Dual Power Supply• Multiple Power and Ground Pins to Minimize Noise• Specified Within–Device SkewDnLOGIC SYMBOL1 OF 6 BITSDCLKRQQnQnPLCC–28FN SUFFIXCASE 776PIN NAMESPIND0–D5CLK, CLKTCLKMRQ0–Q5Q0–Q5VCCEVCCTVEEhttp://onsemi.comMARKINGDIAGRAM10H604AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekPinout: 28–Lead PLCC (Top View)1FUNCTIONTTL Data InputsDifferential ECL Clock InputTTL Clock InputECL Master Reset InputTrue ECL OutputsInverted ECL OutputsECL VCC (0V)TTL VCC (+5.0V)ECL VEE (–5.2V)D1 D2 V CCT D3 D4 D5 V CCED02625 24 23 22 21 20 1918Q5CLKCLKTCLK*TCLKV BBCLK2728171615Q5Q4Q4*MRVBB1. When using MECL inputs, TCLK must be tied to ground (0V).2. When using only one MECL input, the unused MECL input must be tiedto VBB, and TCLK must be tied to ground (0V).3. When using TCLK, both MECL inputs must be tied to VEE (–5.2V).TRUTH TABLEDnLHXMRLLHTCLK/CLKZZXZ = LOW to HIGH TransitionQn+1LHLCLK 214 V CCEMR 313 Q3V CCE 412 Q35 6 7 8 9 10 11Q0 Q0 V EE Q1 Q1 Q2 Q2ORDERING INFORMATIONDevice Package ShippingMC10H604FN PLCC–28 37 Units/RailMC100H604FN PLCC–28 37 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 2182 Publication Order Number:MC10H604/D

MC10H604, MC100H604DC CHARACTERISTICS: VEE = VEE(Min) to VEE(Max); VCCE = GND; VCCT = 5.0V +10%0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIEE ECL Power Supply Current 10H100HICCHICCL130130TTL Power Supply Current 354513014010H ECL DC CHARACTERISTICS: VCCT = +5.0 V ± 10%; VEE = – 5.20 V ±5%35450°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditionIINHIINLVIHVILInput HIGH CurrentInput LOW Current 0.5Input HIGH VoltageInput LOW Voltage–1170–1950225–840–14800.5–1130–1950145–810–14800.5–1060–19501301503545mAmA145 µAµA–720–1480VBB Output Bias Voltage –1400 –1290 –1370 –1270 –1330 –1210 mVVOHVOLOutput HIGH VoltageOutput LOW Voltage–1020–1950–840–1630–980–1950–810–1630100H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 4.2 V to – 5.5 V–910–19500°C 25°C 85°C–720–1595mVmV50 Ω to – 2.0 VSymbol Parameter Min Max Min Max Min Max Unit ConditionIINHIINLVIHVILInput HIGH CurrentInput LOW Current 0.5Input HIGH VoltageInput LOW Voltage–1165–1810225–880–14750.5–1165–1810145–880–14750.5–1165–1810145 µAµA–880–1475VBB Output Bias Voltage –1400 –1280 –1400 –1280 –1400 –1280 mVVOHVOLOutput HIGH VoltageOutput LOW Voltage–1025–1810–880–1620–1025–1810–880–1620–1025–1810–880–1620mVmV50 Ω to – 2.0 VTTL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 85°CSymbol Parameter Min Max Min Max Min Max Unit ConditionVIH Input HIGH Voltage2.0VIL Input LOW Voltage0.8IIH Input HIGH Current 201002.00.8201002.00.820100VVµA VIN = 2.7 VVIN = 7.0 VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 VVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18 mAAC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to – 5.5 V (100H version)0°C 25°C 85°CSymbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit ConditiontPLHtPHLPropagation DelayCLK to Qto Output TCLK to QMR to Q1.52.01.53.54.04.01.52.01.53.54.04.01.52.01.53.54.04.0ns 50Ω to – 2.0Vts Setup Time 1.5 0.5 1.5 0.5 1.5 0.5 ns 50Ω to – 2.0VtH Hold Time 1.5 0.5 1.5 0.5 1.5 0.5 ns 50Ω to – 2.0VtPWMinimum Pulse WidthCLK, MR 1.0 1.0 1.0VPP Minimum Input Swing 150 mVtrtfRise/Fall Times0.3 1.0 2.0 0.3 1.0 2.0 0.3 1.0 2.0ns 50Ω to – 2.0Vns 20% – 80%http://onsemi.com183

The MC10/100H605 is a 6–bit, registered, dual supply ECL to TTLtranslator. The device features differential ECL inputs for both dataand clock. The TTL outputs feature balanced 24mA sink/sourcecapabilities for driving transmission lines.With its differential ECL inputs and TTL outputs the H605 device isideally suited for the receive function of a HPPI bus typeboard–to–board interface application. The on chip registers simplifythe task of synchronizing the data between the two boards.A VBB reference voltage is supplied for use with single–ended dataor clock. For single–ended applications the VBB output should beconnected to the “bar” inputs (Dn or CLK) and bypassed to ground viaa 0.01µF capacitor. To minimize the skew of the device differentialclocks should be used.The ECL level Master Reset pin is asynchronous and common to allflip–flops. A “HIGH” on the Master Reset forces the Q outputs“LOW”.The device is available in either ECL standard: the 10H device iscompatible with MECL 10H logic levels while the 100H device iscompatible with 100K logic levels.• Differential ECL Data and Clock Inputs• 24mA Sink, 24mA Source TTL Outputs• Dual Power Supply• Multiple Power and Ground Pins to Minimize Noise• 2.0ns Part–to–Part SkewPLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAM10H605AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H605FN PLCC–28 37 Units/RailMC100H605FN PLCC–28 37 Units/Rail1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 4184 Publication Order Number:MC10H605/D

MC10H605, MC100H605LOGIC DIAGRAMPinout: 28–Lead PLCC (Top View)1 OF 6 BITSQ226Q3 V CCT Q4 GND Q5 V CCT MR25 24 23 22 21 20 1918D5DnDnDQQnQ1Q027281716D5D4GND15D4CLK214V CCECLKRCLKV BB345 6 7 8 9 10 111312D3D3D0 D0 V EE D1 D1 D2 D2CLKCLKPIN NAMESMRVBBTRUTH TABLEDnLHXMRLLHTCLK/CLKZZXQn+1LHLPIND0–D5D0–D5CLK, CLKMRQ0–Q5VCCEVCCTGNDVEEFUNCTIONTrue ECL Data InputsInverted ECL Data InputsDifferential ECL Clock InputECL Master Reset InputTTL OutputsECL VCCTTL VCCTTL GroundECL VEEZ = LOW to HIGH Transitionhttp://onsemi.com185

MC10H605, MC100H60510H ECL DC CHARACTERISTICS (VCCT = +5.0V ±10%; VEE = –5.20V ±5%)0°C 25°C 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditionIEE Supply Current 63 75 63 75 61 75 mAIINH Input HIgh Current 225 145 145 µAIINL Input Low Current 0.5 0.5 0.5 µAVIH Input High Voltage –1170 –840 –1130 –810 –1060 –720 mVVIL Input Low Voltage –1950 –1480 –1950 –1480 –1950 –1480 mVVBB Output Bias Voltage –1400 –1280 –1370 –1270 –1330 –1210 mVVDiff Input Differential Voltage 150 150 150 mVVmaxCMRRVminCMRRInput Common ModeReject RangeInput Common ModeReject Range–2800–3000–33000 0 0 mV–2800–3000–3300100H ECL DC CHARACTERISTICS (VCCT = +5.0V ±5%; VEE = –4.2V to 5.5V)–2800–3000–33000°C 25°C 85°CmV VEE = –4.94VEE = –5.20VEE = –5.46Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditionIEE Supply Current 65 75 65 75 70 85 mAIINH Input HIgh Current 225 145 145 µAIINL Input Low Current 0.5 0.5 0.5 µAVIH Input High Voltage –1165 –880 –1165 –880 –1165 –880 mVVIL Input Low Voltage –1810 –1475 –1810 –1475 –1810 –1475 mVVBB Reference Voltage –1400 –1280 –1400 –1280 –1400 –1200 mVVDiff Input Differential Voltage 150 150 150 mVVmaxCMRRVminCMRRInput Common ModeReject RangeInput Common ModeReject Range–2000–2200–2400* NOTE: DO NOT short the ECL inputs to the TTL VCC.0 0 0 mV–2000–2200–2400–2000–2200–2400mV VEE = –4.20VEE = –4.50VEE = –4.80http://onsemi.com186

MC10H605, MC100H605TTL DC CHARACTERISTICS (VCCT = +5.0V ±10%; VEE = –5.2V ±5% (10H); VEE = –4.2V to 5.5V (100H))0°C 25°C 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditionICCL Supply Current 65 75 65 75 65 75 mA Outputs LowICCH Supply Current 65 75 65 75 65 75 mA Outputs HighVOL Output Low Voltage 500 500 500 mV IOL = 24mAVOH Output High Voltage 2.5 2.5 2.5 mV IOH = 24mAIOSOutput Short CircuitCurrent100 225 100 225 100 225 mA VOUT = 0VAC TEST LIMITS (VCCT = +5.0V ±10%; VEE = –5.2V ±5% (10H); VEE = –4.2V to 5.5V (100H))0°C 25°C 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditiontPLHPropagation DelayCLK to Q (Diff)CLK to Q (SE)4.54.35.35.36.56.74.54.35.45.46.56.74.54.35.65.66.56.7ns Across P.S.and TempCL = 50pFtPHLPropagation DelayCLK to Q (Diff)CLK to Q (SE)4.03.85.05.06.06.24.03.85.15.16.06.24.03.85.55.56.06.2ns Across P.S.and TempCL = 50pFtPHLPropagation DelayMR to Q 2.5 4.9 7.0 2.5 5.2 7.0 3.0 5.8 7.5ns Across P.S.and TempCL = 50pFtSKEWDevice SkewPart–to–Part (Diff)Within–Device1.00.32.00.71.00.32.00.71.00.32.00.7nsCL = 50pFtS Setup Time 1.5 1.5 1.5 nstH Hold Time 1.5 1.5 1.5 nstPWtPWMinimum Pulse WidthCLKMinimum Pulse WidthMR1.0 1.0 1.0 ns1.0 1.0 1.0 nsVPP Minimum Input Swing 150 150 150 mV Peak–to–Peaktr Rise Time 0.7 1.0 1.5 0.7 1.0 1.5 0.7 1.0 1.5 ns 1V to 2Vtf Fall Time 0.5 0.7 1.2 0.5 0.7 1.2 0.5 0.7 1.2 ns 1V to 2VtRR Reset/Recovery Time 2.5 2.5 2.5 nshttp://onsemi.com187

The MC10/100H606 is a 6–bit, registered, single supply TTL toPECL translator. The device features differential PECL outputs aswell as a choice between either a differential PECL clock input or aTTL clock input. The asynchronous master reset control is a PECLlevel input.With its differential PECL outputs and TTL inputs the H606 deviceis ideally suited for the transmit function of a HPPI bus typeboard–to–board interface application. The on chip registers simplifythe task of synchronizing the data between the two boards.The device is available in either ECL standard: the MECL 10Hdevice is compatible with MECL 10KH logic levels, with a VCC of +5volts while the 100H device is compatible with 100K logic levels,with a VCC of +5 volts.• Differential 50Ω ECL Outputs• Choice Between Differential PECL or TTL Clock Input• Single Power Supply• Multiple Power and Ground Pins to Minimize NoiseDnCLKCLKTCLKMRVBB**LOGIC SYMBOL1 OF 6 BITSDCLKRQQnQn1. When using PECL inputs, TCLK must be tied to ground (0V).2. When using only one PECL input, the unused PECL input must be tiedto VBB, and TCLK must be tied to ground (0V).3. When using TCLK, both PECL inputs must be tied to ground (0V).TRUTH TABLEDnLHXMRLLHTCLK/CLKZZXQn+1LHLPLCC–28FN SUFFIXCASE 776PIN NAMESPIND0–D5CLK, CLKTCLKMRQ0–Q5Q0–Q5VCCEVCCTGNDhttp://onsemi.comMARKINGDIAGRAM10H606AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekPinout: 28–Lead PLCC (Top View)D0TCLKV BBCLKCLKMRV CCE262728234ORDERING INFORMATIONDevice Package ShippingMC10H606FN PLCC–28 37 Units/Rail1FUNCTIONTTL Data InputsDifferential PECL Clock InputTTL Clock InputPECL Master Reset InputTrue PECL OutputsInverted PECL OutputsPECL VCC (+5.0V)TTL VCC (+5.0V)TTL/PECL GroundD1 D2 V CCT D3 D4 D5 V CCE25 24 23 22 21 20 19125 6 7 8 9 10 11Q0 Q0 GND Q1 Q1 Q2 Q2Q5Q5Q4Q4V CCEQ3MC100H606FN PLCC–28 37 Units/Rail181716151413Q3Z = LOW to HIGH Transition© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 2188 Publication Order Number:MC10H606/D

MC10H606, MC100H606DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = + 25°C TA = + 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditionICCL Supply Current 18 30 18 30 18 30 mA Outputs LOWICCH Supply Current 13 25 13 25 13 25 mA Outputs HIGHIGND Supply Current 75 90 75 90 75 95 mATTL DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVIH Input HIGH Voltage 2.0 2.0 2.0 VVIL Input LOW Voltage 0.8 0.8 0.8 VVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18mAIIH Input HIGH Current 201002010020100V VIN = 2.7VVIN = 7.0VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5V10H PECL DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINH Input HIGH Current 255 145 145 µAIINL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage (Note 1.) 3830 4160 3870 4190 3930 4280 mV VCCT = 5.0VVIL Input LOW Voltage (Note 1.) 3050 3520 3050 3520 3050 3555 mV VCCT = 5.0VVOH Output HIGH Voltage (Note 1.) 3980 4160 4020 4190 4080 4270 mV VCCT = 5.0VVOL Output LOW Voltage (Note 1.) 3050 3370 3050 3370 3050 3400 mV VCCT = 5.0VVBB Reference Voltage (Note 1.) 3600 3710 3630 3730 3670 3790 mV VCCT = 5.0V1. PECL VIL, VIH, VOL, VOH VBB are given for VCCT = VCCE = 5.0V and will vary 1:1 with the power supply.http://onsemi.com189

MC10H606, MC100H606100H PECL DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINH Input HIGH Current 255 145 145 µAIINL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage (Note 2.) 3835 4120 3835 4120 3835 4120 mV VCCT = 5.0VVIL Input LOW Voltage (Note 2.) 3190 3525 3190 3525 3190 3525 mV VCCT = 5.0VVOH Output HIGH Voltage (Note 2.) 3975 4120 3975 4120 3975 4120 mV VCCT = 5.0VVOL Output LOW Voltage (Note 2.) 3190 3380 3190 3380 3190 3380 mV VCCT = 5.0VVBB Output Bias Voltage (Note 2.) 3600 3720 3600 3720 3600 3720 mV VCCT = 5.0V2. PECL VIL, VIH, VOL, VOH VBB are given for VCCT = VCCE = 5.0V and will vary 1:1 with the power supply.AC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = + 25°C TA = + 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditiontPDPropagation DelayTCLK++1.75 3.75 1.75 3.00 3.75 1.75 3.75 ns 50 to –2.0VtPDtPDtPDtPDPropagation DelayTCLK+–Propagation DelayCLK++Propagation DelayCLK+–Propagation DelayMR+–1.75 3.75 1.75 3.00 3.75 1.75 3.75 ns 50 to –2.0V1.50 3.50 1.50 2.50 3.50 1.50 3.50 ns 50 to –2.0V1.50 3.50 1.50 2.50 3.50 1.50 3.50 ns 50 to –2.0V1.50 3.50 1.50 2.50 3.50 1.75 3.75 ns 50 to –2.0VtSKEWDevice SkewPart–to–PartWithin Device2.00.51.00.32.00.52.00.5ns50 to –2.0VtS Setup Time 1.5 0.5 1.5 0.5 1.5 0.5 ns 50 to –2.0VtH Hold Time 1.5 0.5 1.5 0.5 1.5 0.5 ns 50 to –2.0VtPWtPWMinimum PulseWidthCLKMinimum PulseWidthMR1.5 1.5 1.0 1.5 ns 50 to –2.0V1.5 1.5 1.5 ns 50 to –2.0Vtr Rise Time 2.0 1.0 2.0 2.0 ns 50 to –2.0Vtf Fall Time 2.0 1.0 2.0 2.0 ns 50 to –2.0VtRES/RECReset/RecoveryTime2.5 2.0 2.5 2.0 2.5 2.0 ns 50 to –2.0Vhttp://onsemi.com190

The MC10H/100H607 is a 6–bit, registered PECL to TTLtranslator. The device features differential PECL inputs for both dataand clock. The TTL outputs feature 48mA sink, 24mA source drivecapability for driving high fanout loads or transmission lines. Theasynchronous master reset control is an ECL level input.With its differential PECL inputs and TTL outputs the H607 deviceis ideally suited for the receive function of a HPPI bus typeboard–to–board interface application. The on chip registers simplifythe task of synchronizing the data between the two boards.The device is available in either ECL standard: the 10H device iscompatible with MECL 10H logic levels, with a VCC of +5.0 volts,while the 100H device is compatible with 100K logic levels, with aVCC of +5.0 volts.• Differential ECL Data and Clock Inputs• 48mA Sink, 24mA Source TTL Outputs• Single Power Supply• Multiple Power and Ground Pins to Minimize NoisePLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAMA = Assembly LocationWL = Wafer LotYY = YearWW = Work Week110H607AWLYYWWORDERING INFORMATIONDevice Package ShippingMC10H607FN PLCC–28 37 Units/RailMC100H607FN PLCC–28 37 Units/Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3191 Publication Order Number:MC10H607/D

MC10H607, MC100H607LOGIC DIAGRAM1 OF 6 BITSDnDnDQQnCLKRPinout: 28–Lead PLCC (Top View)Q3 VCCT Q4 TGND Q5 VCCT MRCLKQ22625 24 23 22 21 20 1918D5CLKQ12717D5MRQ02816D4VBBTGND115D4CLK214VCCECLK313D3VBB412D3567 891011D0D0EGNDD1D1D2D2PIN NAMESPinD0 – D5D0 – D5CLK, CLKMRQ0 – Q5VCCEVCCTTGNDEGNDFunctionTrue PECL Data InputsInverted PECL Data InputsDifferential PECL Clock InputPECL Master Reset InputTTL OutputsPECL VCCTTL VCCTTL GroundPECL GroundDC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TRUTH TABLEDn MR TCLK/CLK Qn + 1LHXOpen InputLLHXZ = LOW to HIGH TransitionTA = 0°C TA = + 25°C TA = + 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditionIEEECL Power Supply Current10H100H70658580ICCL TTL Supply Current 100 120 100 120 100 120 mAICCH TTL Supply Current 100 120 100 120 100 120 mA7070858570758595ZZXXmALHLLhttp://onsemi.com192

MC10H607, MC100H60710H PECL DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINH Input HIGH Current 255 145 145 µAIINL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage 3830 4160 3870 4190 3930 4280 mV VCCT = 5.0VVIL Input LOW Voltage 3050 3520 3050 3520 3050 3555 mV VCCT = 5.0VVBB Output Bias Voltage 3600 3710 3630 3730 3670 3790 mV VCCT = 5.0VNOTE: PECL VIL, VIH, VOL, VOH, VBB are given for VCCT = VCCE = 5.0V and will vary 1:1 with power supply.100H PECL DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIIH Input HIGH Current 255 145 145 µAIIL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage 3835 4120 3835 4120 3835 4120 mV VCCT = 5.0VVIL Input LOW Voltage 3190 3525 3190 3525 3190 3525 mV VCCT = 5.0VVBB Output Bias Voltage 3600 3720 3600 3720 3600 3720 mV VCCT = 5.0VNOTE: PECL VIL, VIH, VOL, VOH, VBB are given for VCCT = VCCE = 5.0V and will vary 1:1 with power supply.10H/100H TTL DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVOH Output HIGH Voltage 2.52.02.52.02.52.0VIOH = –15mAIOH = –24mAVOL Output LOW Voltage 0.55 0.55 0.55 V IOL = 48mANOTE: DC levels such as VOH, VOL, etc., are standard for PECL and FAST devices, with the exceptions of: IOL = 48mA at 0.5VOL;and IOH = –24mA at 2.0VOH.AC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)TA = 0°C TA = + 25°C TA = + 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditiontPLHtPHHPropagation Delay to OutputQCLK to5.54.67.77.76.04.98.28.36.75.910.010.0nsCL = 50pFtPHL Propagation Delay to Output MR to Q 4.4 7.5 4.7 8.1 5.8 10.5 ns CL = 50pFtPW Minimum Pulse Width CLK, MR 1.0 1.0 1.0 nstr Rise Time 0.5 2.0 0.5 2.0 0.5 2.0 ns 1.0V to 2.0Vtf Fall Time 0.5 2.0 0.5 2.0 0.5 2.0 ns 1.0V to 2.0VtS Setup Time 1.5 1.5 1.5 nstH Hold Time 1.5 1.5 1.5 nsVPP Minimum Input Swing 200 200 200 mV1. Numbers are for both ++ and – – delay MR to Q.http://onsemi.com193

The MC10H/100H640 generates the necessary clocks for the68030, 68040 and similar microprocessors. It is guaranteed to meet theclock specifications required by the 68030 and 68040 in terms ofpart–to–part skew, within–part skew and also duty cycle skew.The user has a choice of using either TTL or PECL (ECL referencedto +5.0V) for the input clock. TTL clocks are typically used in presentMPU systems. However, as clock speeds increase to 50MHz andbeyond, the inherent superiority of ECL (particularly differentialECL) as a means of clock signal distribution becomes increasinglyevident. The H640 also uses differential PECL internally to achieve itssuperior skew characteristic.The H640 includes divide–by–two and divide–by–four stages, bothto achieve the necessary duty cycle skew and to generate MPU clocksas required. A typical 50MHz processor application would use aninput clock running at 100MHz, thus obtaining output clocks at50MHz and 25MHz (see Logic Diagram).The 10H version is compatible with MECL 10H ECL logic levels,while the 100H version is compatible with 100K levels (referencedto +5.0V).• Generates Clocks for 68030/040• Meets 030/040 Skew Requirements• TTL or PECL Input Clock• Extra TTL and PECL Power/Ground Pins• Asynchronous Reset• Single +5.0V SupplyFunctionReset (R): LOW on RESET forces all Q outputs LOW and all Qoutputs HIGH.Power–Up: The device is designed to have the POS edges of the ÷2and ÷4 outputs synchronized at power up.Select (SEL): LOW selects the ECL input source (DE/DE). HIGHselects the TTL input source (DT).The H640 also contains circuitry to force a stable state of the ECLinput differential pair, should both sides be left open. In this case, theDE side of the input is pulled LOW, and DE goes HIGH.PLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAM10H640AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H640FN PLCC–28 37 Units/RailMC100H640FN PLCC–28 37 Units/Rail1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 4194 Publication Order Number:MC10H640/D

MC10H640, MC100H640Pinout: 28–Lead PLCC(Top View)VT VT Q1 GT GT Q0 VTLOGIC DIAGRAMTTL OutputsQ0Q2GT2725 24 23 22 21 20 1926 1817VBBDEVBBTTL/ECL Clock InputsQ1Q2GTQ3VT2812161514DEVERDEDE MUX ÷ 2DTQ3Q0VT313GESELQ1Q04125 6 7 8 9 10 11Q1 GT GT Q4 Q5 VT SELDTTTL Control InputsR÷ 4Q4Q5PIN NAMESPINGTVTVEGEDE, DEVBBDTQn, QnSELRFUNCTIONTTL Ground (0 V)TTL VCC (+5.0 V)ECL VCC (+5.0 V)ECL Ground (0 V)ECL Signal Input (positive ECL)VBB Reference OutputTTL Signal InputSignal Outputs (TTL)Input Select (TTL)Reset (TTL)http://onsemi.com195

MC10H640, MC100H640AC CHARACTERISTICS (VT = VE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditiontPLHtPLHPropagation Delay ECLD to OutputPropagation Delay TTLD to OutputQ0–Q3 4.9 5.9 4.9 5.9 5.2 6.2 ns CL = 25pF5.0 6.0 5.0 6.0 5.3 6.3 ns CL = 25pFtskwd* Within–Device Skew 0.5 0.5 0.5 ns CL = 25pFtPLHtPLHtPLHtPLHPropagation Delay ECLD to OutputPropagation Delay TTLD to OutputPropagation Delay ECLD to OutputPropagation Delay TTLD to OutputQ0, Q1 4.9 5.9 4.9 5.9 5.2 6.2 ns CL = 25pF5.0 6.0 5.0 6.0 5.3 6.3 ns CL = 25pFQ4, Q5 4.9 5.9 4.9 5.9 5.2 6.2 ns CL = 25pF5.0 6.0 5.0 6.0 5.3 6.3 ns CL = 25pFtPDPropagation DelayR to OutputAllOutputs4.3 6.3 4.3 6.3 5.0 7.0 ns CL = 25pFtRtFOutput Rise/Fall Time0.8 V – 2.0 VAllOutputs2.52.52.52.52.52.5nsCL = 25pFfmax Maximum Input Frequency 135 135 135 MHz CL = 25pFtpw Minimum Pulse Width 1.50 1.50 1.50 nstrr Reset Recovery Time 1.25 1.25 1.25 ns* Within–Device Skew defined as identical transitions on similar paths through a device.VCC and CL RANGES TO MEET DUTY CYCLE REQUIREMENTS(0°C ≤ TA ≤ 85°C Output Duty Cycle MeasuredRelative to 1.5V)Symbol Characteristic Min Nom Max Unit ConditionRange of VCC and CL to meet minimum pulse width(HIGH or LOW) = 11.5 ns at fout ≤ 40 MHzVCCCL4.75105.0 5.2550VpFQ0–Q3Q0–Q1Range of VCC and CL to meet minimum pulse width(HIGH or LOW) = 9.5 ns at 40 < fout ≤ 50 MHzVCCCL4.875155.0 5.12527VpFQ0–Q3http://onsemi.com196

MC10H640, MC100H640DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIEE Power Supply Current ECL 57 57 57 mA VE PinICCH TTL 30 30 30 mA Total all VT pinsICCL 30 30 30 mATTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage2.00.82.00.82.00.8VIIH Input HIGH Current 201002010020100µA VIN = 2.7VVIN = 7.0VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5VVOH Output HIGH Voltage 2.52.02.52.02.52.0VIOH = –3.0mAIOH = –15mAVOL Output LOW Voltage 0.5 0.5 0.5 V IOL = 24mAVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0V10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current 0.52250.51750.5175 µAVIH*VIL*Input HIGH VoltageInput LOW Voltage3.833.054.163.523.873.054.193.523.943.054.283.555V VE = 5.0VVBB* Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V*NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current 0.52250.51750.5175 µAVIH*VIL*Input HIGH VoltageInput LOW Voltage3.8353.194.123.5253.8353.194.123.5253.8353.194.123.525V VE = 5.0VVBB* Output Reference Voltage 3.62 3.74 3.62 3.74 3.62 3.74 V*NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.10/100H640DUTY CYCLE CONTROLTo maintain a duty cycle of ±5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures1 and 2. For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.Best duty cycle control is obtained with a single µP load and minimum line length.http://onsemi.com197

MC10H640, MC100H64011115.25 VCCPW (ns)1095 VCC4.75 VCCNEGATIVE PULSE WIDTH (ns)1094.75 VCC5 VCC5.25 VCC0 25 50 75 85LOAD (pF)0 25 50 75 85LOAD (pF)Figure 1. Positive Pulse Width at25°C Ambient and 50 MHz OutFigure 2. Negative Pulse Width @ 50 MHzOut and 25°C Ambient1111POSITIVE PULSE WIDTH (ns)1095.125 VCC5 VCC4.875 VCCNEGATIVE PULSE WIDTH (ns)1094.875 VCC5 VCC5.125 VCC0 25 50 75 85LOAD (pF)0 25 50 75 85LOAD (pF)Figure 3. Positive Pulse Width at25°C Ambient at 50 MHz OutFigure 4. Negative Pulse Width @ 50 MHzOut and 25°C AmbientPOSITIVE PULSE WIDTH (ns)1110950 pF25 pF10 pFNEGATIVE PULSE WIDTH (ns)1110910 pF25 pF0° 25° 50° 75° 85°TEMPERATURE (°C)Figure 5. Temperature versus Positive Pulse Widthfor 100H640 at 50 MHz and +5.0 V VCC0° 25° 50° 75° 85°TEMPERATURE (°C)Figure 6. Temperature versus Negative Pulse Widthfor MC100H640 @ 50 MHz and +5.0 V VCChttp://onsemi.com198

MC10H640, MC100H640(ns)6.26.05.84.75 V5 V5.25 Vt PD5.65.45.20 25 50 75 85CLOAD (pF)Figure 7. tPD versus Load Typical at TA = 25°CDTRESET, RRtpwRtrecQ0, Q1, Q2, Q3Q0, Q1Q4, Q5Figure 8. MC10H/100H640 Clock Phase and Reset Recovery Time After Reset PulseDinQ0Q1Q3Q2Q4 & Q5AFTER POWER UPOUTPUTS Q4 & Q5 WILL SYN WITH POSITIVE EDGES OF Din & Q0 Q3 & NEGATIVE EDGES OF Q0 & Q1Figure 9. Output Timing Diagramhttp://onsemi.com199

The MC10H/100H641 is a single supply, low skew translating 1:9clock driver. Devices in the Motorola H600 translator series utilize the28–lead PLCC for optimal power pinning, signal flow through andelectrical performance.The device features a 24mA TTL output stage, with ACperformance specified into a 50pF load capacitance. A latch isprovided on–chip. When LEN is LOW (or left open, in which case it ispulled LOW by the internal pulldown) the latch is transparent. AHIGH on the enable pin (EN) forces all outputs LOW. Both the LENand EN pins are positive ECL inputs.The VBB output is provided in case the user wants to drive thedevice with a single–ended input. For single–ended use the VBBshould be connected to the D input and bypassed with a 0.01µFcapacitor.The 10H version of the H641 is compatible with positive MECL10H logic levels. The 100H version is compatible with positive100K levels.• PECL–TTL Version of Popular ECLinPS E111• Low Skew• Guaranteed Skew Spec• Latched Input• Differential ECL Internal Design• VBB Output for Single–Ended Use• Single +5V Supply• Logic Enable• Extra Power and Ground Supplies• Separate ECL and TTL Supply PinsPLCC–28FN SUFFIXCASE 776PIN NAMESPinsGT, VTGE, VED, DVBBQ0–Q8ENLENhttp://onsemi.comFunctionMARKINGDIAGRAM10H641AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekTTL GND, TTL VCCECL GND, ECL VCCSignal Input (Positive ECL)VBB Reference Output (Positive ECL)Signal Outputs (TTL)Enable Input (Positive ECL)Latch Enable Input (Positive ECL)1Pinout: 28–Lead PLCC (Top View)GT Q6 VT Q7 VT Q8 GTORDERING INFORMATIONDevice Package ShippingGT2625 24 23 22 21 20 1918VBBMC10H641FN PLCC–28 37 Units/RailMC100H641FN PLCC–28 37 Units/RailQ52717DVT2816DQ4115VEVT214LENQ3313GEGT45 6 7 8 9 10 1112ENGT Q2 VT Q1 VT Q0 GT© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 4200 Publication Order Number:MC10H641/D

MC10H641, MC100H641LOGIC DIAGRAMTTL OutputsQ0Q1Q2PECL InputQ3DDDQQ4VBBLENQ5ENQ6Q7Q8DC CHARACTERISTICS (VT = VE = 5.0V ±5%)TA = 0°C TA = + 25°C TA = + 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditionIEEPower Supply CurrentPECL24 30 24 30 24 30 mAICCH TTL 24 30 24 30 24 30 mAICCL 27 35 27 35 27 35 mATTL DC CHARACTERISTICS (VT = VE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVOH Output HIGH Voltage 2.5 2.5 2.5 V IOH = –15mAVOL Output LOW Voltage 0.5 0.5 0.5 V IOL = 24mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0V10H PECL DC CHARACTERISTICS0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIIH Input HIGH Current 225 175 175 µAIIL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage 3.83 4.16 3.87 4.19 3.94 4.28 V VE = 5.0V1VIL Input LOW Voltage 3.05 3.52 3.05 3.52 3.05 3.55 V VE = 5.0V1VBB Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V VE = 5.0V11. PECL VIH, VIL, and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0V.http://onsemi.com201

MC10H641, MC100H641100H PECL DC CHARACTERISTICS0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINH Input HIGH Curren 225 175 175 µAIINL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage 3.835 4.120 3.835 4.120 3.835 4.120 V VE = 5.0V1VIL Input LOW Voltage 3.190 3.525 3.190 3.525 3.190 3.525 V VE = 5.0V1VBB Output Reference Voltage 3.62 3.74 3.62 3.74 3.62 3.74 V VE = 5.0V11. PECL VIH, VIL, and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0V.AC CHARACTERISTICS (VT = VE = 5.0V ±5%)TJ = 0°C TJ = + 25°C TJ = + 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ConditiontPLH Propagation Delay 5.00 5.50 6.00 4.86 5.36 5.86 5.08 5.58 6.08 ns CL = 50 pF1tPHL D to Q5.36 5.86 6.36 5.27 5.77 6.27 5.43 5.93 6.43tskewDevice SkewPart–to–PartSingle VCCOutput–to–Output100075035010007503501000750350psCL = 50pF2CL = 50 pF3CL = 50 pF4tPLHtPHLtPLHtPHLPropagation DelayLEN to QPropagation DelayEN to Q4.9 6.9 4.9 6.9 5.0 7.0 ns CL = 50 pF5.0 7.0 4.9 6.9 5.0 7.0 ns CL = 50 pFtrtfOutput Rise/Fall0.8V to 2.0V1.71.61.71.61.71.6nsCL = 50 pFfMAX Max Input Frequency 65 65 65 MHz CL = 50 pF5tS Setup Time 0.75 0.50 0.75 0.50 0.75 0.50 nstH Hold Time 0.75 0.50 0.75 0.50 0.75 0.50 ns1. Propagation delay measurement guaranteed for junction temperatures. Measurements performed at 50MHz input frequency.2. Skew window guaranteed for a single temperature across a VCC = VT = VE of 4.75V to 5.25V (See Application Note in this datasheet).3. Skew window guaranteed for a single temperature and single VCC = VT = VE4. Output–to–output skew is specified for identical transitions through the device.5. Frequency at which output levels will meet a 0.8V to 2.0V minimum swing.Determining Skew for a Specific ApplicationThe H641 has been designed to meet the needs of very lowskew clock distribution applications. In order to optimizethe device for this application special considerations arenecessary in the determining of the part–to–part skewspecification limits. Older standard logic devices arespecified with relatively slack limits so that the device canbe guaranteed over a wide range of potential environmentalconditions. This range of conditions represented all of thepotential applications in which the device could be used. Theresult was a specification limit that in the vast majority ofcases was extremely conservative and thus did not allow foran optimum system design. For non–critical skew designsthis practice is acceptable, however as the clock speeds ofsystems increase overly conservative specification limitscan kill a design.The following will discuss how users can use theinformation provided in this data sheet to tailor apart–to–part skew specification limit to their application.The skew determination process may appear somewhattedious and time consuming, however if the utmost inperformance is required this procedure is necessary. Forapplications which do not require this level of skewperformance a generic part–to–part skew limit of 2.5ns canbe used. This limit is good for the entire ambient temperaturerange, the guaranteed VCC (VT, VE) range and theguaranteed operating frequency range.http://onsemi.com202

MC10H641, MC100H641Temperature DependenceA unique characteristic of the H641 data sheet is that theAC parameters are specified for a junction temperaturerather than the usual ambient temperature. Because very fewdesigns will actually utilize the entire commercialtemperature range of a device a tighter propagation delaywindow can be established given the smaller temperaturerange. Because the junction temperature and not the ambienttemperature is what affects the performance of the device theparameter limits are specified for junction temperature. Inaddition the relationship between the ambient and junctiontemperature will vary depending on the frequency, load andboard environment of the application. Since these factors areall under the control of the user it is impossible to providespecification limits for every possible application.Therefore a baseline specification was established forspecific junction temperatures and the information thatfollows will allow these to be tailored to specificapplications.Since the junction temperature of a device is difficult tomeasure directly, the first requirement is to be able to“translate” from ambient to junction temperatures. Thestandard method of doing this is to use the power dissipationof the device and the thermal resistance of the package. Fora TTL output device the power dissipation will be a functionof the load capacitance and the frequency of the output. Thetotal power dissipation of a device can be described by thefollowing equation:PD (watts) = ICC (no load) * VCC +VS * VCC * f * CL * # Outputswhere:VS= Output Voltage Swing = 3Vf = Output FrequencyCL = Load CapacitanceICC = IEE + ICCHFigure 1 plots the ICC versus Frequency of the H641 withno load capacitance on the output. Using this graph and theinformation specific to the application a user can determinethe power dissipation of the H641.5NORMALIZED ICC432Figure 2 illustrates the thermal resistance (in °C/W) forthe 28–lead PLCC under various air flow conditions. Byreading the thermal resistance from the graph andmultiplying by the power dissipation calculated above thejunction temperature increase above ambient of the devicecan be calculated.70°C/W)THERMAL RESISTANCE (605040300 200 400 600 800 1000AIRFLOW (LFPM)Figure 2. ∅JA versus Air FlowFinally taking this value for junction temperature andapplying it to Figure 3 allows the user to determine thepropagation delay for the device in question. A morecommon use would be to establish an ambient temperaturerange for the H641’s in the system and utilize the abovemethodology to determine the potential increased skew ofthe distribution network. Note that for this information if theTPD versus Temperature curve were linear the calculationswould not be required. If the curve were linear over alltemperatures a simple temperature coefficient could beprovided.PROPAGATION DELAY (ns)6.46.26.05.85.65.4TPHLTPLH100 10 20 30 40 50 60 70 80FREQUENCY (MHz)Figure 1. ICC versus f (No Load)5.2–30 –10 10 30 50 70 90 110 130JUNCTION TEMPERATURE ( °C)Figure 3. TPD versus Junction Temperaturehttp://onsemi.com203

MC10H641, MC100H641VCC DependenceTTL and CMOS devices show a significant propagationdelay dependence with VCC. Therefore the VCC variation ina system will have a direct impact on the total skew of theclock distribution network. When calculating the skewbetween two devices on a single board it is very likely anassumption of identical VCC’s can be made. In this case thenumber provided in the data sheet for part–to–part skewwould be overly conservative. By using Figure 4 the skewgiven in the data sheet can be reduced to represent a smalleror zero variation in VCC. The delay variation due to thespecified VCC variation is ≈270ps. Therefore, the 1nswindow on the data sheet can be reduced by 270ps if thedevices in question will always experience the same VCC.The distribution of the propagation delay ranges given in thedata sheet is actually a composite of three distributionswhose means are separated by the fixed difference inpropagation delay at the typical, minimum and maximumVCC.MORMALIZED PROPAGATION DELAY (ns)1.151.101.051.000.950.900.850.800.750TPLHMEASUREDTPHLTHEORETICAL10 20 30 40 50 60 70 80 90 100CAPACITIVE LOAD (pF)Figure 5. TPD versus Load∆ T PD (ps)1401006020–20–60–100–1404.75TPHL4.85 4.95 5.05 5.15 5.25VCC (V)Figure 4. ∆TPD versus VCCTPLHCapacitive Load DependenceAs with VCC the propagation delay of a TTL output isintimately tied to variation in the load capacitance. The skewspecifications given in the data sheet, of course, assumeequal loading on all of the outputs. However situations couldarise where this is an impossibility and it may be necessaryto estimate the skew added by asymmetric loading. Inaddition the propagation delay numbers are provided onlyfor 50pF loads, thus necessitating a method of determiningthe propagation delay for alternative loads.Figure 5 shows the relationship between the twopropagation delays with respect to the capacitive load on theoutput. Utilizing this graph and the 50pF limits thespecification of the H641 can be mapped into a spec foreither a different value load or asymmetric loads.Rise/Fall Skew DeterminationThe rise–to–fall skew is defined as simply the differencebetween the TPLH and the TPHL propagation delays. Thisskew for the H641 is dependent on the VCC applied to thedevice. Notice from Figure 4 the opposite relationship ofTPD versus VCC between TPLH and TPHL. Because of thisthe rise–to–fall skew will vary depending on VCC. Since inall likelihood it will be impossible to establish the exactvalue for VCC, the expected variation range for VCC shouldbe used. If this variation will be the ±5% shown in the datasheet the rise–to–fall skew could be established by simplysubtracting the fastest TPLH from the slowest TPHL; thisexercise yields 1.41ns. If a tighter VCC range can be realizedFigure 4 can be used to establish the rise–to–fall skew.Specification Limit Determination ExampleThe situation pictured in Figure 6 will be analyzed as anexample. The central clock is distributed to two differentcards; on one card a single H641 is used to distribute theclock while on the second card two H641’s are required tosupply the needed clocks. The data sheet as well as thegraphical information of this section will be used tocalculate the skew between H641a and H641b as well as theskew between all three of the devices. Only the TPLH will beanalyzed, the TPHL numbers can be found using the sametechnique. The following assumptions will be used:– All outputs will be loaded with 50pF– All outputs will toggle at 30MHz– The VCC variation between the two boards is ±3%– The temperature variation between the threedevices is ±15°C around an ambient of 45°C.– 500LFPM air flowhttp://onsemi.com204

MC10H641, MC100H641The first task is to calculate the junction temperature forthe devices under these conditions. Using the powerequation yields:PD = ICC (no load) * VCC +VCC * VS * f * CL * # outputs= 4.3 * 48mA * 5V + 5V * 3V * 30MHz *50pF * 9= 432mW + 203mW = 635mWUsing the thermal resistance graph of Figure 2 yields athermal resistance of 41°C/W which yields a junctiontemperature of 71°C with a range of 56°C to 86°C. Using theTPD versus Temperature curve of Figure 3 yields apropagation delay of 5.42ns and a variation of 0.19ns.Since the design will not experience the full ±5% VCCvariation of the data sheet the 1ns window provided will beunnecessarily conservative. Using the curve of Figure 4shows a delay variation due to a ±3% VCC variation of±0.075ns. Therefore the 1ns window can be reduced to1ns – (0.27ns – 0.15ns) = 0.88ns. Since H641a and H641bare on the same board we will assume that they will alwaysbe at the same VCC; therefore the propagation delay windowwill only be 1ns – 0.27ns = 0.73ns.Putting all of this information together leads to a skewbetween all devices of0.19ns + 0.88ns(temperature + supply, and inherent device),while the skew between devices A and B will be only0.19ns + 0.73ns(temperature + inherent device only).In both cases, the propagation delays will be centeredaround 5.42ns, resulting in the following tPLH windows:TPLHTPLH= 4.92ns – 5.99ns; 1.07ns window(all devices)= 5.00ns – 5.92ns; 0.92ns window(devices a & b)Of course the output–to–output skew will be as shown inthe data sheet since all outputs are equally loaded.This process may seem cumbersome, however the delaywindows, and thus skew, obtained are significantly betterthan the conservative worst case limits provided at thebeginning of this note. For very high performance designs,this extra information and effort can mean the differencebetween going ahead with prototypes or spending valuableengineering time searching for alternative approaches.BACKPLANEH641aECLH641bECLH641cECLQ0Q8Q0Q8Q0Q8TTLTTLTTLFigure 6. Example ApplicationCard 1Card 2http://onsemi.com205

The MC10H/100H642 generates the necessary clocks for the68030, 68040 and similar microprocessors. It is guaranteed to meet theclock specifications required by the 68030 and 68040 in terms ofpart–to–part skew, within–part skew and also duty cycle skew.The user has a choice of using either TTL or PECL (ECL referencedto +5.0V) for the input clock. TTL clocks are typically used in presentMPU systems. However, as clock speeds increase to 50MHz andbeyond, the inherent superiority of ECL (particularly differentialECL) as a means of clock signal distribution becomes increasinglyevident. The H642 also uses differential PECL internally to achieve itssuperior skew characteristic.The H642 includes divide–by–two and divide–by–four stages, bothto achieve the necessary duty cycle skew and to generate MPU clocksas required. A typical 50MHz processor application would use aninput clock running at 100MHz, thus obtaining output clocks at50MHz and 25MHz (see Logic Diagram).The 10H version is compatible with MECL 10H ECL logic levels,while the 100H version is compatible with 100K levels (referenced to+5.0V).• Generates Clocks for 68030/040• Meets 030/040 Skew Requirements• TTL or PECL Input Clock• Extra TTL and PECL Power/Ground Pins• Asynchronous Reset• Single +5.0V SupplyFunctionReset(R): LOW on RESET forces all Q outputs LOW.Select(SEL): LOW selects the ECL input source (DE/DE). HIGHselects the TTL input source (DT).The H642 also contains circuitry to force a stable input state of theECL differential input pair, should both sides be left open. In this Case,the DE side of the input is pulled LOW, and DE goes HIGH.Power Up: The device is designed to have positive edges of the ÷2and ÷4 outputs synchronized at Power Up.PLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAM10H642AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H642FN PLCC–28 37 Units/RailMC100H642FN PLCC–28 37 Units/Rail1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 5206 Publication Order Number:MC10H642/D

MC10H642, MC100H642VT VT Q1 GT GT Q0 VTQ225 24 23 22 21 20 1926 18VBBGT2717DEGT2816DEQ31Pinout: 28–Lead PLCC(Top View)15VEVT214RVT313GEQ445 6 7 8 9 10 1112DTQ5GT GT Q6 Q7 VT SELLOGIC DIAGRAMTTL OutputsQ7TTL/ECL Clock InputsVBBQ6Q5DEDEMUX÷4Q4DTQ3SELQ2TTL Control Inputs÷2Q1RQ0PIN NAMESPin Symbol Description Pin Symbol Description8182838485868788891011121314Q3VTVTQ4Q5GTGTQ6Q7VTSELDTGERSignal Output (TTL)**TTL VCC (+5.0V)TTL VCC (+5.0V)Signal Output (TTL)**Signal Output (TTL)**TTL Ground (0V)TTL Ground (0V)Signal Output (TTL)**Signal Output (TTL)**TTL VCC (+5.0V)Input Select (TTL)TTL Signal InputECL Ground (0V)Reset (TTL)1516171819202122232425262728VEDEDEVBBVTQ0GTGTQ1VTVTQ2GTGTECL VCC (+5.0V)ECL Signal Input (Non–Inverting)ECL Signal Input (Inverting)VBB Reference OutputTTL VCC (+5.0V)Signal Output (TTL)*TTL Ground (0V)TTL Ground (0V)Signal Output (TTL)*TTL VCC (+5.0V)TTL VCC (+5.0V)Signal Output (TTL)**TTL Ground (0V)TTL Ground (0V)**Divide by 2**Divide by 4http://onsemi.com207

MC10H642, MC100H642AC CHARACTERISTICS (VT = VE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditiontPLHPropagation DelayD to OutputQ2–Q7C ECLC TTL4.704.705.705.704.754.755.755.754.604.505.605.50nsCL = 25pFtskpp Part–to–Part Skew 1.0 1.0 1.0 nstskwd* Within–Device Skew 0.5 0.5 0.5 nstPLHPropagation DelayD to OutputQ0, Q1C ECLC TTL4.304.305.305.304.504.505.505.504.254.255.255.25nsCL = 25pFtskpp Part–to–Part Skew AllOutputs2.0 2.0 2.0 ns CL = 25pFtskwd Within–Device Skew 1.0 1.0 1.0 ns CL = 25pFtPDPropagation DelayR to OutputAllOutputs4.3 6.3 4.0 6.0 4.5 6.5 ns CL = 25pFtRtFOutput Rise/Fall Time0.8 V to 2.0 VAllOutputs2.52.52.52.52.52.5nsCL = 25pFfMAX** Maximum Input Frequency 100 100 100 MHz CL = 25pFRPW Reset Pulse Width 1.5 1.5 1.5 nsRRT Reset Recovery Time 1.25 1.25 1.25 ns* Within–Device Skew defined as identical transactions on similar paths through a device.** NOTE: MAX Frequency is 135MHz.10H PECL CHARACTERISTICS (VT = VE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current 0.5* NOTE2250.51750.5175 µAVIHVILInput HIGH VoltageInput LOW Voltage3.833.054.163.523.873.054.193.523.943.054.283.555V VEE = 5.0V* NOTEVBB Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V100H PECL CHARACTERISTICS (VT = VE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current 0.5* NOTE2250.51750.5175 µAVIHVILInput HIGH VoltageInput LOW Voltage3.8353.1904.1203.5253.8353.1904.1203.5253.8353.1904.1203.525V VEE = 5.0V* NOTEVBB Output Reference Voltage 3.620 3.740 3.620 3.740 3.620 3.740 V*NOTE: PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0V.http://onsemi.com208

MC10H642, MC100H64210H/100H DC CHARACTERISTICS (VT = VE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIEE Power Supply Current PECL 57 57 57 mA VE PinICCH TTL 30 30 30 mA Total All VT PinsICCL 30 30 30 mA10H/100H TTL DC CHARACTERISTICS (VT = VE = 5.0V ±5%)TA = 0°C TA = 25°C TA = 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage2.00.82.00.82.00.8VIIH Input HIGH Current 201002010020100µA VIN = 2.7VVIN = 7.0VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5VVOH Output HIGH Voltage 2.52.02.52.02.52.0VIOH = –3.0mAIOH = –15mAVOL Output LOW Voltage 0.5 0.5 0.5 V IOL = 24mAVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0V10/100H642DUTY CYCLE CONTROLTo maintain a duty cycle of ±5% at 50 MHz, limit the loadcapacitance and/or power supply variation as shown inFigures 1 and 2. For a ±2.5% duty cycle limit, see Figures 3and 4. Figures 5 and 6 show duty cycle variation withtemperature. Figure 7 shows typical TPD versus load.Figure 8 shows reset recovery time. Figure 9 shows outputstates after power up.Best duty cycle control is obtained with a single µP loadand minimum line length.http://onsemi.com209

MC10H642, MC100H6421111POSITIVE PULSE WIDTH (ns)104.755.005.25NEGATIVE PULSE WIDTH (ns)104.755.005.259 0 10 20 30 40 50 60CAPACITIVE LOAD (pF)90 10 20 30 40 50 60CAPACITIVE LOAD (pF)Figure 1. MC10H642 Positive PW versus Load@ ±5% VCC, TA = 25°CFigure 2. MC10H642 Negative PW versus Load@ ±5% VCC, TA = 25°C10.610.8POSITIVE PULSE WIDTH (ns)10.410.210.09.89.64.8755.005.125NEGATIVE PULSE WIDTH (ns)10.610.410.210.09.84.8755.005.1259.49.69.2 0 10 20 30 40 50 609.40 10 20 30 40 50 60CAPACITIVE LOAD (pF)CAPACITIVE LOAD (pF)Figure 3. MC10H642 Positive PW versus Load@ ±2.5% VCC, TA = 25°CFigure 4. MC10H642 Negative PW versus Load@ ±2.5% VCC, TA = 25°C10.410.5POSITIVE PULSE WIDTH (ns)10.210.09.89.60 pF25 pF50 pFNEGATIVE PULSE WIDTH (ns)10.310.19.99.79.50 pF25 pF50 pF9.40 20 40 60 80 1000 20 40 60 80 100TEMPERATURE (°C)TEMPERATURE (°C)Figure 5. MC10H642 Positive PW versus Temperature,VCC = 5.0VFigure 6. MC10H642 Negative PW versusTemperature, VCC = 5.0Vhttp://onsemi.com210

MC10H642, MC100H6426.26.0Tpd (ns)5.85.64.755.005.255.45.20 10 20 30 40 50 60CAPACITIVE (pF)Figure 7. MC10H642 + Tpd versus Load, VCC ±5%, TA = 25°C(Overshoot at 50 MHz with no load makes graph non linear)DTRESET, RQ0Q1RtpwRtrecQ2Q7MC10/100H642Figure 8. Clock Phase and Reset Recovery Time After Reset PulseMC10/100H642DinQ0.Q1Q4 & Q5Q2Q7After Power UpFigure 9. OutputsQ2 Q7 will Synchronize with Pos Edges of Din & Q0 Q1http://onsemi.com211

MC10H642, MC100H642SWITCHING CIRCUIT AND WAVEFORMSSwitching Circuit PECL:PECLPULSEGENERATORUSE 0.1 µF CAPACITORSFOR DECOUPLING.50 Ω COAXUSE OSCILLOSCOPEINTERNAL 50 Ω LOADFOR TERMINATION.CH AIN50 Ω COAXVEEDEVICEUNDERTESTOSCILLOSCOPEVCC & VCCOOUTCH B450 Ω50 Ω COAXTTLDEVICEUNDERTESTtPZL, tPLZ+7 V OPENR1500 Ω50 pF R2500 ΩALLOTHERSWAVEFORMS: Rise and Fall TimesPECL/TTLPropagation Delay — Single EndedPECL/TTL80%/2.0 V50%/1.5 VVinVout20%/0.8 VTpd++Tpd––TriseTfallVout50%/1.5 Vhttp://onsemi.com212

The MC10H/100H643 is a dual supply, low skew translating 1:8clock driver. Devices in the Motorola H600 translator series utilize the28–lead PLCC for optimal power pinning, signal flow through andelectrical performance. The dual–supply H643 is similar to the H641,which is a single–supply 1:9 version of the same function.The device features a 48mA TTL output stage, with ACperformance specified into a 50pF load capacitance. A Latch isprovided on–chip. When LEN is LOW (or left open, in which case it ispulled LOW by the internal pulldowns) the latch is transparent. AHIGH on the enable pin (EN) forces all outputs LOW.The 10H version is compatible with MECL 10H ECL logic levels.The 100H version is compatible with 100K levels.• ECL/TTL Version of Popular ECLinPS E111• Low Skew Within Device 0.5ns• Guaranteed Skew Spec Part–to–Part 1.0ns• Latch• Differential Internal Design• VBB Output• Dual Supply• Reset/Enable• Multiple TTL and ECL Power/Ground PinsQ326Pinout: 28–Lead PLCC (Top View)Q4OGND3Q5OVT2Q6OGND4Q725 24 23 22 21 20 1918IVT2PLCC–28FN SUFFIXCASE 776PIN NAMESPINOGNDOVTIGNDIVTVEEVCCED, DVBBQ0–Q7ENLENhttp://onsemi.comMARKINGDIAGRAM10H643AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekFUNCTIONTTL Output Ground (0V)TTL Output VCC (+5.0V)Internal TTL GND (0V)Internal TTL VCC (+5.0V)ECL VEE (–5.2/–4.5V)ECL Ground (0V)Signal Input (ECL)VBB Reference OutputSignal Outputs (TTL)Enable Input (ECL)Latch Enable Input (ECL)1OGND22717IGND2Q2OVT1Q12812161514VCCEVCCELENORDERING INFORMATIONDevice Package ShippingMC10H643FN PLCC–28 37 Units/RailOGND1313VBBMC100H643FN PLCC–28 37 Units/RailQ04125 6 7 8 9 10 11DIVT1IGND1V EEV EEV EEEND© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 4213 Publication Order Number:MC10H643/D

MC10H643, MC100H643LOGIC DIAGRAMQ0Q1Q2ECL INPUTQ3DDDQTTL OUTPUTSVBBQ4LENENQ5Q6Q7DC CHARACTERISTICS (IVT = OVT = 5.0V ±5%; VEE = –5.2V ±5% (10H Version); VEE = –4.2V to 5.5V (100H Version))0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIEE ECL – 42 – 42 – 42 mA VEE PinsICCL Power Supply Current TTL – 106 – 106 – 106 mA Total all OVTICCH – 95 – 95 – 95 mA and IVT pinsAC CHARACTERISTICS (IVT = OVT = 5.0V ±5%; VEE = –5.2V ±10% (10H); –4.2V to 5.5V (100H); VCCE = GND)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditiontPLHPropagation Delay to OutputDLENEN4.03.53.55.05.55.54.13.53.55.15.55.54.43.93.95.45.95.9nsCL = 50pFt SKEW Within–Device Skew – 0.5 – 0.5 0.5 ns Note 1twPulse Width OutHIGH or LOW@ fout = 50MHz9.0 11.0 9.0 11.0 9.0 11.0 nsCL = 50pFNote 2tsthSetup TimeD 0.75 – 0.75 – 0.75 – nsHold TimeD 0.75 – 0.75 – 0.75 – nst RRRecovery TimeLENEN1.251.25––1.251.25––1.251.25––nstpwMinimum Pulse WidthLENEN1.51.5––1.51.5––1.51.5––nstrtfRise / Fall Times0.8 V – 2.0 V – 1.2 – 1.2 – 1.2 ns1. Within–Device skew defined as identical transitions on similar paths through a device.2. Pulse width is defined relative to 1.5V measurement points on the ouput waveform.CL = 50pFhttp://onsemi.com214

MC10H643, MC100H643TRUTH TABLED LEN EN QLHXXLLHXLLLHLHQOLDC TTL CHARACTERISTICS(IVT = OVT = 5.0V ±5%; VEE = –5.2V ±5% (10H Version); VEE = –4.2V to 5.5V (100H Version))0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVOHOutput HIGH Voltage2.52.0––2.52.0––2.52.0–– VIOH = –3.0mAIOH = –15mAVOL Output LOW Voltage – 0.5 – 0.5 – 0.5 V IOH = 48mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0V10H ECL DC CHARACTERISTICS(IVT = OVT = 5.0V ±5%; VEE = –5.2V ±5% (10H Version); VEE = –4.2V to 5.5V (100H Version))0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current–0.5225––0.5175––0.5175–µAVIHVILInput HIGH VoltageInput LOW Voltage–1170–1950–840–1480–1130–1950–810–1480–1070–1950–735–1450mVVBB Output Reference Voltage –1380 –1270 –1350 –1250 –1310 –1190 mV100H ECL DC CHARACTERISTICS (IVT = OVT = 5.0V ±5%; VEE = –5.2V ±5% (10H); VEE = –4.2V to 5.5V (100H))0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current–0.5225––0.5175––0.5175–µAVIHVILInput HIGH VoltageInput LOW Voltage–1165–1810–880–1475–1165–1810–880–1475–1165–1810–880–1475mVVBB Output Reference Voltage –1380 –1260 –1380 –1260 –1380 –1260 mVhttp://onsemi.com215

The MC10H/100H644 generates the necessary clocks for the68030, 68040 and similar microprocessors. The device is functionallyequivalent to the H640, but with fewer outputs in a smaller outline20–lead PLCC package. It is guaranteed to meet the clockspecifications required by the 68030 and 68040 in terms ofpart–to–part skew, within–part skew and also duty cycle skew.The user has a choice of using either TTL or PECL (ECL referencedto +5.0V) for the input clock. TTL clocks are typically used in presentMPU systems. However, as clock speeds increase to 50MHz andbeyond, the inherent superiority of ECL (particularly differentialECL) as a means of clock signal distribution becomes increasinglyevident. The H644 also uses differential ECL internally to achieve itssuperior skew characteristic.The H644 includes divide–by–two and divide–by–four stages, bothto achieve the necessary duty cycle and skew to generate MPU clocksas required. A typical 50MHz processor application would use aninput clock running at 100MHz, thus obtaining output clocks at50MHz and 25MHz (see Logic Symbol).The 10H version is compatible with MECL 10H ECL logic levels,while the 100H version is compatible with 100K levels (referencedto +5.0V).• Generates Clocks for 68030/040• Meets 68030/040 Skew Requirements• TTL or PECL Input Clock• Extra TTL and ECL Power/Ground Pins• Within Device Skew on Similar Paths is 0.5 ns• Asynchronous Reset• Single +5.0V SupplyFunctionReset (R): LOW on RESET forces all Q outputs LOW and all Qoutputs HIGH.Synchronized Outputs: The device is designed to have the POSedges of the ÷2 and ÷4 outputs synchronized.Select (SEL): LOW selects the PECL input source (DE/DE). HIGHselects the TTL input source (DT).The H644 also contains circuitry to force a stable state of the PECLinput differential pair, should both sides be left open. In this case, theDE side of the input is pulled LOW, and DE goes HIGH.PLCC–20FN SUFFIXCASE 775http://onsemi.comMARKINGDIAGRAM10H644AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H644FN PLCC–20 37 Units/RailMC100H644FN PLCC–20 37 Units/Rail1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 4216 Publication Order Number:MC10H644/D

MC10H644, MC100H644Pinout: 20–Lead PLCC (Top View)Q4 VT Q5 GT RGT191817 16 15 1413VEQ32012DEGT111VBBQ2210DEGT34 5 6 7 89GEQ1 VT Q0 SEL DTLOGIC DIAGRAMTTL OUTPUTSVBBDE(ECL)DE(ECL)2:1 MUX÷2Q0Q1DT(TTL)Q2SEL(TTL)Q3÷4Q4R(TTL)Q5PIN NAMESPINGTVTVEGEDE, DEVBBDTQn, QnSELRFUNCTIONTTL Ground (0V)TTL VCC (+5.0V)ECL VCC (+5.0V)ECL Ground (0V)ECL Signal Input (positive ECL)VBB Reference OutputTTL Signal InputSignal Outputs (TTL)Input Select (TTL)Reset (TTL)http://onsemi.com217

MC10H644, MC100H644AC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditiontPLHtPLHPropagation Delay ECLD to OutputPropagation Delay TTLD to OutputAll Outputs 5.8 6.8 5.7 6.7 6.1 7.1 ns CL = 50pF5.7 6.7 5.7 6.7 6.0 7.0 ns CL = 50pFtskwd* Within–Device Skew Q0, 1, 4, 5 – 0.5 – 0.5 – 0.5 ns CL = 50pFtskwd* Within–Device Skew Q2, Q3 – 0.5 – 0.5 – 0.5 ns CL = 50pFtskwd* Within–Device Skew All Outputs – 1.5 – 1.5 – 1.5 ns CL = 50pFtskp–p* Part–to–Part Skew Q0, 1, 4, 5 – 1.0 – 1.0 – 1.0 ns CL = 50pFtPDtRtFPropagation DelayR to OutputOutput Rise/Fall Time0.8V – 2.0VAll Outputs 4.3 7.3 4.3 7.3 4.5 7.5 ns CL = 50pFAll Outputs – 1.6 – 1.6 – 1.6 ns CL = 50pFfmax Maximum Input Frequency 135 – 135 – 135 – MHz CL = 50pFTW Minimum Pulse Width Reset 1.5 – 1.5 – 1.5 – nstrr Reset Recovery Time 1.25 – 1.25 – 1.25 – nsTPWTSPulse Width Out High orLow @ fin = 100 MHzand CL = 50 pfQ0, 1 9.5 10.5 9.5 10.5 9.5 10.5 ns CL = 50pfRelative 1.5VSetup TimeSEL to DE, DT 2.0 – 2.0 – 2.0 –nsTHHold TimeSEL to DE, DT 2.0 – 2.0 – 2.0 –* Skews are specified for Identical Edgesnshttp://onsemi.com218

MC10H644, MC100H644DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIEE Power Supply Current ECL 65 65 65 mA VE PinICC TTL 85 85 85 mA Total all VT pinsTTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage2.00.82.00.82.00.8VIIH Input HIGH Current 201002010020100µA VIN = 2.7 VVIN = 7.0 VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 VVOH Output HIGH Voltage 2.52.02.52.02.52.0VIOH = –3.0 mAIOH = –24 mAVOL Output LOW Voltage 0.5 0.5 0.5 V IOL = 24 mAVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18 mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0 V10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current 0.52250.51750.5175 µAVIH*VIL*Input HIGH VoltageInput LOW Voltage3.833.054.163.523.873.054.193.523.943.054.283.55VVE = 5.0 VVBB* Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V VE = 5.0 V100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIINHIINLInput HIGH CurrentInput LOW Current 0.52250.51750.5175 µAVIH*VIL*Input HIGH VoltageInput LOW Voltage3.8353.194.123.5253.8353.194.123.5253.8353.194.123.525VVE = 5.0 VVBB* Output Reference Voltage 3.62 3.74 3.62 3.74 3.62 3.74 V VE = 5.0 V* NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0 V.Only corresponds to ECL Clock Inputs.http://onsemi.com219

The MC10H645 is a single supply, low skew, TTL I/O 1:9 ClockDriver. Devices in the Motorola H600 clock driver family utiize the28–lead PLCC for optimal power and signal pin placement.The device features a 24mA TTL ouput stage with AC performancespecified into a 50pF load capacitance. A 2:1 input mux is provided onchip to allow for distributing both system and diagnostic clock signalsor designing clock redundancy into a system. With the SEL input heldLOW the DO input will be selected, while the D1 input is selectedwhen the SEL input is forced HIGH.• Low Skew Typically 0.65ns Within Device• Guaranteed Skew Spec 1.25ns Part–to–Part• Input Clock Muxing• Differential ECL Internal Design• Single Supply• Extra TTL and ECL Power/Ground PinsPIN NAMESPLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAMA = Assembly LocationWL = Wafer LotYY = YearWW = Work Week110H645AWLYYWWPINGTVTVEGEDnQ0 – Q8SELFUNCTIONTTL Ground (0V)TTL VCC (+5.0V)ECL VCC (+5.0V)ECL Ground (0V)TTL Signal InputTTL Signal OutputsTTL Mux SelectORDERING INFORMATIONDevice Package ShippingMC10H645FN PLCC–28 37 Units/RailMC100H645FN PLCC–28 37 Units/RailLOGIC DIAGRAMPinout: 28–Lead PLCC (Top View)TTL InputsMUXTTL OutputsQ0Q1GT26GT Q6 VT Q7 VT Q8 GT25 24 23 22 21 20 1918NCD0D0D0QQ2Q52717D0D1D1D1SQSQ3Q4VTQ4VT2812161514D1VESELSELQ5Q6Q7Q3GT3413125 6 7 8 9 10 11GENCQ8GTQ2 VT Q1 VT Q0 GT© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 5220 Publication Order Number:MC10H645/D

MC10H645PIN DESCRIPTIONSPin Symbol Description Pin Symbol Description1234567891011121314Q4VTQ3GTGTQ2VTQ1VTQ0GTNCGESELSignal Output (TTL)TTL VCC (+5.0V)Signal Output (TTL)TTL Ground (0V)TTL Ground (0V)Signal Output (TTL)TTL VCC (+5.0V)Signal Output (TTL)TTL VCC (+5.0V)Signal Output (TTL)TTL Ground (0V)No ConnectionECL GroundSelect Input (TTL)1516171819202122232425262728VED1D0NCGTQ8VTQ7VTQ6GTGTQ5VTECL VCC (+5.0V)Signal Input (TTL)Signal Input (TTL)No ConnectionTTL Ground (0V)Signal Output (TTL)TTL VCC (+5.0V)Signal Output (TTL)TTL VCC (+5.0V)Signal Output (TTL)TTL Ground (0V)TTL Ground (0V)Signal Output (TTL)TTL VCC (+5.0V)TRUTH TABLED0 D1 SEL QLHXXXXLHLLHHLHLHABSOLUTE RATINGS (Do not exceed)Symbol Characteristic Value UnitVE (ECL) Power Supply Voltage –0.5 to +7.0 VVT (TTL) Power Supply Voltage –0.5 to +7.0 VVI (TTL) Input Voltage –0.5 to +7.0 VVout Disabled 3–State Output 0.0 to VT VTstg Storage Temperature –65 to 150 °CTamb Operating Temperature 0.0 to +85 °CDC CHARACTERISTICS (VT = VE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionIEE Power Supply Current ECL 30 30 30 mA VE PinICCH TTL 30 30 30 mA Total all VT pinsICCL 35 35 35 mAVOH Output HIGH Voltage 2.52.02.52.02.52.0VIOH = –3.0mAIOH = –15mAVOL Output LOW Voltage 0.5 0.5 0.5 V IOL = 24mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0Vhttp://onsemi.com221

MC10H645TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage2.00.82.00.82.00.8VIIH Input HIGH Current 201002010020100µA VIN = 2.7 VVIN = 7.0 VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 VVOH Output HIGH Voltage 2.52.02.52.02.52.0VIOH = –3.0 mAIOH = –24 mAVOL Output LOW Voltage 0.5 0.5 0.5 V IOL = 24 mAVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18 mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0 VAC CHARACTERISTICS (VT = VE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditiontPLHtPLHPropagation DelayD0 to Output OnlyPropagation DelayD1 to OutputQ0–Q8 4.8 5.8 4.8 5.8 5.2 6.2 ns CL = 50pF4.8 5.8 4.8 5.8 5.2 6.2 nstPHLPropagation DelayD0 to OutputD1 to Output4.84.85.85.84.84.85.85.85.25.26.26.2nstskpptskwd*tPLHPart–to–Part SkewD0 to Output OnlyWithin–Device SkewD0 to Output OnlyPropagation DelaySEL to Q1.0 1.0 1.0 ns0.65 0.65 0.65 nsQ0–Q8 4.5 6.5 5.0 7.0 5.2 7.2 ns CL = 50pFtrtfOutput Rise/Fall Time0.8V to 2.0VQ0–Q8 0.50.52.52.50.50.52.52.50.50.52.52.5nsCL = 50pFtSSetup TimeSEL to D 1.0 1.0 1.0* Within–Device Skew defined as identical transitions on similar paths through a device.DUTY CYCLE SPECIFICATIONS (0°C ≤ TA ≤ 85°C; Duty Cycle Measured Relative to 1.5V)nsSymbol Characteristic Min Nom Max Unit ConditionPWRange of VCC and CL to Meet Min PulseWidth (HIGH or LOW) at fout ≤50MHzVCCCLPW4.87510.09.05.0 5.12550.011.0VpFnsAll Outputshttp://onsemi.com222

The MC10H/100H646 is a single supply, low skew translating 1:8clock driver. Devices in the Motorola H600 translator series utilize the28–lead PLCC for optimal power pinning, signal flow through andelectrical performance. The single supply H646 is similar to the H643,which is a dual supply 1:8 version of the same function.The H646 was designed specifically to drive series terminatedtransmission lines. Special techniques were used to match the HIGHand LOW output impedances to about 7ohms. This simplifies thechoice of the termination resistor for series terminated applications. Tomatch the HIGH and LOW output impedances, it was necessary toremove the standard IOS limiting resistor. As a result, the user shouldtake care in preventing an output short to ground as the part will bepermanently damaged.The H646 device meets all of the requirements for driving the 60and 66MHz Pentium Microprocessor. The device has no PLLcomponents, which greatly simplifies its implementation into a digitaldesign. The eight copies of the clock allows for point–to–point clockdistribution to simplify board layout and optimize signal integrity.The H646 provides differential PECL inputs for picking up LOWskew PECL clocks from the backplane and distributing it to TTL loadson a daughter board. When used in conjunction with theMC10/100E111, very low skew, very wide clock trees can bedesigned. In addition, a TTL level clock input is provided forflexibility. Note that only one of the inputs can be used on a singlechip. For correct operation, the unused input pins should be left open.The Output Enable pin forces the outputs into a high impedancestate when a logic 0 is applied.The output buffers of the H646 can drive two series terminated, 50Ωtransmission lines each. This capability allows the H646 to drive up to16 different point–to–point clock loads. Refer to the Applicationssection for a more detailed discussion in this area.The 10H version is compatible with MECL 10H ECL logic levels.The 100H version is compatible with 100K levels.• PECL/TTL–TTL Version of Popular ECLinPS E111• Low Skew• Guaranteed Skew Spec• Tri–State Enable• Differential Internal Design• VBB Output• Single Supply• Extra TTL and ECL Power/Ground Pins• Matched High and Low Output Impedance• Meets Specifications Required to Drive the PentiumMicroprocessorPLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAM10H646AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H646FN PLCC–28 37 Units/RailMC100H646FN PLCC–28 37 Units/Rail1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 2223 Publication Order Number:MC10H646/D

MC10H646, MC100H646Q4OGNDQ5OVTQ6OGNDQ7PIN NAMESQ3OGNDQ2OVTQ1OGND26272812325 24 23 22 21 20 19Pinout: 28–Lead PLCC(Top View)181716151413ENIVTIGNDVCCEVCCEVBBPINOGNDOVTIGNDIVTVEEVCCEECLK, ECLKVBBQ0–Q7ENFUNCTIONTTL Output Ground (0V)TTL Output VCC (+5.0V)Internal TTL GND (0V)Internal TTL VCC (+5.0V)ECL VEE (0V)ECL Ground (5.0V)Differential Signal Input(PECL)VBB Reference OutputSignal Outputs (TTL)Tri–State Enable Input (TTL)Q04125 6 7 8 9 10 11TCLKIVTIGNDVEEVEEVEEECLKECLKINTERNAL TTL POWERIVT01OVT01LOGIC DIAGRAMQ0AENQ0Q1INTERNAL TTL GROUNDFigure 1. Output StructureOGND0IGND01Q2700Power versus Frequency per BitTCLKECLKECLKQ3Q4Q5Q6POWER, mW600500400300200PDynamic = CL ƒ VSwing VCCPTotal = PStatic + PDynamic300pF200pF100pF50pFQ710000 20 40 60 80 100 120FREQUENCY, MHzNo LoadFigure 2. Power versus Frequency (Typical)TRUTH TABLETCLK ECLK ECLK EN QGNDGNDHLXLHGNDGNDXHLGNDGNDXL = Low Voltage Level; H = High Voltage Level; Z = TristateHHHHLLHHLZhttp://onsemi.com224

MC10H646, MC100H646DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVOH Output HIGH Voltage 2.6 ––2.6 ––2.6 ––VIOH = 24mAVOL Output LOW Voltage – 0.5 – 0.5 – 0.5 V IOL = 48mAIOS Output Short Circuit Current – – – – – – mA See Note 11. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device donot include a limiting IOS resistor.TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage2.00.82.00.82.00.8VIIH Input HIGH Current 201002010020100µA VIN = 2.7 VVIN = 7.0 VIIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 VVOH Output HIGH Voltage 2.52.02.52.02.52.0VIOH = –3.0 mAIOH = –24 mAVOL Output LOW Voltage 0.5 0.5 0.5 V IOL = 24 mAVIK Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18 mA10H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit NotesIIH Input HIGH Current 225 175 175 µAIIL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage 3.83 4.16 3.87 4.19 3.94 4.28 V IVT = IVO =VCCE = 5.0V (1)VIL Input LOW Voltage 3.05 3.52 3.05 3.52 3.05 3.555 V IVT = IVO =VCCE = 5.0V (1)VBBOutput ReferenceVoltage3.62 3.73 3.65 3.75 3.69 3.81 V IVT = IVO =VCCE = 5.0V (1)100H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit NotesIIH Input HIGH Current 225 175 175 µAIIL Input LOW Current 0.5 0.5 0.5 µAVIH Input HIGH Voltage 3.835 4.12 3.835 4.12 3.835 3.835 V IVT = IVO =VCCE = 5.0V (1)VIL Input LOW Voltage 3.19 3.525 3.19 3.525 3.19 3.525 V IVT = IVO =VCCE = 5.0V (1)VBBOutput ReferenceVoltage3.62 3.74 3.62 3.74 3.62 3.74 V IVT = IVO =VCCE = 5.0V (1)1. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = 5.0Vhttp://onsemi.com225

MC10H646, MC100H646DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Typ Max Min Max Unit ConditionICCLPower SupplyCurrent185 166 185 185 mA Total all OVT, IVT,and VCCE pinsICCH 175 154 175 175 mAICCZ 210 210 210AC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%)0°C 25°C 85°CSymbol Characteristic Min Max Min Max Min Max Unit ConditiontPLH Propagation Delay ECLK to QTCLK to Q4.85.15.86.45.05.36.06.45.65.76.67.0nstPHL Propagation Delay ECLK to QTCLK to Q4.44.75.46.04.44.85.45.94.85.25.86.5nstSK(O) Output Skew Q0, Q3, Q4, Q7Q1, Q2, Q5Q0–Q7350350500350350500350350500ps Note 1, 6tSK(PR) Process Skew ECLK to QTCLK to Q1.01.31.01.11.01.3ns Note 2, 6tSK(P) Pulse Skew ∆tPLH – tPHL 1.0 1.0 1.0 nstr, tf Rise/Fall Time 0.3 1.5 0.3 1.5 0.3 1.5 nstPW Output Pulse Width 66MHz @ 2.0V66MHz @ 0.8V60MHz @ 2.0V60MHz @ 0.8V5.55.56.06.05.55.56.06.05.55.56.06.0ns Note 3, 6tStability Clock Stability ±75 ±75 ±75 ps Note 4, 6FMAX Maximum Input Frequency 80 80 80 MHz Note 5, 61. Output skew defined for identical output transitions.2. Process skew is valid for VCC = 5.0V ±5%.3. Parameters guaranteed by tSK(P) and tr, tf specification limits.4. Clock stability is the period variation between two successive rising edges.5. For series terminated lines. See Applications section for FMAX enhancement techniques.6. All AC specifications tested driving 50Ω series terminated transmission lines at 80MHz.http://onsemi.com226

The MC10H/100H680 is a dual supply 4–bit differential ECL bus toTTL bus transceiver. It is designed to allow the system designer to nolonger be limited in bus speed associated with standard TTL busses.Using a differential ECL Bus will increase the frequency of operationand increase noise immunity.Both the TTL and the ECL ports are capable of driving a bus. TheECL outputs have the ability to drive 25 Ω, allowing both ends of thebus line to be terminated in the characteristic impedance of 50 Ω. TheTTL outputs are specified to source 15 mA and sink 48 mA, allowingthe ability to drive highly capacitive loads.The ECL output levels are VOH approximately equal to –1.0 V andVOL cutoff equal to –2.0 V (VTT). When the ECL ports are disabledboth EIOx and EIOxB go to the VOL cutoff level. The ECL inputreceivers have special circuitry which detects this disabled condition,prevents oscillation, and forces the TTL output to the low state. Thenoise margin in this disabled state is greater than 600 mV. MultipleECL VCCO pins are utilized to minimize switching noise.The TTL ports have standard levels. The TTL input receivers havePNP input devices to significantly reduce loading. Multiple TTLpower and ground pins are utilized to minimize switching noise.The control pins (EDIR and ECEB) of the 10H version iscompatible with MECL 10H ECL logic levels. The control pins of the100H version are compatible with 100K levels.• Differential ECL Bus (25 Ω) I/O Ports• High Drive TTL Bus I/O Ports• Extra TTL and ECL Power/Ground Pins to Minimize SwitchingNoise• Dual Supply• Direction and Chip Enable Control PinsPLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAM10H680AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H680FN PLCC–28 37 Units/RailMC100H680FN PLCC–28 37 Units/Rail1Pinout: 28–Lead PLCC (Top View)EIO0V CCO1EIO0BVEEEI01V CCO2EIO1BTIO2GT3VT2GT4TIO3TCEBECEBT1012625 24 23 22 21 20 1918EIO3BGT22717VCCO4VT12816EIO3GT1115VCCETIO0214EIO2BTDIR313VCCO3EDIR4 125 6 7 8 9 10 11EIO2© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7227 Publication Order Number:MC10H680/D

MC10H680, MC100H680PIN DESCRIPTIONSPin Symbol Function1 GT1 TTL Ground 12 TIO0 TTL I/O Bit 03 TDIR TTL Direction Control4 EDIR ECL Direction Control5 EIO0 ECL I/O Bit 06 VCCO1 ECL VCC 1 (0V) – Outputs7 EIO0B ECL I/O Bit 0 Bar8 VEE ECL Supply (–5.2/–4.5V)9 EIO1 ECL I/O Bit 110 VCCO2 ECL VCC 2 (0V) – Outputs11 EIO1B ECL I/O Bit 1 Bar12 EIO2 ECL I/O Bit 213 VCCO3 ECL VCC 3 (0V) – Outputs14 EIO2B ECL I/O Bit 2 Bar15 VCCE ECL VCC (0V)16 EIO3 ECL I/O Bit 317 VCCO4 ECL VCC 4 (0V) – Outputs18 EIO3B ECL I/O Bit 3 Bar19 ECEB ECL Chip Enable Bar Control20 TCEB TTL Chip Enable Bar Control21 TIO3 TTL I/O Bit 322 GT4 TTL Ground 423 VT2 TTL Supply 2 (5V)24 GT3 TTL Ground 325 TIO2 TTL I/O Bit 226 TIO1 TTL I/O Bit 127 GT2 TTL Ground 228 VT1 TTL Supply 1 (5V)TRUTH TABLETDIR — Direction Control TTL LevelsEDIR — Direction Control ECL LevelsTCEB — Chip Enable Bar Control TTL LevelsECEB — Chip Enable Bar Control ECL LevelsTIN — TTL InputTOUT — TTL OutputEIN — ECL InputEINB — ECL Input BarEOUT — ECL OutputEOUTB — ECL Output BarH — HIGHL — LOWLC — ECL Low Cutoff (VTT = –2.0 V)X — Don’t CareZ — High ImpedanceECEB TCEB EDIR TDIR EIN EINB EOUT EOUTB TIN TOUT COMMENTSH X X X X X LC LC X Z ECL and TTL Outputs DisabledX H X X X X LC LC X Z ECL and TTL Outputs DisabledL L H X H LC NA H ECL to TTL DirectionL L H X LC H NA L ECL to TTL DirectionL L H X LC LC NA L ECL to TTL Direction (L–L Cond.)L L X H H LC NA H ECL to TTL DirectionL L X H LC H NA L ECL to TTL DirectionL L X H LC LC NA L ECL to TTL Direction (L–L Cond.)L L L L NA NA H LC H TTL to ECL DirectionL L L L NA NA LC H L TTL to ECL Directionhttp://onsemi.com228

MC10H680, MC100H680ABSOLUTE RATINGS (Do not exceed):Power Supply Voltage VEE (ECL) –8.0 to 0 VdcPower Supply Voltage VCCT (TTL) –0.5 to +7.0 VdcInput VoltageVI (ECL)VI (TTL)0.0 to VEE–0.5 to +7.0VdcDisabled 3–State Output Vout (TTL) 0.0 to VCCT VdcOutput Source Current Continuous Iout (ECL) 100 mAdcOutput Source Current Surge Iout (ECL) 200 mAdcStorage Temperature Tstg –65 to 150 °COperating Temperature Tamb 0.0 to +75 °CECL DC CHARACTERISTICS: VCCT = + 5.0 V ±10%, VEE = – 5.2 ±5% (10H Version); VEE = – 4.2 V to – 5.5 V (100H Version)TA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionIEE Supply Current/ECL –110 –110 –110 mAIINH Input HIGH Current 225 145 145 µAIINL Input LOW Current 0.5 0.5 0.3 µAVOHVOLOutput HIGH VoltageOutput LOW Voltage–1100–2.1–840–2.03–1100–2.1CONTROL INPUTS ONLY10H ECL DC CHARACTERISTICS: VCCT = + 5.0 ±10%, VEE = – 5.2 ±5%–810–2.03–1100–2.1–735–2.03mVV25 Ω to – 2.1 VTA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage–1170–1950–840–1480–1130–1950–810–1480CONTROL INPUTS ONLY100H ECL DC CHARACTERISTICS: VCCT = + 5.0 ±10%, VEE = – 4.2 V to – 5.5 V–1070–1950–735–1450TA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage–1165–1810–880–1475–1165–1810–880–1475–1165–1810–880–1475mVmVhttp://onsemi.com229

MC10H680, MC100H680TTL DC CHARACTERISTICS: VCCT = + 5.0 V ±10%, VEE = – 5.2 ±5% (10H Version); VEE = – 4.2 V to – 5.5 V (100H Version)TA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionVIHVILStandard InputStandard Input2.00.8VIK Input Clamp –1.2 –1.2 –1.2 Vdc IIN = –18 mA2.00.82.00.8VdcVOHOutput HIGH VoltageOutput HIGH Voltage2.52.02.52.02.52.0VIOH = – 3.0 mAIOH = –15 mAVOL Output LOW Voltage 0.55 0.55 0.55 V IOL = 48 mAIIH*TTL (Input HIGH)TTL (Input HIGH)201002010020100µA Vin = 2.7 VVin = 7.0 VIIL* TTL (Input LOW) –0.6 –0.6 –0.6 mA Vin = 0.5 VICCL Supply Current 75 75 75 mAICCH Supply Current 70 70 70 mAICCZ Supply Current 70 70 70 mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0 V* NOTE: TTL Control Inputs onlyTTL I/O DC CHARACTERISTICS ONLYTA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionIIH/IOZHIIL/IOZLOutput DisableCurrentECL TO TTL DIRECTION / AC TEST702007020070200µA VOUT = 2.7 VVOUT = 0.5 VTA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Waveforms Min Max Min Max Min Max Unit ConditiontPLHtPHLtPZHtPZLtPHZtPLZtPZHtPZLtPHZtPLZPropagation Delayto OutputECEB to OutputEnable TimeECEB to OutputDisable TimeTCEB to OutputEnable TimeTCEB to OutputDisable Time2, 4 2.7 4.8 2.7 4.8 2.7 4.8 ns CL = 50 pF2, 5, 6 3.53.52, 5, 6 3.53.52, 5, 6 5.75.42, 5, 6 4.04.06.56.08.66.57.76.98.55.83.53.53.53.55.75.44.14.26.56.08.66.57.76.98.46.03.73.73.73.75.95.94.24.76.76.48.87.37.97.48.36.5nsnsnsnsCL = 50 pFCL = 50 pFCL = 50 pFCL = 50 pFtr/tf 1.0 to 2.0 Vdc 3 0.4 1.5 0.4 1.5 0.4 1.5 ns CL = 50 pFTTL TO ECL DIRECTION / AC TESTTA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Waveforms Min Max Min Max Min Max Unit ConditiontPLHtPHLPropagation Delayto Output1, 4 1.8 4.6 1.8 4.6 2.0 4.9 ns 25 Ω to – 2.0 VtPLHtPHLtPLHtPHLtr/tfECEBto OutputTCEBto OutputOutput Rise/FallTime 20% –80%1, 4 2.9 5.1 3.0 5.2 3.4 5.7 ns 25 Ω to – 2.0 V1, 4 3.4 6.3 3.5 6.6 3.8 7.4 ns 25 Ω to – 2.0 V1, 3 1.0 3.4 1.0 3.4 1.0 3.4 ns 25 Ω to – 2.0 Vhttp://onsemi.com230

MC10H680, MC100H680BLOCK DIAGRAMCONTROL INPUTSTDIREDIRTCEECEGND1EOETOEVCCEVEEVCCO1TTL I/OTIO0EIO0EIO0ECL I/OVCCT1GND2VCCO2TIO1EIO1EIO1GND3TIO2VCCO3EIO2EIO2VCCT2GND4TIO3VCCO4EIO3EIO3http://onsemi.com231

MC10H680, MC100H680SWITCHING CIRCUIT AND WAVEFORMSECLUSE 0.1 µF CAPACITORSFOR DECOUPLING.VEEVCC & VCCOTTL+7 V OPENPULSEGENERATOR50 Ω COAXUSE OSCILLOSCOPEINTERNAL 50 Ω LOADFOR TERMINATION.CH AIN50 Ω COAXDEVICEUNDERTESTOSCILLOSCOPEOUT50 ΩCH B50 Ω COAXDEVICEUNDERTESTtPZL, tPLZR1500 Ω50 pF R2500 ΩALLOTHERSFigure 1. Switching Circuit ECLFigure 2.ECL/TTLECL/TTL80%/2.0 V50%/1.5 VVINTPLHTPHLVOUT20%/1.0 VTPD++TPD––TRISETFALLVOUT50%/1.5 VFigure 3. WAVEFORMS: Rise and Fall TimesFigure 4. Propagation Delay — Single EndedTTLTTLVEVE1.5 V 1.5 V1.5 V 1.5 VVEVEVOUT1.5 VTPZLTPLZ0.3 VVOLVOUTTPZH1.5 VTPHZ0.3 V>VOH ≈3.5 VFigure 5. 3–State Output Low Enable andDisable TimesFigure 6. 3–State Output High Enable andDisable Timeshttp://onsemi.com232

The MC10/100H681 is a dual supply Hex ECL/TTL transceiverwith latches in both directions. ECL controlled Direction and ChipEnable Bar pins. There are two Latch Enable pins, one for eachdirection.The ECL outputs are single ended and drive 50 Ω. The TTL outputsare specified to source 15 mA and sink 48 mA, allowing the ability todrive highly capacitive loads. The high driving ability of the TTLoutputs make the device ideal for bussing applications.The ECL output levels are standard VOH and VOL cutoff equal to–2.0 V (VTT). When the ECL ports are disabled the outputs go to theVOL cutoff level. Multiple ECL VCCO pins are utilized to minimizeswitching noise.The TTL ports have standard levels. The TTL input receivers havePNP input devices to significantly reduce loading. Multiple TTLpower and ground pins are utilized to minimize switching noise.The 10H version is compatible with MECL 10H ECL logic levels.The 100H version is compatible with 100K levels.• Separate Latch Enable Controls for each Direction• ECL Single Ended 50 Ω I/O Port• High Drive TTL I/O Ports• Extra TTL and ECL Power/Ground Pins to Minimize SwitchingNoise• Dual Supply• Direction and Chip Enable Control PinsPLCC–28FN SUFFIXCASE 776http://onsemi.comMARKINGDIAGRAM10H681AWLYYWWA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10H681FN PLCC–28 37 Units/RailMC100H681FN PLCC–28 37 Units/Rail1Pinout: 28–Lead PLCC (Top View)TIO3VTGTTIO4VTGTTIO5TIO22625 24 23 22 21 20 1918EIO5VT2717VCCOGT2816EIO4TIO1115VCCEVT214EIO3GT313VCCOTIO04 125 6 7 8 9 10 11EIO2DIRCEBLEETLETEVEEEIO0EIO1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3233 Publication Order Number:MC10H681/D

MC10H681, MC100H681Pin Symbol Description1 TI01 TTL I/O BIT 12 VT TTL VCC (5.0 V)3 GTTTL GND (0 V)4 TI00 TTL I/O Bit 056DIRCEBDirection Control (ECL)Chip Enable Bar Control (ECL)7LEETLatch Enable ECL-TTL Control (ECL)8LETELatch Enable TTL-ECL Control (ECL)9VEEECL Supply (– 5.2/–4.5 5 V)10EI00ECL I/O BIT 011EI01ECL I/O BIT 112EI02ECL I/O BIT 213VCCOECL VCC (0 V) — Outputsuts14EIO3TTL I/O BIT 315VCCEECL VCC (0 V)16EIO4ECL I/O BIT 417 VCCO ECL VCC (0 V) — Outputs18EIO5ECL I/O BIT 519 TI05 TTL I/O BIT 520 GT TTL GND (0 V)21VTTTL VCC (5.0 V)22TI04TTL I/O BIT 423GTTTL GND (0 V)24VTTTL VCC (5.0 V)25TIO3TTL I/O BIT 326TIO2TTL I/O BIT 227VT28GTTTL VCC (5.0 V)TTL VCC (0 V)DIRTOECEEOEDQ6EIOLE-TETIO6QDLELE-ETTRUTH TABLECEB DIR LEET LETE EOUT TOUTH X X X Z ZL H L L Z EINL H H L Z QoL L L L TIN ZL L L H Qo Z• Hex• Bi-Directional• ECL/TTL Translation• Dual Supply• ECL Outputs, 50 Ohm S.E., VOH/Cutoff• TTL Outputs, 48 mA Sink, 15 mA Source• Multi Power and Ground Pins• Separate LE Controlshttp://onsemi.com234

MC10H681, MC100H681ECL DC CHARACTERISTICS: VCCT = + 5.0 V ±10%, VEE = – 5.2 ±5% (10H Version); VEE = – 4.2 V to – 5.5 V (100H Version)TA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionIEE Supply Current/ECL — –113 — –113 — –113 mAIINH Input HIGH Current — 225 — 145 — 145 µAIINL Input LOW Current 0.5 — 0.5 — 0.3 — µAVOHVOLOutput HIGH VoltageOutput LOW Voltage–1020–2.1–840–2.03–980–2.1–810–2.03–920–2.1–735–2.03mVV50 Ω to – 2.1 V10H ECL DC CHARACTERISTICS: VCCT = + 5.0 ±10%, VEE = – 5.2 ±5%TA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage–1170–1950–840–1480–1130–1950–810–1480–1070–1950–735–1450mV100H ECL DC CHARACTERISTICS: VCCT = + 5.0 ±10%, VEE = – 4.2 V to – 5.5 VTA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionVIHVILInput HIGH VoltageInput LOW Voltage–1165–1810–880–1475–1165–1810–880–1475–1165–1810–880–1475mVABSOLUTE RATINGS (Do not exceed):Power Supply Voltage VEE (ECL) –8.0 to 0 VdcPower Supply Voltage VCCT (TTL) –0.5 to + 7.0 VdcInput VoltageVI (ECL)VI (TTL)0.0 to VEE–0.5 to + 7.0VdcDisabled 3-State Output Vout (TTL) 0.0 to VCCT VdcOutput Source Current Continuous Iout (ECL) 100 mAdcOutput Source Current Surge Iout (ECL) 200 mAdcStorage Temperature Tstg –65 to 150 °COperating Temperature Tamb 0.0 to + 75 °Chttp://onsemi.com235

MC10H681, MC100H681TTL DC CHARACTERISTICS: VCCT = + 5.0 V ±10%, VEE = – 5.2 ±5% (10H Version); VEE = – 4.2 V to – 5.5 V (100H Version)TA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditionVIHVILStandard InputStandard Input2.0——0.8VIK Input Clamp — –1.2 — –1.2 — –1.2 Vdc IIN = –18 mA2.0——0.82.0——0.8VdcVOHOutput HIGH VoltageOutput HIGH Voltage2.52.0——2.52.0——2.52.0——VIOH = – 3.0 mAIOH = –15 mAVOL Output LOW Voltage — 0.55 — 0.55 — 0.55 V IOL = 48 mAIIH/IOZHIIL/IOZLOutput DisableCurrent——70200——70200——70200µA VOUT = 2.7 VVOUT = 0.5 VICCL Supply Current — 63 — 63 — 63 mAICCH Supply Current — 63 — 63 — 63 mAICCZ Supply Current — 63 — 63 — 63 mAIOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0 VECL TO TTL DIRECTION AC CHARACTERISTICSTA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditiontPLHtPHLPropagationDelay to Output4.0 7.8 4.0 7.8 4.2 8.0 ns CL = 50 pFtPLHtPHLLEET toOutput5.55.58.37.65.55.58.37.65.75.88.58.0nsCL = 50 pFtPZHtPZLCEB to OutputEnable Time5.55.38.38.35.55.38.38.34.75.48.58.4nsCL = 50 pFtPHZtPLZCEB to OutputDisable Time3.53.57.25.33.53.57.25.33.74.17.35.8nsCL = 50 pFtr/tf 1.0 Vdc to 2.0 Vdc 0.4 2.2 0.4 2.2 0.4 2.2 ns CL = 50 pFTTL TO ECL DIRECTION AC CHARACTERISTICSTA = 0°C TA = 25°C TA = 75°CTestSymbol Parameter Min Max Min Max Min Max Unit ConditiontPLHtPHLPropagationDelay to Output1.9 3.9 1.9 3.9 2.2 4.4 ns 50 Ω to – 2.0 VtPHLtPLHCEB toOutput2.22.34.04.62.22.34.04.62.52.74.35.0ns50 Ω to – 2.0 VtPHLtPLHtr/tfLETE toOutputOutput Rise/FallTime 20% –80%2.4 3.9 2.4 3.9 2.7 4.3 ns 50 Ω to – 2.0 V0.4 2.2 0.4 2.2 0.4 2.2 ns 50 Ω to – 2.0 Vhttp://onsemi.com236

MC10H681, MC100H681TEST CIRCUITS AND WAVEFORMSPULSEGENERATORECLUSE 0.1 µF CAPACITORSFOR DECOUPLING.50 Ω COAXUSE OSCILLOSCOPEINTERNAL 50 Ω LOADFOR TERMINATION.CH AIN50 Ω COAXVEEDEVICEUNDERTESTOSCILLOSCOPEVCC & VCCOOUTCH B50 Ω COAXTTLDEVICEUNDERTESTtPZL, tPLZ+7 V OPENR1500 Ω50 pF R2500 ΩALLOTHERSFigure 1. Test Circuit ECLFigure 2. Test Circuit TTLECL/TTLECL/TTL80%/2.0 V50%/1.5 VVINVOUT20%/1.0 VTPD++ TPD – –TRISETFALLVOUT50%/1.5 VFigure 3. Rise and Fall TimesFigure 4. Propagation Delay — Single EndedTTLTTLVEVE1.5 V 1.5 V1.5 V 1.5 VVEVEVOUT1.5 VTPZLTPLZ0.3 VVOLVOUTTPZL1.5 VTPHZ0.3 V> VOH≈3.5 VFigure 5. 3-State Output Low Enableand Disable TimesFigure 6. 3-State Output High Enableand Disable Timeshttp://onsemi.com237

http://onsemi.com238CHAPTER 3MECL 10K Data Sheets

MECL 10KINTEGRATED CIRCUITSMC10,100/10,200 Series–30 to 85°CFunction Selection — (–30° to +85°C)Function Device CaseNOR GatesQuad 2-Input Gate MC10102 620, 648, 775Triple 4-3-3 Input Gate MC10106 620, 648, 775Dual 3-Input 3-Output Gate MC10111 620, 648Dual 3-Input 3-Output Gate MC10211 620, 648, 775OR GatesQuad 2-Input Gate MC10103 620, 648, 775Dual 3-Input 3-Output Gate MC10110 620, 648Dual 3-Input 3-Output Gate MC10210 620, 648, 775AND GatesQuad 2-Input Gate MC10104 620, 648, 775Hex Gate MC10197 620, 648, 775Complex GatesQuad OR/NOR Gate MC10101 620, 648, 775Triple 2-3-2 Input OR/NOR Gate MC10105 620, 648, 775Dual 4-5 Input OR/NOR Gate MC10109 620, 648, 775Dual 3-Input 3-Output OR/NOR Gate MC10212 648, 775Triple 2-Input Exclusive OR/NOR Gate MC10107 620, 648, 775Quad 2-Input Exclusive OR/NOR Gate MC10113 620, 648, 775Dual 2-Wide 2-3 Input OR-AND/OR-AND MC10117 620, 648, 775INVERT4-Wide 3-Input OR-AND/OR-AND MC10121 620, 648, 775INVERTBuffers/InvertersHex Buffer/Enable MC10188 620, 648, 775Hex Inverter/Enable MC10189 620, 648, 775Hex Inverter/Buffer MC10195 620, 648, 775Line Drivers/Line ReceiversTriple Line Receiver MC10114 620, 648, 775Quad Line Receiver MC10115 620, 648, 775Triple Line Receiver MC10116 620, 648, 775Triple Bus Driver MC10123 620, 648, 775Quad Bus Receiver MC10129 620Quad Bus Driver MC10192 620, 648, 775Triple Line Receiver MC10216 620, 648, 775TranslatorsQuad TTL-MECL MC10124 620, 648, 775Quad MECL-TTL MC10125 620, 648, 775Function Device CaseFlip-Flop/LatchesDual D Master Slave Flip-Flop MC10131 620, 648, 775Dual J-K Master Slave Flip-Flop MC10135 620, 648, 775Quad Latch MC10153 620, 648, 775Hex D Master Slave Flip-Flop MC10176 620, 648, 775Hex D Common Reset Flip-Flop MC10186 620, 648, 775Dual D Master Slave Flip-Flop MC10231 620, 648, 775Quad Latch MC10133 620, 648Quint Latch MC10175 620, 648, 775Quad/Common Clock Latch MC10168 648Encoders8-Input Encoder MC10165 620, 648DecodersBinary to 1-8 (Low) MC10161 620, 648, 775Binary to 1-8 (High) MC10162 620, 648, 775Dual Binary to 1-4 (Low) MC10171 620, 648, 775Dual Binary to 1-4 (High) MC10172 620, 648, 775Parity Generator/Checkers12-Bit Parity Generator-Checker MC10160 620, 6489 + 2 Bit Parity MC10170 620, 648CountersHexadecimal MC10136 620, 648, 775Decade MC10137 620, 648Biquinary MC10138 620, 648, 775Binary Down Counter MC10154 620, 648Binary MC10178 620, 648, 775Arithmetic Functions5-Bit Magnitude Comparator MC10166 620, 648, 7754-Bit Arithmetic Function Gen. MC10181 623Shift Register4-Bit Universal MC10141 620, 648, 775MultivibratorsMonostable Multivibrators MC10198 620, 648, 775MultiplexerDual with Latch MC10134 620, 648, 775Quad 2-Input/Noninverting MC10158 620, 648, 775Quad 2-Input/Inverting MC10159 620, 648, 7758-Line MC10164 620, 648, 775Quad 2-Input/Latch MC10173 620, 648, 775Dual 4-1 MC10174 620, 648, 775http://onsemi.com239

The MC10101 is a quad 2–input OR/NOR gate with one input fromeach gate common to pin 12.• PD = 25 mW typ/gate (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.com471013LOGIC DIAGRAM12 9VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT2536141115CDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10101LAWLYYWWMC10101PAWLYYWW110101AWLYYWWVCC1AOUT121615VCC2DOUTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekBOUT314COUTAINAOUT451312DINCOMMONINPUTORDERING INFORMATIONDevice Package ShippingBOUT611COUTMC10101L CDIP–16 25 Units / RailBINVEE78109CINDOUTMC10101P PDIP–16 25 Units / RailMC10101FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6240 Publication Order Number:MC10101/D

MC10101ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 29 20 26 29 mAdcInput Current IinH 412IinL 412Output Voltage Logic 1 VOH 5522Output Voltage Logic 0 VOL 5522Threshold Voltage Logic 1 VOHA 5522Threshold Voltage Logic 0 VOLA 5522Switching Times (50Ω Load)Propagation Delayt4+2–t4–2+t4+5+t4–5–Rise Time (20 to 80%) t2+t5+Fall Time (20 to 80%) t2–t5–225525250.50.5–1.060–1.060–1.060–1.060–1.890–1.890–1.890–1.890–1.080–1.080–1.080–1.0801.01.01.01.01.11.11.11.1425850–0.890–0.890–0.890–0.890–1.675–1.675–1.675–1.675–1.655–1.655–1.655–1.6553.13.13.13.13.63.63.63.60.50.5–0.960–0.960–0.960–0.960–1.850–1.850–1.850–1.850–0.980–0.980–0.980–0.9801.01.01.01.01.11.11.11.12.02.02.02.02.02.02.02.0265535–0.810–0.810–0.810–0.810–1.650–1.650–1.650–1.650–1.630–1.630–1.630–1.6302.92.92.92.93.33.33.33.30.30.3–0.890–0.890–0.890–0.890–1.825–1.825–1.825–1.825–0.910–0.910–0.910–0.9101.01.01.01.01.11.11.11.1265535–0.700–0.700–0.700–0.700–1.615–1.615–1.615–1.615–1.595–1.595–1.595–1.5953.33.33.33.33.73.73.73.7µAdcµAdcVdcVdcVdcVdcnshttp://onsemi.com241

MC10101ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 412IinL 412Output Voltage Logic 1 VOH 5522Output Voltage Logic 0 VOL 5522Threshold Voltage Logic 1 VOHA 5522Threshold Voltage Logic 0 VOLA 552241212412441288888888(VCC)GndSwitching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+2–t4–2+t4+5+t4–5–Rise Time (20 to 80%) t2+t5+Fall Time (20 to 80%) t2–t5–22552525Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.1241244444444412412422552525888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com242

The MC10102 is a quad 2–input NOR gate. The MC10102 providesone gate with OR/NOR outputs.• PD = 25 mW typ/gate (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.com456710111213LOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT2314159CDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10102LAWLYYWWMC10102PAWLYYWW110102AWLYYWWVCC1AOUTBOUT123161514VCC2DOUTCOUTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAIN413DINAIN512DINORDERING INFORMATIONBIN611CINDevice Package ShippingBIN710CINMC10102L CDIP–16 25 Units / RailVEE89DOUTMC10102P PDIP–16 25 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.MC10102FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6243 Publication Order Number:MC10102/D

MC10102ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 29 20 26 29 mAdcInput Current IinH 12 425 265 265 µAdcOutput Voltage Logic 1 VOH 991515Output Voltage Logic 0 VOL 991515Threshold Voltage Logic 1 VOHA 991515Threshold Voltage Logic 0 VOLA 991515Switching Times (50Ω Load)Propagation DelayIinL 12 0.5 0.5 0.3 µAdct12+15–t12–15+t12+9+t12–9–Rise Time (20 to 80%) t15+t9+Fall Time (20 to 80%) t15–t9–151599159159–1.060–1.060–1.060–1.060–1.890–1.890–1.890–1.890–1.080–1.080–1.080–1.0801.01.01.01.01.11.11.11.1–0.890–0.890–0.890–0.890–1.675–1.675–1.675–1.675–1.655–1.655–1.655–1.6553.13.13.13.13.63.63.63.6–0.960–0.960–0.960–0.960–1.850–1.850–1.850–1.850–0.980–0.980–0.980–0.9801.01.01.01.01.11.11.11.12.02.02.02.02.02.02.02.0–0.810–0.810–0.810–0.810–1.650–1.650–1.650–1.650–1.630–1.630–1.630–1.6302.92.92.92.93.33.33.33.3–0.890–0.890–0.890–0.890–1.825–1.825–1.825–1.825–0.910–0.910–0.910–0.9101.01.01.01.01.11.11.11.1–0.700–0.700–0.700–0.700–1.615–1.615–1.615–1.615–1.595–1.595–1.595–1.5953.33.33.33.33.73.73.73.7VdcVdcVdcVdcnshttp://onsemi.com244

MC10102ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 12 12 8 1, 16Output Voltage Logic 1 VOH 991515Output Voltage Logic 0 VOL 991515Threshold Voltage Logic 1 VOHA 991515Threshold Voltage Logic 0 VOLA 991515(VCC)GndIinL 12 12 8 1, 1612131213Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt12+15–t12–15+t12+9+t12–9–Rise Time (20 to 80%) t15+t9+Fall Time (20 to 80%) t15–t9–151599159159Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.121312131212121212121212121312131515991591598888888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com245

The MC10103 is a quad 2–input OR gate. The MC10103 providesone gate with OR/NOR outputs.• PD = 25 mW typ/gate (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.com456712131011LOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 82315914CDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10103LAWLYYWWMC10103PAWLYYWW1DIPPIN ASSIGNMENTPLCC–20FN SUFFIXCASE 77510103AWLYYWWVCC1AOUTBOUT123161514VCC2COUTDOUTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAINAINBINBINVEE45678131211109CINCINDINDINCOUTORDERING INFORMATIONDevice Package ShippingMC10103L CDIP–16 25 Units / RailMC10103P PDIP–16 25 Units / RailMC10103FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6246 Publication Order Number:MC10103/D

MC10103ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 29 21 26 29 mAdcInput Current IinH 4* 390 245 245 µAdcOutput Voltage Logic 1 VOH 29Output Voltage Logic 0 VOL 29Threshold Voltage Logic 1 VOHA 29Threshold Voltage Logic 0 VOLA 29Switching Times (50Ω Load)Propagation DelayIinL 4* 0.5 0.5 0.3 µAdct4+2+t12+9–29–1.060–1.060–1.890–1.890–1.080–1.0801.01.0–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.1 3.6 1.1 2.0 3.3 1.1 3.7Fall Time (20 to 80%) t2– 2 1.1 3.6 1.1 2.0 3.3 1.1 3.7* Individually test each input applying VIH or VIL to input under test.3.13.11.01.02.02.02.92.91.01.0–0.700–0.700–1.615–1.615–1.595–1.5953.33.3VdcVdcVdcVdcnshttp://onsemi.com247

MC10103ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 4* 4* 8 1, 16Output Voltage Logic 1 VOH 29Output Voltage Logic 0 VOL 29 12, 13Threshold Voltage Logic 1 VOHA 29(VCC)GndIinL 4* 4* 8 1, 164.5 88Threshold Voltage Logic 0 VOLA 29 12, 134, 512, 1388884, 5 88Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+2+t12+9–29Rise Time (20 to 80%) t2+ 2 4 2 8 1, 16Fall Time (20 to 80%) t2– 2 4 2 8 1, 16* Individually test each input applying VIH or VIL to input under test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.41229881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com248

The MC10104 is a quad 2–input AND gate. One of the gates hasboth AND/NAND outputs available.• PD = 35 mW typ/gate (No Load)• tpd = 2.7 ns typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.com4567LOGIC DIAGRAM23CDIP–16L SUFFIXCASE 62016MARKINGDIAGRAMSMC10104LAWLYYWW10111213VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 814915PDIP–16P SUFFIXCASE 6481161MC10104PAWLYYWW1DIPPIN ASSIGNMENTPLCC–20FN SUFFIXCASE 77510104AWLYYWWVCC1AOUTBOUT123161514VCC2DOUTCOUTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAINAINBINBINVEE45678131211109DINDINCINCINDOUTORDERING INFORMATIONDevice Package ShippingMC10104L CDIP–16 25 Units / RailMC10104P PDIP–16 25 Units / RailMC10104FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6249 Publication Order Number:MC10104/D

MC10104ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 39 35 39 mAdcInput Current IinH* 1213Output Voltage Logic 1 VOH 159Output Voltage Logic 0 VOL 159Threshold Voltage Logic 1 VOHA 991515Threshold Voltage Logic 0 VOLA 991515Switching Times (50Ω Load)Propagation Delay425350265220265220µAdcIinL 12 0.5 0.5 0.3 µAdct12+15+t12–15–t12+9–t12–9+t13+15+t13+9–Rise Time (20 to 80%) t15+t9+Fall Time (20 to 80%) t15–t9–151599159159159–1.060–1.060–1.890–1.890–1.090–1.090–1.090–1.0901.01.01.01.01.01.01.51.51.51.5* Inputs 4, 7, 10 and 13 will behave similarly for ac and IinH values.Inputs 5, 6, 11 and 12 will behave similarly for ac and IinH values.–0.890–0.890–1.675–1.675–1.655–1.655–1.655–1.6554.34.34.34.34.34.33.73.73.73.7–0.960–0.960–1.850–1.850–0.980–0.980–0.980–0.9801.01.01.01.01.01.01.51.51.51.52.22.22.22.22.72.72.02.02.02.0–0.810–0.810–1.650–1.650–1.630–1.630–1.630–1.6304.04.04.04.04.04.03.53.53.53.5–0.890–0.890–1.825–1.825–0.910–0.910–0.910–0.9101.01.01.01.01.01.01.51.51.51.5–0.700–0.700–1.615–1.615–1.595–1.595–1.595–1.5954.24.24.24.24.24.23.63.63.63.6VdcVdcVdcVdcnshttp://onsemi.com250

MC10104ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH* 1213Output Voltage Logic 1 VOH 15912, 1313Output Voltage Logic 0 VOL 159 12, 13Threshold Voltage Logic 1 VOHA 991515Threshold Voltage Logic 0 VOLA 99151588(VCC)Gnd1, 161, 16IinL 12 12 8 1, 1612, 13 8812131213Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt12+15+t12–15–t12+9–t12–9+t13+15+t13+9–Rise Time (20 to 80%) t15+t9+1515991591591313131312121212Fall Time (20 to 80%) t15– 15 12t9– 9 12* Inputs 4, 7, 10 and 13 will behave similarly for ac and IinH values.Inputs 5, 6, 11 and 12 will behave similarly for ac and IinH values.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.131213121212121213131313131312131213151599159159159888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com251

The MC10105 is a triple 2–3–2 input OR/NOR gate.• PD = 30 mW typ/gate (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.comLOGIC DIAGRAM4 35 29101113 1412 15VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT67CDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10105LAWLYYWWMC10105PAWLYYWW110105AWLYYWWVCC1AOUTAOUT123161514VCC2COUTCOUTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAINAINBOUTBOUTVEE45678131211109CINCINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.BINBINBINORDERING INFORMATIONDevice Package ShippingMC10105L CDIP–16 25 Units / RailMC10105P PDIP–16 25 Units / RailMC10105FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6252 Publication Order Number:MC10105/D

MC10105ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 23 17 21 23 mAdcInput Current IinH 4 425 265 265 µAdcOutput Voltage Logic 1 VOH 32Output Voltage Logic 0 VOL 32Threshold Voltage Logic 1 VOHA 32Threshold Voltage Logic 0 VOLA 32Switching Times (50Ω Load)Propagation DelayIinL 4 0.5 0.5 0.3 µAdct4+3–t4–3+t4+2+t4–2–Rise Time (20 to 80%) t3+t2+Fall Time (20 to 80%) t3–t2–33223232–1.060–1.060–1.890–1.890–1.080–1.0801.01.01.01.01.11.11.11.1–0.890–0.890–1.675–1.675–1.655–1.6553.13.13.13.13.63.63.63.6–0.960–0.960–1.850–1.850–0.980–0.9801.01.01.01.01.11.11.11.12.02.02.02.02.02.02.02.0–0.810–0.810–1.650–1.650–1.630–1.6302.92.92.92.93.33.33.33.3–0.890–0.890–1.825–1.825–0.910–0.9101.01.01.01.01.11.11.11.1–0.700–0.700–1.615–1.615–1.595–1.5953.33.33.33.33.73.73.73.7VdcVdcVdcVdcnshttp://onsemi.com253

MC10105ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 4 4 8 1, 16Output Voltage Logic 1 VOH 32 4Output Voltage Logic 0 VOL 32(VCC)GndIinL 4 4 8 1, 164 88Threshold Voltage Logic 1 VOHA 32 4Threshold Voltage Logic 0 VOLA 32884 88Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+3–t4–3+t4+2+t4–2–Rise Time (20 to 80%) t3+t2+Fall Time (20 to 80%) t3–t2–33223232Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.44444444443322323288888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com254

The MC10106 is a triple 4–3–3 input NOR gate.• PD = 30 mW typ/gate (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.com4567LOGIC DIAGRAM910 2111213 1514VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 83CDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10106LAWLYYWWMC10106PAWLYYWW110106AWLYYWWVCC1BOUTDIPPIN ASSIGNMENT121615VCC2COUTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAOUTAINAINAIN345614131211CINCINCINBINORDERING INFORMATIONDevice Package ShippingMC10106L CDIP–16 25 Units / RailAIN710BINMC10106P PDIP–16 25 Units / RailVEE89BINMC10106FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6255 Publication Order Number:MC10106/D

MC10106ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 23 17 21 23 mAdcInput Current IinH 4 425 265 265 µAdcOutput Voltage Logic 1 VOH 32Output Voltage Logic 0 VOL 32Threshold Voltage Logic 1 VOHA 32Threshold Voltage Logic 0 VOLA 32Switching Times (50Ω Load)Propagation DelayIinL 4 0.5 0.5 0.3 µAdct4+3–t4–3+33–1.060–1.060–1.890–1.890–1.080–1.0801.01.0–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t3+ 3 1.1 3.6 1.1 2.0 3.3 1.1 3.7Fall Time (20 to 80%) t3– 3 1.1 3.6 1.1 2.0 3.3 1.1 3.73.13.11.01.02.02.02.92.91.01.0–0.700–0.700–1.615–1.615–1.595–1.5953.33.3VdcVdcVdcVdcnsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 4 4 8 1, 16Output Voltage Logic 1 VOH 32Output Voltage Logic 0 VOL 32Threshold Voltage Logic 1 VOHA 32Threshold Voltage Logic 0 VOLA 32(VCC)GndIinL 4 4 8 1, 1649Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+3–t4–3+33Rise Time (20 to 80%) t3+ 3 4 3 8 1, 16Fall Time (20 to 80%) t3– 3 4 3 8 1, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.4944493388888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com256

The MC10107 is a triple–2 input exclusive OR/NOR gate.• PD = 40 mW typ/gate (No Load)• tpd = 2.8 ns typ• tr, tf = 2.5 ns typ (20%–80%)http://onsemi.com459714LOGIC DIAGRAM15 133 = (4 • 5) + (4 • 5)2 = (4 • 5) + (4 • 5)VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT23111012CDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10107LAWLYYWWMC10107PAWLYYWW110107AWLYYWWVCC1AOUTAOUT123161514VCC2CINCINA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAINAIN*NCBIN456713121110COUTCOUTBOUTBOUTORDERING INFORMATIONDevice Package ShippingMC10107L CDIP–16 25 Units / RailVEE89BINMC10107P PDIP–16 25 Units / Rail*NC = No ConnectionMC10107FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6257 Publication Order Number:MC10107/D

MC10107ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 31 28 31 mAdcInput Current IinH 4, 9, 145, 7, 15Output Voltage Logic 1 VOH 2233Output Voltage Logic 0 VOL 2233Threshold Voltage Logic 1 VOHA 2233Threshold Voltage Logic 0 VOLA 2233425350265220265220µAdcIinL * 0.5 0.5 0.3 µAdc–1.060–1.060–1.060–1.060–1.890–1.890–1.890–1.890–1.080–1.080–1.080–1.080–0.890–0.890–0.890–0.890–1.675–1.675–1.675–1.675–1.655–1.655–1.655–1.655–0.960–0.960–0.960–0.960–1.850–1.850–1.850–1.850–0.980–0.980–0.980–0.980–0.810–0.810–0.810–0.810–1.650–1.650–1.650–1.650–1.630–1.630–1.630–1.630–0.890–0.890–0.890–0.890–1.825–1.825–1.825–1.825–0.910–0.910–0.910–0.910–0.700–0.700–0.700–0.700–1.615–1.615–1.615–1.615–1.595–1.595–1.595–1.595Switching Times (50Ω Load) Min Typ Max nsPropagation Delayt++t+ –t–+t– –t++t+ –t–+t– –Inputs4,9 or 14to eitherOutputInputs5,7 or 15to eitherOutput–1.11.11.11.11.11.11.11.1Rise Time (20 to 80%) t+ ** 1.1 3.5 1.1 2.5 3.5 1.1 3.8Fall Time (20 to 80%) t– ** 1.1 3.5 1.1 2.5 3.5 1.1 3.8* Individually test each input applying VIH or VIL to input under test.** Any Output.3.83.83.83.83.83.83.83.81.11.11.11.11.11.11.11.12.02.02.02.02.82.82.82.83.73.73.73.73.73.73.73.71.11.11.11.11.11.11.11.14.04.04.04.04.04.04.04.0VdcVdcVdcVdchttp://onsemi.com258

MC10107ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 5, 7, 15 8 1, 16Input Current IinH 4, 9, 145, 7, 15Output Voltage Logic 1 VOH 2233Output Voltage Logic 0 VOL 2233Threshold Voltage Logic 1 VOHA 2233Threshold Voltage Logic 0 VOLA 2233**88(VCC)Gnd1, 161, 16IinL * * 8 1, 164, 545454, 55 45Switching Times (50Ω Load) +1.1V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt++t+ –t–+t– –t++t+ –t–+t– –Inputs4,9 or 14to eitherOutputInputs5,7 or 15to eitherOutput5, 7, 155, 7, 155, 7, 155, 7, 154, 9, 144, 9, 144, 9, 144, 9, 1445454Input4, 9 or14Input5, 7 or1544CorrespondingXOR/XNOROutputsCorrespondingXOR/XNOROutputsRise Time (20 to 80%) t+ ** 4, 9, 14 Any Input Corresponding 8 1, 16XOR/XNORFall Time (20 to 80%) t– ** 4, 9, 14 Any Input Outputs 8 1, 16* Individually test each input applying VIH or VIL to input under test.** Any Output.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.8888888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com259

The MC10109 is a dual 4–5 input OR/NOR gate.• PD = 30 mW typ/gate (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.com4LOGIC DIAGRAM5 3627910111213VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 81415CDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10109LAWLYYWWMC10109PAWLYYWW110109AWLYYWWVCC1AOUTDIPPIN ASSIGNMENT121615VCC2BOUTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAOUTAINAINAINAIN345671413121110BOUTBINBINBINBINORDERING INFORMATIONDevice Package ShippingMC10109L CDIP–16 25 Units / RailMC10109P PDIP–16 25 Units / RailVEE89BINMC10109FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6260 Publication Order Number:MC10109/D

MC10109ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 15 11 14 15 mAdcInput Current IinH 4 425 265 265 µAdcOutput Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23Switching Times (50Ω Load)Propagation DelayIinL 4 0.5 0.5 0.3 µAdct4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–22332323–1.060–1.060–1.890–1.890–1.080–1.0801.01.01.01.01.11.11.11.1–0.890–0.890–1.675–1.675–1.655–1.6553.73.73.73.74.04.04.04.0–0.960–0.960–1.850–1.850–0.980–0.9801.01.01.01.01.11.11.11.12.02.02.02.02.02.02.02.0–0.810–0.810–1.650–1.650–1.630–1.6302.92.92.92.93.33.33.33.3–0.890–0.890–1.825–1.825–0.910–0.9101.01.01.01.01.11.11.11.1–0.700–0.700–1.615–1.615–1.595–1.5953.73.73.73.74.04.04.04.0VdcVdcVdcVdcnshttp://onsemi.com261

MC10109ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 4 4 8 1, 16Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23 4Threshold Voltage Logic 1 VOHA 23(VCC)GndIinL 4 4 8 1, 164 88Threshold Voltage Logic 0 VOLA 23 44488884 88Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–22332323Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.4444444422332323888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com262

The ability to control three parallel lines from a single point makesthe MC10110 particularly useful in clock distribution applicationswhere minimum clock skew is desired. Three VCC pins are providedand each one should be used.• PD = 80 mW typ/pkg (No Load)• tpd = 2.4 ns typ (All Outputs Loaded)• tr, tf = 2.2 ns typ (20%–80%)567LOGIC DIAGRAM10 9 12111314VCC1 = PIN 1, 15VCC2 = PIN 16VEE = PIN 8234http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10110LAWLYYWWMC10110PAWLYYWW110101AWLYYWWVCC1AOUTDIPPIN ASSIGNMENT121615VCC2VCC1A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAOUTAOUTAINAINAINVEE34567814131211109BOUTBOUTBOUTBINBINBINORDERING INFORMATIONDevice Package ShippingMC10110L CDIP–16 25 Units / RailMC10110P PDIP–16 25 Units / RailMC10110FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7263 Publication Order Number:MC10110/D

MC10110ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 42 30 38 42 mAdcInput Current IinH 5, 6, 7 680 425 425 µAdcOutput Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234Switching Times (50Ω Load)Propagation DelayIinL 5, 6, 7 0.5 0.5 0.3 µAdct5+2+t5–2–t5+3+t5–3–t5+4+t5–4–Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–223344234234–1.060–1.060–1.060–1.890–1.890–1.890–1.080–1.080–1.0801.41.41.41.41.41.41.01.01.01.01.01.0–0.890–0.890–0.890–1.675–1.675–1.675–1.655–1.655–1.6553.53.53.53.53.53.53.53.53.53.53.53.5–0.960–0.960–0.960–1.850–1.850–1.850–0.980–0.980–0.9801.41.41.41.41.41.41.11.11.11.11.11.12.42.42.42.42.42.42.22.22.22.22.22.2–0.810–0.810–0.810–1.650–1.650–1.650–1.630–1.630–1.6303.53.53.53.53.53.53.53.53.53.53.53.5–0.890–0.890–0.890–1.825–1.825–1.825–0.910–0.910–0.9101.51.51.51.51.51.51.21.21.21.21.21.2–0.700–0.700–0.700–1.615–1.615–1.615–1.595–1.595–1.5953.83.83.83.83.83.83.83.83.83.83.83.8VdcVdcVdcVdcnshttp://onsemi.com264

MC10110ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWCharacteristicSymbolUnderTest VIHmax VILmin VIHAmin VILAmax VEE(VCC)GndPower Supply Drain Current IE 8 8 1, 15, 16Input Current IinH 5, 6, 7 * 8 1, 15, 16Output Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234IinL 5, 6, 7 * 8 1, 15, 165675675678888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt5+2+t5–2–t5+3+t5–3–t5+4+t5–4–Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–* Individually test each input using the pin connections shown.2233442342345555555555552233442342348888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com265

The MC10111 is designed to drive up to three transmission linessimul– taneously. The multiple outputs of this device also allow thewire “OR”–ing of several levels of gating for minimization of gate andpackage count.The ability to control three parallel lines from a single point makesthe MC10111 particularly useful in clock distribution applicationswhere minimum clock skew is desired. Three VCC pins are providedand each one should be used.• PD = 80 mW typ/gate (No Load)• tpd = 2.4 ns typ (All Outputs Loaded)• tr, tf = 2.2 ns typ (20%–80%)567LOGIC DIAGRAMVCC1 = PIN 1,15VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT1210 9 131411234http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10111LAWLYYWWMC10111PAWLYYWW110111AWLYYWWVCC1AOUTAOUTAOUTAIN123451615141312VCC2VCC1BOUTBOUTBOUTORDERING INFORMATIONDevice Package ShippingMC10111L CDIP–16 25 Units / RailMC10111P PDIP–16 25 Units / RailMC10111FN PLCC–20 46 Units / RailAIN611BINAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7266 Publication Order Number:MC10111/D

MC10111ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 42 30 38 42 mAdcInput Current IinH 5, 6, 7 680 425 425 µAdcOutput Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234Switching Times (50Ω Load)Propagation DelayIinL 5, 6, 7 0.5 0.5 0.3 µAdct5+2–t5–2+t5+3–t5–3+t5+4–t5–4+Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–223344234234–1.060–1.060–1.060–1.890–1.890–1.890–1.080–1.080–1.0801.41.41.41.41.41.41.01.01.01.01.01.0–0.890–0.890–0.890–1.675–1.675–1.675–1.655–1.655–1.6553.53.53.53.53.53.53.53.53.53.53.53.5–0.960–0.960–0.960–1.850–1.850–1.850–0.980–0.980–0.9801.41.41.41.41.41.41.11.11.11.11.11.12.42.42.42.42.42.42.22.22.22.22.22.2–0.810–0.810–0.810–1.650–1.650–1.650–1.630–1.630–1.6303.53.53.53.53.53.53.53.53.53.53.53.5–0.890–0.890–0.890–1.825–1.825–1.825–0.910–0.910–0.9101.51.51.51.51.51.51.21.21.21.21.21.2–0.700–0.700–0.700–1.615–1.615–1.615–1.595–1.595–1.5953.83.83.83.83.83.83.83.83.83.83.83.8VdcVdcVdcVdcnshttp://onsemi.com267

MC10111ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWCharacteristicSymbolUnderTest VIHmax VILmin VIHAmin VILAmax VEE(VCC)GndPower Supply Drain Current IE 8 8 1, 15, 16Input Current IinH 5, 6, 7 * 8 1, 15, 16Output Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234IinL 5, 6, 7 * 8 1, 15, 165675675678888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt5+2–t5–2+t5+3–t5–3+t5+4–t5–4+Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–* Individually test each input using the pin connections shown.2233442342345555555555552233442342348888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com268

The MC10113 is a quad Exclusive OR gate, with an enable commonto all four gates. The outputs may be wire–ORed together to perform a4–bit comparison function (A = B). The enable is active low.• PD = 175 mW typ/pkg (No Load)• tpd = 2.5 ns typ• tr, tf = 2.0 ns typ (20%–80%)45E 9LOGIC DIAGRAM2VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8http://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10113LAWLYYWW671011121331415VCC1AOUTBOUTAINDIPPIN ASSIGNMENT123416151413VCC2DOUTCOUTDINPDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MC10113PAWLYYWW110113AWLYYWWAINBINBIN567121110DINCINCINORDERING INFORMATIONDevice Package ShippingVEE89ENABLEMC10113L CDIP–16 25 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.TRUTH TABLEIN E OUTPUTL L L LL H L HH L L HH H L LX X H LMC10113P PDIP–16 25 Units / RailMC10113FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6269 Publication Order Number:MC10113/D

MC10113ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 46 42 46 mAdcInput Current IinH 4,7,10,135,6,11,129Output Voltage Logic 1 VOH 231415Output Voltage Logic 0 VOL 231415Threshold Voltage Logic 1 VOHA 231415Threshold Voltage Logic 0 VOLA 231415425350870265220545265220545µAdcIinL * 0.5 0.5 0.3 µAdc–1.060–1.060–1.060–1.060–1.890–1.890–1.890–1.890–1.080–1.080–1.080–1.080–0.890–0.890–0.890–0.890–1.675–1.675–1.675–1.675–1.655–1.655–1.655–1.655–0.960–0.960–0.960–0.960–1.850–1.850–1.850–1.850–0.980–0.980–0.980–0.980–0.810–0.810–0.810–0.810–1.650–1.650–1.650–1.650–1.630–1.630–1.630–1.630–0.890–0.890–0.890–0.890–1.825–1.825–1.825–1.825–0.910–0.910–0.910–0.910–0.700–0.700–0.700–0.700–1.615–1.615–1.615–1.615–1.595–1.595–1.595–1.595Switching Times (50Ω Load) Min Typ Max nsPropagation Delayt4+2+t4–2–t9+2–t9–2+22221.11.11.31.3Rise Time (20 to 80%) t2+ 2 1.1 4.2 1.1 2.5 3.9 1.1 4.4Fall Time (20 to 80%) t2– 2 1.1 4.2 1.1 2.5 3.9 1.1 4.4* Individually test each input applying VIH or VIL to input under test.4.74.75.25.21.31.31.51.52.62.63.43.44.54.55.05.01.31.31.51.55.05.05.55.5VdcVdcVdcVdchttp://onsemi.com270

MC10113ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 4,7,10,135,6,11,129Output Voltage Logic 1 VOH 231415Output Voltage Logic 0 VOL 231415Threshold Voltage Logic 1 VOHA 231415Threshold Voltage Logic 0 VOLA 231415**9888(VCC)Gnd1, 161, 161, 16IinL * * 8 1, 16471113Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+2+t4–2–t9+2–t9–2+222244Rise Time (20 to 80%) t2+ 2 4 2 8 1, 16Fall Time (20 to 80%) t2– 2 4 2 8 1, 16* Individually test each input applying VIH or VIL to input under test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.47111346101244995711132222888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com271

The MC10114 is a triple line receiver designed for use in sensingdifferential signals over long lines. An active current source andtranslated emitter follower inputs provide the line receiver with acommon mode noise rejection limit of one volt in either the positive orthe negative direction. This allows a large amount of common modenoise immunity for extra long lines.Another feature of the MC10114 is that the OR outputs go to a logiclow level whenever the inputs are left floating. The outputs are eachcapable of driving 50 ohm transmission lines.This device is useful in high speed central processors,minicomputers, peripheral controllers, digital communicationsystems, testing and instrumen– tation systems. The MC10114 canalso be used for MOS to MECL interfacing and it is ideal as a senseamplifier for MOS RAM’s.A VBB reference is provided which is useful in making theMC10114 a Schmit trigger, allowing single–ended driving of theinputs, or other applications where a stable reference voltage isnecessary. See MECL Design Handbook (HB205) pages 226 and 228.• PD = 145 mW typ/pkg• tpd = 2.4 ns typ (Single Ended Input)• tpd = 2.0 ns typ (Differential Input)• tr, tf = 2.1 ns typ (20%–80%)LOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10114LAWLYYWWMC10114PAWLYYWW110114AWLYYWW459102367A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1213VBB*141511VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8*V BB to be used to supply bias to the MC10114 only and bypassed (when used) with0.01 µF to 0.1 µF capacitor to ground (0 V). V BB can source < 1.0 mA.When the input pin with the bubble goes positive, its respective output pin withbubble goes positive.DIP PIN ASSIGNMENTORDERING INFORMATIONDevice Package ShippingMC10114L CDIP–16 25 Units / RailMC10114P PDIP–16 25 Units / RailMC10114FN PLCC–20 46 Units / RailVCC1116VCC2AOUT215COUTAOUT314COUTAIN413CINAIN512CINBOUT611VBBBOUT710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6272 Publication Order Number:MC10114/D

MC10114ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 39 28 35 39 mAdcInput Current IinH 4 70 45 45 µAdcOutput Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23ICBO 4 1.5 1.0 1.0 µAdc–1.060–1.060–1.890–1.890–1.080–1.080–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910–0.700–0.700–1.615–1.615–1.595–1.595Reference Voltage VBB 11 –1.420 –1.280 –1.350 –1.230 –1.295 –1.150 VdcCommon Mode RejectionTestVOH 23VOL 23–1.060–1.060–1.890–1.890–0.890–0.890–1.675–1.675–0.960–0.960–1.850–1.850–0.810–0.810–1.650–1.650–0.890–0.890–1.825–1.825–0.700–0.700–1.615–1.615Switching Times (50Ω Load) Min Max Min Typ Max Min Max nsPropagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–223323231.01.01.01.01.51.51.51.54.44.44.44.43.83.83.83.81.01.01.01.01.51.51.51.52.42.42.42.42.12.12.12.14.04.04.04.03.53.53.53.50.90.90.90.91.51.51.51.54.34.34.34.33.73.73.73.7VdcVdcVdcVdcVdcVdchttp://onsemi.com273

MC10114ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VBBSymbol–30°C –0.890 –1.890 –1.205 –1.500+25°C –0.810 –1.850 –1.105 –1.475+85°C –0.700 –1.825 –1.035 –1.440FromPin11Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VBB UnitPower Supply Drain Current IE 8 4, 9, 12 5, 10, 13 mAdcInput Current IinH 4 4 9, 12 5, 10, 13 µAdcOutput Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23IinL 4 9, 12 5, 10, 13 µAdc49, 129, 124Threshold Voltage Logic 1 VOHA 23 9, 12Threshold Voltage Logic 0 VOLA 239, 129, 12449, 129, 12 49, 12 445, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 134 5, 10, 135, 10, 13Reference Voltage VBB 11 5, 10, 13 VdcCommon Mode Rejection Test VOH 23VOL 23Switching Times (50Ω Load) Pulse In Pulse OutPropagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–2233232344444444223323235, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 13VdcVdcVdcVdcVdcVdcnshttp://onsemi.com274

MC10114ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHH* VILH* VIHL* VILL* VEESymbol–30°C +0.110 –0.890 –1.890 –2.890 –5.2+25°C +0.190 –0.850 –1.810 –2.850 –5.2+85°C +0.300 –0.825 –1.700 –2.825 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHH* VILH* VIHL* VILL* VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 4 8 1, 16Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23(VCC)GndIinL 4 8, 4 1, 16Reference Voltage VBB 11 8 1, 16Common Mode Rejection Test VOH 234 5VOL 23 4 55 488888888885 4 88Switching Times (50Ω Load) –3.2 V +2.0 VPropagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–*VIHH = Input Logic 1 level shifted positive one volt for common mode rejection testsVILH = Input Logic 0 level shifted positive one volt for common mode rejection testsVIHL = Input Logic 1 level shifted negative one volt for common mode rejection testsVILL = Input Logic 0 level shifted negative one volt for common mode rejection tests22332323Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com275

The MC10115 is a quad differential amplifier designed for use insensing differential signals over long lines. The base bias supply(VBB) is made available at pin 9 to make the device useful as a Schmitttrigger, or in other applications where a stable reference voltage isnecessary.Active current sources provide the MC10115 with excellentcommon mode noise rejection. If any amplifier in a package is notused, one input of that amplifier must be connected to VBB (pin 9) toprevent upsetting the current source bias network.• PD = 110 mW typ/pkg (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)457610111312LOGIC DIAGRAMVBB*VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8*V BB to be used to supply bias to the MC10115 only and bypassed (when used)with 0.01 µF to 0.1 µF capacitor to ground (0 V). V BB can source < 1.0 mA.When the input pin with the bubble goes positive, the output goes negative.DIPPIN ASSIGNMENT2314159http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATION116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10115LAWLYYWWMC10115PAWLYYWW110115AWLYYWWVCC1AOUTBOUT123161514VCC2DOUTCOUTDevice Package ShippingMC10115L CDIP–16 25 Units / RailMC10115P PDIP–16 25 Units / RailAIN413DINMC10115FN PLCC–20 46 Units / RailAIN512DINBIN611CINBIN710CINVEE89VBBPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6276 Publication Order Number:MC10115/D

MC10115ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 29 26 29 mAdcInput Current IinH 4 150 95 95 µAdcICBO 4 1.5 1.0 1.0 µAdcOutput Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 2 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 2 –1.655 –1.630 –1.595 VdcReference Voltage VBB 9 1.420 1.280 –1.350 –1.230 1.295 –1.150 VdcSwitching Times (50Ω Load)Propagation Delayt4–2+t4+2–221.01.0Rise Time (20 to 80%) t2+ 2 1.1 3.6 1.1 3.3 1.1 3.7Fall Time (20 to 80%) t2– 2 1.1 3.6 1.1 3.3 1.1 3.73.13.11.01.02.92.91.01.03.33.3nsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VBB VEESymbol–30°C –0.890 –1.890 –1.205 –1.500+25°C –0.810 –1.850 –1.105 –1.475+85°C –0.700 –1.825 –1.035 –1.440FromPin9–5.2–5.2–5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VBB VEEPower Supply Drain Current IE 8 4,7,10,13 5,6,11,12 8 1, 16Input Current IinH 4 4 7,10,13 5,6,11,12 8 1, 16(VCC)GndICBO 4 7,10,13 5,6,11,12 8,4 1, 16Output Voltage Logic 1 VOH 2 7,10,13 4 5,6,11,12 8 1, 16Output Voltage Logic 0 VOL 2 4 7,10,13 5,6,11,12 8 1, 16Threshold Voltage Logic 1 VOHA 2 7,10,13 4 5,6,11,12 8 1, 16Threshold Voltage Logic 0 VOLA 2 7,10,13 4 5,6,11,12 8 1, 16Reference Voltage VBB 9 5,6,11,12 8 1, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4–2+t4+2–2244225,6,11,125,6,11,12Rise Time (20 to 80%) t2+ 2 4 2 5,6,11,12 8 1, 16Fall Time (20 to 80%) t2– 2 4 2 5,6,11,12 8 1, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.881, 161, 16http://onsemi.com277

The MC10116 is a triple differential amplifier designed for use insensing differential signals over long lines. The base bias supply(VBB) is made available at pin 11 to make the device useful as aSchmitt trigger, or in other applications where a stable referencevoltage is necessary.Active current sources provide the MC10116 with excellentcommon mode noise rejection. If any amplifier in a package is notused, one input of that amplifier must be connected to VBB (pin 11) toprevent upsetting the current source bias network.Complementary outputs are provided to allow driving twisted pairlines, to enable cascading of several amplifiers in a chain, or simply toprovide complement outputs of the input logic function.• PD = 85 mW typ/pkg (No Load)• tpd = 2.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)459101213LOGIC DIAGRAMVBB*2367141511VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8*V BB to be used to supply bias to the MC10116 only and bypassed (when used)with 0.01 µF to 0.1 µF capacitor to ground (0 V). V BB can source < 1.0 mA.When the input pin with the bubble goes positive, the output pin with the bubblegoes positive.DIPPIN ASSIGNMENThttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10116L CDIP–16 25 Units / Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10116LAWLYYWWMC10116PAWLYYWW110116AWLYYWWVCC1116VCC2MC10116P PDIP–16 25 Units / RailAOUT215COUTMC10116FN PLCC–20 46 Units / RailAOUT314COUTAIN413CINAIN512CINBOUT611VBBBOUT710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6278 Publication Order Number:MC10116/D

MC10116ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 23 17 21 23 mAdcInput Current IinH 4 150 95 95 µAdcOutput Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23ICBO 4 1.5 1.0 1.0 µAdc–1.060–1.060–1.890–1.890–1.080–1.080–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910–0.700–0.700–1.615–1.615–1.595–1.595Reference Voltage VBB 11 –1.420 –1.280 –1.350 –1.230 –1.295 –1.150 VdcSwitching Times (50Ω Load)Propagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–223323231.01.01.01.01.11.11.11.13.13.13.13.13.63.63.63.61.01.01.01.01.11.11.11.12.02.02.02.02.02.02.02.02.92.92.92.93.33.33.33.31.01.01.01.01.11.11.11.13.33.33.33.33.73.73.73.7VdcVdcVdcVdcnshttp://onsemi.com279

MC10116ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VBB VEESymbol–30°C –0.890 –1.890 –1.205 –1.500+25°C –0.810 –1.850 –1.105 –1.475+85°C –0.700 –1.825 –1.035 –1.440FromPin11–5.2–5.2–5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VBB VEEPower Supply Drain Current IE 8 4, 9, 12 5, 10, 13 8 1, 16Input Current IinH 4 4 9, 12 5, 10, 13 8 1, 16Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23(VCC)GndICBO 4 9, 12 5, 10, 13 8,4 1, 1649, 129, 124Threshold Voltage Logic 1 VOHA 23 9, 12Threshold Voltage Logic 0 VOLA 23 9, 129, 12449, 129, 12 49, 12445, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 134 5, 10, 135, 10, 13Reference Voltage VBB 11 5, 10, 13 8 1, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–2233232344444444223323235, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 13Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.88888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com280

The MC10117 is a dual 2–wide 2–3–inputOR–AND/OR–AND–Invert gate. This general purpose logic elementis designed for use in data control, such as digital multiplexing or datadistribution. Pin 9 is common to both gates.• PD = 100 mW typ/pkg (No Load)• tpd = 2.3 ns typ• tr, tf = 2.2 ns typ (20%–80%)4567910111213LOGIC DIAGRAMDIPPIN ASSIGNMENTVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8321415http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10117LAWLYYWWMC10117PAWLYYWW110117AWLYYWWVCC1AOUTAOUTA1INA1INA2IN123456161514131211VCC2BOUTBOUTB1INB1INB2INORDERING INFORMATIONDevice Package ShippingMC10117L CDIP–16 25 Units / RailMC10117P PDIP–16 25 Units / RailMC10117FN PLCC–20 46 Units / RailA2IN710B2INVEE89A2IN, B2INPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6281 Publication Order Number:MC10117/D

MC10117ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 29 20 26 29 mAdcInput Current IinH* 694Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23Switching Times (50Ω Load)Propagation Delay425560390265350245265350245µAdcIinL 4 0.5 0.5 0.3 µAdct4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–* Inputs 4, 5, 12 and 13 have same IinH limit.Inputs 6, 7, 10 and 11 have same IinH limit.22332323–1.060–1.060–1.890–1.890–1.080–1.0801.41.41.41.40.90.90.90.9–0.890–0.780–1.675–1.675–1.655–1.6553.93.93.93.94.14.14.14.1–0.960–0.960–1.850–1.850–0.980–0.9801.41.41.41.41.11.11.11.12.32.32.32.32.22.22.22.2–0.810–0.700–1.650–1.650–1.630–1.6303.43.43.43.44.04.04.04.0–0.890–0.890–1.825–1.825–0.910–0.9101.41.41.41.41.11.11.11.1–0.700–0.590–1.615–1.615–1.595–1.5953.83.83.83.84.64.64.64.6VdcVdcVdcVdcnshttp://onsemi.com282

MC10117ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH* 694Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23 4, 9Threshold Voltage Logic 1 VOHA 23494888(VCC)Gnd1, 161, 161, 16IinL 4 9 8 1, 164, 9 889 4Threshold Voltage Logic 0 VOLA 23 9 4488884 88Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–* Inputs 4, 5, 12 and 13 have same IinH limit.Inputs 6, 7, 10 and 11 have same IinH limit.2233232399999999Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.4444444422332323888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com283

The MC10121 is a basic logic building block providing thesimultaneous OR–AND/OR–AND–Invert function, useful in datacontrol and digital multiplexing applications.• PD = 100 mW typ/pkg (No Load)• tpd = 2.3 ns typ• tr, tf = 2.5 ns typ (20%–80%)45679101112131415LOGIC DIAGRAMDIPPIN ASSIGNMENTVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 823http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10121LAWLYYWWMC10121PAWLYYWW110121AWLYYWWVCC1AOUT121615VCC2A4INORDERING INFORMATIONAOUT314A4INDevice Package ShippingA1IN413A4INMC10121L CDIP–16 25 Units / RailA1IN512A3INMC10121P PDIP–16 25 Units / RailA1INA2IN671110A3INA2IN, A3INMC10121FN PLCC–20 46 Units / RailVEE89A2INPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6284 Publication Order Number:MC10121/D

MC10121ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 29 20 26 29 mAdcInput Current IinH 7910IinL 7910Output Voltage Logic 1 VOH 32Output Voltage Logic 0 VOL 32Threshold Voltage Logic 1 VOHA 32Threshold Voltage Logic 0 VOLA 32Switching Times (50Ω Load)Propagation Delayt4+3–t4–3+t4+2+t4–2–Rise Time (20 to 80%) t3+t2+Fall Time (20 to 80%) t3–t2–332232320.50.50.5–1.060–1.060–1.890–1.890–1.080–1.0801.41.41.41.40.90.90.90.9390390495–0.890–0.890–1.675–1.675–1.655–1.6553.63.63.63.64.14.14.14.10.50.50.5–0.960–0.960–1.850–1.850–0.980–0.9801.41.41.41.41.11.11.11.12.32.32.32.32.52.52.52.5245245310–0.810–0.810–1.650–1.650–1.630–1.6303.43.43.43.44.04.04.04.00.30.30.3–0.890–0.890–1.825–1.825–0.910–0.9101.41.41.41.41.11.11.11.1245245310–0.700–0.700–1.615–1.615–1.595–1.5953.53.53.53.54.64.64.64.6µAdcµAdcVdcVdcVdcVdcnshttp://onsemi.com285

MC10121ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 7910IinL 79107910Output Voltage Logic 1 VOH 32 4, 10, 13Output Voltage Logic 0 VOL 3279104, 10, 13 88Threshold Voltage Logic 1 VOHA 32 10, 13 4Threshold Voltage Logic 0 VOLA 32 10, 13888888884 88(VCC)GndSwitching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+3–t4–3+t4+2+t4–2–Rise Time (20 to 80%) t3+t2+Fall Time (20 to 80%) t3–t2–3322323210, 1310, 1310, 1310, 1310, 1310, 1310, 1310, 13Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.44444444443322323288888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com286

The MC10123 consists of three NOR gates designed for bus drivingapplications on card or between cards. Output low logic levels arespecified with VOL = –2.1 Vdc so that the bus may be terminated to–2.0 Vdc. The gate output, when low, appears as a high impedance tothe bus, because the output emitter– followers of the MC10123 are“turned–off.” This eliminates discontinuities in the characteristicimpedance of the bus.The VOH level is specified when driving a 25–ohm load terminatedto –2.0 Vdc, the equivalent of a 50–ohm bus terminated at both ends.Although 25 ohms is the lowest characteristic impedance that can bedriven by the MC10123, higher impedance values may be used withthis part. A typical 50–ohm bus is shown in Figure 1.• PD = 310 mW typ/pkg (No Load)• tpd = 3.0 ns typ• tr, tf = 2.5 ns typ (20%–80%)VCC1DIPPIN ASSIGNMENT116VCC2http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10123LAWLYYWWMC10123PAWLYYWW110123AWLYYWWBOUTAOUTAINAIN234515141312COUTCINCINCINA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekAINAINVEE67811109BINBINBINORDERING INFORMATIONDevice Package ShippingMC10123L CDIP–16 25 Units / RailMC10123P PDIP–16 25 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.MC10123FN PLCC–20 46 Units / RailLOGIC DIAGRAM45367910 2111213 1514VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 850 ΩFIGURE 1 — 50–OHM BUS DRIVER (TYPICAL APPLICATION)ZO = 50 Ω–2.0VDC1/3 MC10123 1/3 MC10123 1/3 MC10123RECEIVERS (MECL GATES)–2.0VDC50 Ω© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6287 Publication Order Number:MC10123/D

MC10123ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 82 71 75 82 mAdcInput Current IinH 4 350 220 220 µAdcIinL 4 0.5 µAdcOutput Voltage Logic 1 VOH 3 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 3 –2.100 –2.030 –2.100 –2.030 –2.100 –2.030 VdcThreshold Voltage Logic 1 VOHA 3 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 3 –2.100 –2.100 –2.100 VdcSwitching Times (50Ω Load)Propagation Delayt4+3–t4–3+331.21.2Rise Time (20 to 80%) t3+ 3 1.0 3.7 1.0 2.5 3.5 1.0 3.9Fall Time (20 to 80%) t3– 3 1.0 3.7 1.0 2.5 3.5 1.0 3.94.64.61.21.23.03.04.44.41.21.24.84.8nsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnder(VCC)CharacteristicSymbol Test VIHmax VILmin VIHAmin VILAmax VEE GndPower Supply Drain Current IE 8 4,5,6,7,910,11,1213,148 1, 16Input Current IinH 4 4 8 1, 16IinL 4 4 8 1, 16Output Voltage Logic 1 VOH 3 8 1, 16Output Voltage Logic 0 VOL 3 4,5,6,79,128 1, 16Threshold Voltage Logic 1 VOHA 3 4,5,6,7 8 1, 16Threshold Voltage Logic 0 VOLA 3 9,12 4,5,6,7 8 1, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+3–t4–3+33Rise Time (20 to 80%) t3+ 3 4 3 8 1, 16Fall Time (20 to 80%) t3– 3 4 3 8 1, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.4433881, 161, 16http://onsemi.com288

The MC10124 is a quad translator for interfacing data and controlsignals between a saturated logic section and the MECL section ofdigital systems. The MC10124 has TTL compatible inputs, andMECL complementary open–emitter outputs that allow use as aninverting/ non–inverting translator or as a differential line driver.When the common strobe input is at the low logic level, it forces alltrue outputs to a MECL low logic state and all inverting outputs to aMECL high logic state.Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.Propagation delay of the MC10124 is typically 3.5 ns. The dc levelsare standard or Schottky TTL in, MECL 10,000 out.An advantage of this device is that TTL level information can betransmitted differentially, via balanced twisted pair lines, to the MECLequipment, where the signal can be received by the MC10115 orMC10116 differential line receivers. The MC10124 is useful incomputers, instrumentation, peripheral controllers, test equipment,and digital communications systems.• PD = 380 mW typ/pkg (No Load)• tpd = 3.5 ns typ (+ 1.5 Vdc in to 50% out)• tr, tf = 2.5 ns typ (20%–80%)LOGIC DIAGRAM5 4627 3110 121511 1314Gnd = PIN 16VCC (+5.0Vdc) = PIN 9VEE (–5.2Vdc) = PIN 8DIP PIN ASSIGNMENThttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10124L CDIP–16 25 Units / RailMC10124P PDIP–16 25 Units / RailMC10124FN PLCC–20 46 Units / Rail1161MC10124LAWLYYWWMC10124PAWLYYWW110124AWLYYWWBOUTAOUTBOUTAOUTAINCOMMONSTROBEBINVEE12345678161514131211109GNDCOUTDOUTDOUTCOUTDINCINVCCPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6289 Publication Order Number:MC10124/D

MC10124ELECTRICAL CHARACTERISTICSCharacteristicNegative Power SupplyDrain CurrentSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitIE 8 72 66 72 mAdcPositive Power Supply ICCH 9 16 16 18 mAdcDrain CurrentICCL 9 25 25 25 mAdcReverse Current IR 67Forward Current IF 67Input Breakdown Voltage BVin 67Clamp Input Voltage VI 67High Output Voltage VOH 13Low Output Voltage VOL 13High Threshold Voltage VOHA 13Low Threshold Voltage VOLA 13Switching Times (50ΩLoad)Propagation Delay(+3.5Vdc to 50%)1t6+1+t6–1–t7+1+t7–1–t7+3–t7–3+1111335.55.5–1.060–1.060–1.890–1.890–1.080–1.0801.51.01.51.01.51.020050–12.8–3.2–1.5–1.5–0.890–0.890–1.675–1.675–1.655–1.6556.86.06.86.06.86.05.55.5–0.960–0.960–1.850–1.850–0.980–0.9801.01.01.01.01.01.03.53.53.53.53.53.520050–12.8–3.2–1.5–1.5–0.810–0.810–1.650–1.650–1.630–1.6306.06.06.06.06.06.05.55.5–0.890–0.890–1.825–1.825–0.910–0.9101.01.51.01.51.01.520050–12.8–3.2–1.5–1.5–0.700–0.700–1.615–1.615–1.595–1.5956.06.86.06.86.06.8µAdcmAdcVdcVdcVdcVdcVdcVdcnsRise Time (20 to 80%) t1+ 1 1.0 4.2 1.1 2.5 3.9 1.1 4.3Fall Time (20 to 80%) t1– 1 1.0 4.2 1.1 2.5 3.9 1.1 4.31. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.http://onsemi.com290

MC10124ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)CharacteristicNegative Power Supply DrainCurrent@ Test Temperature VIH VILmax VIHA’ VILA’ VFSymbol–30°C +4.0 +0.40 +2.00 +1.10 +0.40+25°C +4.0 +0.40 +1.80 +1.10 +0.40+85°C +4.0 +0.40 +1.80 +0.90 +0.40Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIH VILmax VIHA’ VILA’ VF GndIE 8 16Positive Power Supply Drain ICCH 9 5,6,7,10,11 16CurrentICCL 9 5,6,7,10,11,16Reverse Current IR 67Forward Current IF 67Input Breakdown Voltage BVin 67Clamp Input Voltage VI 67High Output Voltage VOH 135,7,10,116Low Output Voltage VOL 13 6,7High Threshold Voltage VOHA 13Low Threshold Voltage VOLA 136,7666,75,7,10,11667161616165,7,10,11,166,16161616166,7 161666 77716167 1616Switching Times (50Ω Load) +6.0 V Pulse In Pulse Out +2.0 VPropagation Delay(+3.5Vdc to 50%)1t6+1+t6–1–t7+1+t7–1–t7+3–t7–3+111133776666Rise Time (20 to 80%) t1+ 1 6 7 1 16Fall Time (20 to 80%) t1– 1 6 7 1 161. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.667777111133161616161616http://onsemi.com291

MC10124ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)(mA)CharacteristicNegative Power Supply DrainCurrent@ Test Temperature VR VCC VEE II IinSymbol–30°C +2.40 +5.00 –5.2 –10 +1.0+25°C +2.40 +5.00 –5.2 –10 +1.0+85°C +2.40 +5.00 –5.2 –10 +1.0Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VR VCC VEE II Iin GndIE 8 9 8 16Positive Power Supply Drain ICCH 9 9 8 16CurrentICCL 9 9 8 5,6,7,10,11,16Reverse Current IR 67Forward Current IF 67Input Breakdown Voltage BVin 67Clamp Input Voltage VI 67High Output Voltage VOH 13Low Output Voltage VOL 13High Threshold Voltage VOHA 13Low Threshold Voltage VOLA 1367999999999988888888886767161616165,7,10,11,166,16Switching Times (50Ω Load) +7.0 V –3.2 V +2.0 VPropagation Delay(+3.5Vdc to 50%)1t6+1+t6–1–t7+1+t7–1–t7+3–t7–3+111133Rise Time (20 to 80%) t1+ 1 9 8 16Fall Time (20 to 80%) t1– 1 9 8 161. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.99999999999988888888888816161616161616161616161616161616http://onsemi.com292

MC10124SWITCHING TIME TEST CIRCUITVin+6.0 Vdc VCC+7.0 VdcVoutNANDVoutANDCoax0.1 µF 25 µF0.1 µF Coax CoaxInputPulse GeneratorInput Pulset+ = t– = 5.5 ±0.5 ns(10 to 90%)5 46273110 121511 131416 80.1 µF 25 µF 0.1 µFUnused outputs connected to a50–ohm resistor to ground.50–ohm termination to ground lo–cated in each scope channel input.All input and output cables to thescope are equal lengths of 50–ohmcoaxial cable. Wire length should be< 1/4 inch from TPin to input pin andTPout to output pin.+ 2.0 Vdc–3.2 VdcVEENOTE: All power supply and logic levels are shownshifted 2 volts positive.http://onsemi.com293

The MC10125 is a quad translator for interfacing data and controlsignals between the MECL section and saturated logic sections ofdigital systems. The MC10125 incorporates differential inputs andSchottky TTL “totem pole” outputs. Differential inputs allow for useas an inverting/ non–inverting translator or as a differential linereceiver. The VBB reference voltage is available on pin 1 for use insingle–ended input biasing. The outputs of the MC10125 go to a lowlogic level whenever the inputs are left floating.Power supply requirements are ground, +5.0 Volts and –5.2 Volts.Propagation delay of the MC10125 is typically 4.5 ns. The MC10125has fanout of 10 TTL loads. The dc levels are MECL 10,000 in andSchottky TTL, or TTL out. This device has an input common modenoise rejection of ± 1.0 Volt.An advantage of this device is that MECL level information can bereceived, via balanced twisted pair lines, in the TTL equipment. Thisisolates the MECL logic from the noisy TTL environment. This deviceis useful in computers, instrumentation, peripheral controllers, testequipment and digital communications systems.• PD = 380 mW typ/pkg (No Load)• tpd = 4.5 ns typ (50% to + 1.5 Vdc out)• tr, tf = 2.5 ns typ (1.0 V to 2.0 V)236710111415LOGIC DIAGRAMVBB**V BB to be used to supply bias to the MC10125 only and bypassed (when used)with 0.01 µF to 0.1 µF capacitor to ground (0 V). V BB can source < 1.0 mA.When the input pin with the bubble goes positive, the output goes negative.VBBAINAINAOUTBOUTBINBINVEE4512131DIP PIN ASSIGNMENT12345678161514131211109Gnd = PIN 16VCC (+5.0Vdc) = PIN 9VEE (–5.2Vdc) = PIN 8GNDDINDINDOUTCOUTCINCINVCChttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10125L CDIP–16 25 Units / RailMC10125P PDIP–16 25 Units / RailMC10125FN PLCC–20 46 Units / Rail1161MC10125LAWLYYWWMC10125PAWLYYWW110125AWLYYWWPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6294 Publication Order Number:MC10125/D

MC10125ELECTRICAL CHARACTERISTICSCharacteristicNegative Power SupplyDrain CurrentSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitIE 8 –44 –40 –44 mAdcPositive Power Supply ICCH 9 52 52 52 mAdcDrain CurrentICCL 9 39 39 39 mAdcInput Current IinH 1 2 180 115 115 µAdcInput Leakage Current ICBO 2 1.5 1.0 1.0 µAdcHigh Output Voltage VOH 4 2.5 2.5 2.5 VdcLow Output Voltage VOL 4 0.5 0.5 0.5 VdcHigh Threshold Voltage VOHA 4 2.5 2.5 2.5 VdcLow Threshold Voltage VOLA 4 0.5 0.5 0.5 VdcIndeterminate Input VOLS1 4 0.5 0.5 0.5 VdcProtection TestsVOLS2 4 0.5 0.5 0.5 VdcShort Circuit Current IOS 4 40 100 40 100 40 100 mAdcReference Voltage VBB 1 –1.420 –1.280 –1.350 –1.230 –1.295 –1.150 VdcCommon Mode RejectionTestsSwitching Times (50ΩLoad)Propagation Delay(50% to +1.5Vdc)VOH 44VOL 44t6+5–t6–5+t2+4–t2–4+55442.52.51.01.01.01.0Rise Time (+1.0V to 2.0V) t4+ 4 3.3 3.3 3.3Fall Time (+1.0V to 2.0V) t4– 4 3.3 3.3 3.31. Individually test each output, apply VIHmax to pin under test.0.50.56.06.06.06.02.52.51.01.01.01.04.54.54.54.50.50.56.06.06.06.02.52.51.01.01.01.00.50.56.06.06.06.0VdcVdcnshttp://onsemi.com295

MC10125ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)CharacteristicNegative Power SupplyDrain Current@ Test Temperature VIHmax VILmin VIHAmin VILAmax VIHH VILHSymbol–30°C –0.890 –1.890 –1.205 –1.500 +0.110 –0.890+25°C –0.810 –1.850 –1.105 –1.475 +0.190 –0.850+85°C –0.700 –1.825 –1.035 –1.440 +0.300 –0.825Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VIHH VILH GndIE 8 16Positive Power Supply ICCH 9 2,6,10,14 16Drain CurrentICCL 9 2,6,10,14 16Input Current IinH 1 2 2,6,10,14 16Input Leakage Current ICBO 2 16OutputtConditionHigh Output Voltage VOH 4 2,6,10,14 16 –2.0mALow Output Voltage VOL 4 2,6,10,14 16 20mAHigh Threshold Voltage VOHA 4 6,10,14 2 16 –2.0mALow Threshold Voltage VOLA 4 6,10,14 2 16 20mAIndeterminate Input VOLS1 4 16 20mAProtection TestsVOLS2 4 16 20mAShort Circuit Current IOS 4 2,6,10,14 4, 16Reference Voltage VBB 1 2,6,10,14Common Mode RejectionTestsSwitching Times (50ΩLoad)Propagation Delay(50% to +1.5Vdc)VOH 44VOL 44t6+5–t6–5+t2+4–t2–4+5544Pulse In Pulse Out CL (pF)66223 2 16162 3 1616Rise Time(+1.0V to 2.0V) t4+ 4 2 4 25 16Fall Time (+1.0V to 2.0V) t4– 4 2 4 25 161. Individually test each output, apply VIHmax to pin under test.55442525252516161616–2.0mA–2.0mA20mA20mAhttp://onsemi.com296

MC10125ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)CharacteristicNegative Power SupplyDrain Current@ Test Temperature VIHH VILH VBB VCC VEESymbol–30°C –1.890 –2.890+25°C –1.810 –2.850+85°C –1.700 –2.825FromPin1+5.0 –5.2+5.0 –5.2+5.0 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHH VILH VBB VCC VEE GndIE 8 3,7,11,15 9 8 16Positive Power Supply ICCH 9 3,7,11,15 9 8 16Drain CurrentICCL 9 3,7,11,15 9 8 16Input Current IinH 1 2 3,7,11,15 9 8 16Input Leakage Current ICBO 2 3,7,11,15 9 2,6,8,10,14 16OutputtConditionHigh Output Voltage VOH 4 3,7,11,15 9 8 16 –2.0mALow Output Voltage VOL 4 3,7,11,15 9 8 16 20mAHigh Threshold Voltage VOHA 4 3,7,11,15 9 8 16 –2.0mALow Threshold Voltage VOLA 4 3,7,11,15 9 8 16 20mAIndeterminate InputProtection TestsVOLS1 4 9 2,3,6,7,8,10,11,14,1516 20mAVOLS2 4 9 8 16 20mAShort Circuit Current IOS 4 3,7,11,15 9 8 4, 16Reference Voltage VBB 1 3,7,11,15Common Mode Rejection Tests VOH 44 3 2Switching Times(50Ω Load)Propagation Delay(50% to +1.5Vdc)VOL 44 2 3t6+5–t6–5+t2+4–t2–4+55443,7,11,153,7,11,153,7,11,153,7,11,15Rise Time (+1.0V to 2.0V) t4+ 4 3,7,11,15 9 8 16Fall Time (+1.0V to 2.0V) t4– 4 3,7,11,15 9 8 161. Individually test each output, apply VIHmax to pin under test.99999999888888881616161616161616–2.0mA–2.0mA20mA20mAEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com297

MC10125SWITCHING TIME TEST CIRCUITVinVCC+5.0 VdcVoutCoax0.1 µFCoaxInputPulse GeneratorInput Pulset+ = t– = 2.0 ±0.2 ns(20 to 80%)236710114512450CL–1.69 Vdc141513CL = 25 pF, including test fixture50-ohm termination to ground locatedin each scope channel input.All input and output cables to thescope are equal lengths of 50-ohmcoaxial cable. Wire length should be< 1/4 inch from TPin to input pin andTPout to output pin.0.1 µF1VBB16 80.1 µFOne input from each gate must be tied to VBB(Pin 1) during testing.–5.2 VdcVEEhttp://onsemi.com298

The MC10129 data inputs are compatible with, and accept TTLlogic levels as well as levels compatible with IBM–type buses. Theclock, strobe, and reset inputs accept MECL 10,000 logic levels.The data inputs accept the bus levels, and storage elements areprovided to yield temporary latch storage of the information afterreceiving it from the bus. The outputs can be strobed to allow accuratesynchronization of signals and/or connection to MECL 10,000 levelbuses. When the clock is low, and the reset input is disabled, theoutputs will follow the D inputs. The latches will store the data on therising edge of the clock. The outputs are enabled when the strobe inputis high. Unused D inputs must be tied to VCC or Gnd. The clock,strobe, and reset inputs each have 50 k ohm pulldown resistors to VEE.They may be left floating, if not used.The MC10129 will operate in either of two modes. The first mode isobtained by tying the hysteresis control input to VEE. In this mode, theinput threshold points of the D inputs are fixed. The second mode isobtained by tying the hysteresis control input to ground. In this mode,input hysteresis is achieved as shown in the test table. This hysteresisis desirable where extra noise margin is required on the D inputs. Theouter input pins are unaffected by the mode of operation used.The MC10129 is especially useful in interface applications forcentral processors, mini–computers, and peripheral equipment.• PD = 750 mW typ/pkg (No Load)• tpd = 10 ns typ• VCC Max = 7.0 Vdchttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1161MARKINGDIAGRAMSMC10129LAWLYYWWMC10129PAWLYYWW110129AWLYYWWORDERING INFORMATIONDevice Package ShippingMC10129L CDIP–16 25 Units / RailMC10129P PDIP–16 25 Units / RailMC10129FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7299 Publication Order Number:MC10129/D

MC10129LOGIC DIAGRAMPIN ASSIGNMENTD0 7 DCR14 Q0GNDQ3121615GNDQ1Q2314Q0D1 13D15 Q1D3HYSTERESISCONTROL451312D1STROBED2611CLOCKD2 6 DCR3 Q2CR2 Q3D0VEE78109RESETVCCD3 4 DPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin ConversionTables on page 18.HYSTERESISCONTROL 5CRTRUTH TABLECLOCK 11RESET 10STROBE 12VCC = PIN 9GND = PIN 1 AND 16VEE = PIN 8D C STROBE RESET Qn + 1X X L X LX H X H LL L H X LX H H L QnH L H X Hhttp://onsemi.com300

MC10129ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitNegative Power Supply DrainCurrentPositive Power Supply Drain CurrentI E 88167189I CC 9 8.0 8.0 8.0 mAdc152172167189mAdcInput Current I inH 467101112131501501507203903901509595954502452459595959545024524595µAdcI CBO (1.) 467131.51.51.5–1.0–1.0–1.0–1.01.01.01.0µAdcI inL 1011120.50.50.50.50.50.50.30.30.3µAdcOutput Voltage Logic 1 V OH 2323Output Voltage Logic 0 V OL 2323Threshold Voltage Logic 1 V OHA 2 (2.)2222 (3.)2 (4.)Threshold Voltage Logic 0 V OLA 2 (2.)22 (2.)22 (3.)2 (4.)Switching TimesPropagation DelayData Input t 7+14+ 14t 7–14– 14Clock Input t 11–14+ 14t 11–14– 14Strobe Input t 12+14+ 14t 12–14– 14–1.060–1.060–1.060–1.060–1.890–1.890–1.890–1.890–1.080–1.080–1.080–1.080–1.080–1.0803.73.72.72.71.61.6–0.890–0.890–0.890–0.890–1.675–1.675–1.675–1.675–1.655–1.655–1.655–1.655–1.655–1.655151511118.08.0–0.960–0.960–0.960–0.960–1.850–1.850–1.850–1.850–0.980–0.980–0.980–0.980–0.980–0.9803.73.72.72.71.61.610105.05.04.04.0–0.810–0.810–0.810–0.810–1.650–1.650–1.650–1.650–1.630–1.630–1.630–1.630–1.630–1.63015159.09.07.07.0–0.890–0.890–0.890–0.890–1.825–1.825–1.825–1.825–0.910–0.910–0.910–0.910–0.910–0.910Reset Input t 10+14– 14 2.0 8.0 2.0 5.0 6.5 2.0 8.0Hysteresis Mode t 7+14+ 14t 7–14– 146.63.7Setup Time t setup 14 30 2.7 15 30Hold Time t hold 14 0 –2.0 15 –2.0Rise Time t+ 14 1.5 5.0 1.5 2.0 4.3 1.5 5.0Fall Time t– 14 1.5 5.0 1.5 2.0 4.3 1.5 5.030176.73.7181025153.73.72.72.71.61.66.63.7–0.700–0.700–0.700–0.700–1.615–1.615–1.615–1.615–1.595–1.595–1.595–1.595–1.595–1.5951. Pin 5 to V EE , V IL to Data input one at a time.2. Output latched to logic high state prior to test. V IHA ′, V ILA ′ are standard logic 1 and logic 0 MTTL threshold voltages. V IHA ′′, V ILA ′′, V IHA ′′′ and V ILA ′′′ are logic1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 301.3. Input level on data input taken from +0.4V up to voltage level given.4. Input level on data input taken from +4.0V down to voltage level given.5. Operation and limits shown also apply for V CC = +6.0V.VIHA′′VIHA′′′Hysteresis ModeThreshold VoltageLogic 1VoutLogic 0VILA′′VILA′′′VinFigure 1. Hysteresis Mode Threshold Voltage304011118.08.03040VdcVdcVdcVdcnshttp://onsemi.com301

MC10129ELECTRICAL CHARACTERISTICSTEST VOLTAGE VALUES (Volts)MECL 10,000 INPUT LEVELS TTL INPUT LEVELS (6.)CharacteristicNegative Power SupplyDrain CurrentPositive Power SupplyDrain Current@ Test Temperature V IHmax V ILmin V IHAmin V ILAmax V IH V IL V IHA′ V ILA′SymbolI E 88–30°C –0.890 –1.890 –1.155 –1.500 3.000 0.400 2.000 0.800+25°C –0.810 –1.850 –1.105 –1.475 3.000 0.400 2.000 0.800+85°C –0.700 –1.825 –1.035 –1.440 3.000 0.400 2.000 0.800PinTEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest V IHmax V ILmin V IHAmin V ILAmax V IH V IL V IHA′ V ILA′Gnd11111212I CC 9 4,6,7,13 1,161,5,161,16Input Current I inH 4671011121310,111112467131,161,161,161,161,161,161,16I CBO (1.) 46713467131,161,161,161,16I inL 1011121011121,161,161,16Output VoltageLogic 1Output VoltageLogic 0Threshold VoltageLogic 1Threshold VoltageLogic 0V OH 2323V OL 2323V OHA 2 (2.)2222 (3.)2 (4.)V OLA 2 (2.)22 (2.)22 (3.)2 (4.)121212121212121211,1210,1212121211,1210,1212121210,1110,1110,1110,1110,1110,1110,1110,1110,1110,1110,1110,1110,1110,1110,1110,11Switching TimesPropagation Delay +1.11V +0.31V Pulse InData Input t 7+14+ 14t 7–14– 14Clock Input t 11–14+ 14t 11–14– 14Strobe Input t 12+14+ 14t 12–14– 141212121210,1110,11101010,1110,11121011777,117,11121210111246464444444646441,161,161,5,161,5,161,161,161,5,161,5,161,161,161,161,161,5,161,5,161,161,161,161,161,5,161,5,16PulseOut +5.0V +2.40V Figure +2.0V14141414141477Figure 3Figure 3Figure 6Figure 6Figure 4Figure 4Reset Input t 10+14– 14 12 10,11 14 7 7 Figure 5 1,16Hysteresis Mode t 7+14+ 14t 7–14– 14121210,1110,11771414Figure 3Figure 3Setup Time t setup 14 12 10 7,11 14 Figure 7 1,16Hold Time t hold 14 12 10 7,11 14 Figure 7 1,16Rise Time t+ 14 12 10,11 7 14 Figure 3 1,16Fall Time t– 14 12 10,11 7 14 Figure 3 1,161. Pin 5 to V EE , V IL to Data input one at a time.2. Output latched to logic high state prior to test. V IHA ′, V ILA ′ are standard logic 1 and logic 0 MTTL threshold voltages. V IHA ′′, V ILA ′′, V IHA ′′′ and V ILA ′′′ are logic1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 301.3. Input level on data input taken from +0.4V up to voltage level given.4. Input level on data input taken from +4.0V down to voltage level given.5. Operation and limits shown also apply for V CC = +6.0V. 6. When testing, choose either TTL or IBM input levels.1,161,161,161,161,161,161,5,161,5,16http://onsemi.com302

MC10129ELECTRICAL CHARACTERISTICSTEST VOLTAGE VALUES (Volts)IBM INPUT LEVELS (6.)HYSTERESIS MODECharacteristic@ Test Temperature V IH V IL V IHA ′ V ILA ′ V IHA ′′ V ILA ′′ V IHA ′′′ V ILA ′′′ V CC (5.) V EE–30°C 3.11 0.150 2.90 2.00 2.20 1.30 +5.0 –5.2+25°C 3.11 0.150 1.700 0.70 2.60 1.70 1.90 1.00 +5.0 –5.2+85°C 3.11 0.150 2.30 1.40 1.60 0.70 +5.0 –5.2PinTEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderSymbol Test V IH V IL V IHA ′ V ILA ′ V IHA ′′ V ILA ′′ V IHA ′′′ V ILA ′′′ V CC (5.) V EEGndNegative Power SupplyDrain CurrentI E 889985,81,5,161,16Positive Power SupplyDrain CurrentI CC 9 4,6,7,13995,85,81,161,16Input Current I inH 4671011121346713999999988888881,161,161,161,161,161,161,16I CBO (1.) 4671346713999988881,161,161,161,16I inL 1011129998881,161,161,16Output VoltageLogic 1Output VoltageLogic 0Threshold VoltageLogic 1Threshold VoltageLogic 0V OH 2323V OL 2323V OHA 2 (2.)2222 (3.)2 (4.)V OLA 2 (2.)22 (2.)22 (3.)2 (4.)464644444446464Switching TimesPropagation Delay +5.0V +2.40V Figure +7.0V –3.2V +2.0VData Input t 7+14+ 14t 7–14– 14Clock Input t 11–14+ 14t 11–14– 14Strobe Input t 12+14+ 14t 12–14– 14774Figure 3Figure 3Figure 6Figure 6Figure 4Figure 4Reset Input t 10+14– 14 7 Figure 5 9 5,8 1,16Hysteresis Mode t 7+14+ 14t 7–14– 14Figure 3Figure 3Setup Time t setup 14 Figure 7 9 5,8 1,16Hold Time t hold 14 Figure 7 9 5,8 1,16Rise Time t+ 14 Figure 3 9 5,8 1,16Fall Time t– 14 Figure 3 9 5,8 1,161. Pin 5 to V EE , V IL to Data input one at a time.2. Output latched to logic high state prior to test. V IHA ′, V ILA ′ are standard logic 1 and logic 0 MTTL threshold voltages. V IHA ′′, V ILA ′′, V IHA ′′′ and V ILA ′′′ are logic1 and logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 301.3. Input level on data input taken from +0.4V up to voltage level given.4. Input level on data input taken from +4.0V down to voltage level given.5. Operation and limits shown also apply for V CC = +6.0V. 6. When testing, choose either TTL or IBM input levels.444499999999999999999999999999995,85,8885,85,8885,85,85,85,8885,85,85,85,8885,85,85,85,85,85,8881,161,161,5,161,5,161,161,161,5,161,5,161,161,161,161,161,5,161,5,161,161,161,161,161,5,161,5,161,161,161,161,161,161,161,5,161,5,16http://onsemi.com303

MC10129Figure 2. SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°CVin+5.0 VdcVCC+7.0 VdcVoutCoax0.1 µ F25 µF0.1 µFCoaxInputD07D14Q0C RPulse GeneratorInput Pulset+ = t– = 5.5 ± 0.5 ns(10 to 90%)13D1D15Q1Unused Inputs (D)must be tied toVCC or Pin 16C R50-ohm termination to ground locatedin each scope channel input.All input and output cables to thescope are equal lengths of 50-ohmcoaxial cable. Wire length should be< 1/4 inch from TPin to input pin andTPout to output pin.D2D364DC RD32Q2Q3Unused outputsconnected to a50-ohm resistorto ground.HysteresisControl 5C RClock 11Reset 10Strobe 121 16825 µF 0.1 µF+ 2.0 Vdc–3.2 VdcVEENOTE: All power supplies and logic levels are shifted 2 volts positive.http://onsemi.com304

MC10129Figure 3 – DATA to OUTPUT(Clock and Reset are low, Strobe is high)Figure 4 – STROBE to OUTPUT(Data is high, Clock and Reset are low)Data50%t+t–+5.0 V+2.4 VStrobe50%t+t–+1.11 V+0.31 VQ80%50%20%+1.11 V+0.31 VQ80%50%20%+1.11 V+0.31 Vt7+14+t7–14–t12+14+t12–14–Figure 6 – CLOCK to OUTPUT(Reset is low, Strobe is high)Figure 5 – RESET to OUTPUT(Data and Strobe are high)Data+5.0 V+2.4 VReset50%+1.11 V+0.31 VClockQ50%t–50%t+80%50%20%+1.11 V+0.31 V+1.11 V+0.31 VClock+1.11 V50%t+t–+0.31 Vt11–14–t11–14+Figure 7 – TSET UP AND THOLD WAVEFORMSQ80%50%20%+1.11 V+0.31 VDtsetup50%50%thold+5.00 V+2.400 V+1.11 VC50%+0.31 Vt11–14+t10+14–Qhttp://onsemi.com305

The MC10131 is a dual master–slave type D flip–flop.Asynchronous Set (S) and Reset (R) override Clock (CC) and ClockEnable (CE) inputs. Each flip–flop may be clocked separately byholding the common clock in the low state and using the enable inputsfor the clocking function. If the common clock is to be used to clockthe flip–flop, the Clock Enable inputs must be in the low state. In thiscase, the enable inputs perform the function of controlling thecommon clock.The output states of the flip–flop change on the positive transition ofthe clock. A change in the information present at the data (D) inputwill not affect the output information at any other time due to masterslave construction.• PD = 235 mW typ/pkg (No Load)• FTog = 160 MHz typ• tpd = 3.0 ns typ• tr, tf = 2.5 ns typ (20%–80%)VCC1Q1Q1R1S1CE1D1VEEDIP PIN ASSIGNMENTS1 5D1 7C E1 6R1 4C C 9R2 13C E2 11D2 10S2 1212345678161514131211109LOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8Q1Q1Q2Q2VCC2Q2Q2R2S2CE2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.D2CC231415http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10131L CDIP–16 25 Units / RailMC10131P PDIP–16 25 Units / RailMC10131FN PLCC–20 46 Units / Rail1161MC10131LAWLYYWWMC10131PAWLYYWW110131AWLYYWWCLOCKED TRUTH TABLEC D Qn+1L X QnH L LH H HC = C E + C C. A clock H is a clock transition from a low to ahigh state.R–S TRUTH TABLER S Qn+1L L QnL H HH L LH H N.D.N.D. = Not Defined© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6306 Publication Order Number:MC10131/D

MC10131ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 62 45 56 62 mAdcInput Current IinH 45679IinL 4, 5*6, 7, 9*Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 22Threshold Voltage Logic 0 VOLA 23Switching Times (50Ω Load)Clock InputPropagation Delayt9+2–t9+2+t6+2+t6+2–22220.50.5–1.060–1.060–1.890–1.890–1.080–1.0801.71.71.71.7525525350390425–0.890–0.890–1.675–1.675–1.655–1.6550.50.5–0.960–0.960–1.850–1.850–0.980–0.980330330220245265–0.810–0.810–1.650–1.650–1.630–1.6300.30.3–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.0 4.6 1.1 2.5 4.5 1.1 4.9Fall Time (20 to 80%) t2– 2 1.0 4.6 1.1 2.5 4.5 1.1 4.94.64.64.64.61.81.81.81.83.03.03.03.04.54.54.54.51.81.81.81.8330330220245265–0.700–0.700–1.615–1.615–1.595–1.5955.05.05.05.0µAdcµAdcVdcVdcVdcVdcnsSet InputnsPropagation Delayt5+2+t12+15+t5+3–t12+14–2153141.71.71.71.74.44.44.44.41.81.81.81.82.82.82.82.84.34.34.34.31.81.81.81.84.84.84.84.8Reset InputnsPropagation Delayt4+2–t13+15–t4+3–t13+14+2153141.71.71.71.74.44.44.44.41.81.81.81.82.82.82.82.84.34.34.34.31.81.81.81.84.84.84.84.8Setup Time tsetup 7 2.5 2.5 2.5 nsHold Time thold 7 1.5 1.5 1.5 nsToggle Frequency (Max) ftog 2 125 125 160 125 MHz* Individually test each input applying VIH or VIL to input under test.Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)VIHmaxVILminhttp://onsemi.com307

MC10131ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 45679IinL 4, 5*6, 7, 9*Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 22Threshold Voltage Logic 0 VOLA 23456795757**57 957 9888888888888888(VCC)GndSwitching Times (50Ω Load)Clock Input +1.11Vdc Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt9+2–t9+2+t6+2+t6+2–222277Rise Time (20 to 80%) t2+ 2 7 9 2 8 1, 16Fall Time (20 to 80%) t2– 2 9 2 8 1, 169966222288881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16Set InputPropagation Delayt5+2+t12+15+t5+3–t12+14–2153146951251221531488881, 161, 161, 161, 16Reset InputPropagation Delayt4+2–t13+15–t4+3–t13+14+2153146941341321531488881, 161, 161, 161, 16Setup Time tsetup 7 6, 7 2 8 1, 16Hold Time thold 7 6, 7 2 8 1, 16Toggle Frequency (Max) ftog 2 6 2 8 1, 16* Individually test each input applying VIH or VIL to input under test.VIHmaxOutput level to be measured after a clock pulse has been applied to the CE Input (Pin 6)VILminEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com308

The MC10133 is a high speed, low power, quad latch consisting offour bistable latch circuits with D type inputs and gated Q outputs,allowing direct wiring to a bus. When the clock is high, outputs willfollow D inputs. Information is latched on the negative goingtransition of the clock.The outputs are gated when the output enable (G) is low. All fourlatches may be clocked at one time with the common clock (CC), oreach half may be clocked separately with its clock enable (CE).• PD=310 mW typ/pkg (No Load)• tpd= 4.0 ns typ• tr, tf= 2.0 ns typ (20%–80%)D0G0D1CECCCED2G135741312910LOGIC DIAGRAMQ0Q1Q22 Q06 Q1VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 811 Q2http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10133LAWLYYWWMC10133PAWLYYWW110133AWLYYWWD314Q3DIP PIN ASSIGNMENT15 Q3A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekVCC1Q0D0CEG0123451615141312VCC2Q3D3CCCETRUTH TABLEG C D Qn+1HLLLC = CC = CEXLHHXXLHLQnLHQ1D1VEE67811109Q2G1D2ORDERING INFORMATIONDevice Package ShippingMC10133L CDIP–16 25 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.MC10133P PDIP–16 25 Units / RailMC10133FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7309 Publication Order Number:MC10133/D

MC10133ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 82 75 82 mAdcInput Current IinH 34513Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 222Threshold Voltage Logic 1 VOHA 22222222Threshold Voltage Logic 0 VOLA 222222Switching Times (50Ω Load)Propagation Delay390425560560245265350350245265350350µAdcIinL 3 0.5 0.5 0.3 µAdct3+2+t4+2+t5–2+tsetupthold22233–1.060–1.060–1.890–1.890–1.890–1.080–1.080–1.080–1.080–1.080–1.080–1.080–1.0801.01.01.02.51.5–0.890–0.890–1.675–1.675–1.675–1.655–1.655–1.655–1.655–1.655–1.655–0.960–0.960–1.850–1.850–1.850–0.980–0.980–0.980–0.980–0.980–0.980–0.980–0.980–0.810–0.810–1.650–1.650–1.650–1.630–1.630–1.630–1.630–1.630–1.630–0.890–0.890–1.825–1.825–1.825–0.910–0.910–0.910–0.910–0.910–0.910–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.0 3.6 1.1 2.0 3.5 1.1 3.8Fall Time (20 to 80%) t2– 2 1.0 3.6 1.1 2.0 3.5 1.1 3.85.65.43.2–0.700–0.700–1.615–1.615–1.615–1.595–1.595–1.595–1.595–1.595–1.595Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)VIHmaxVILminData input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured afterdevice has latched.* Latch set to zero state before test.1.01.01.02.51.54.04.02.00.70.75.45.43.11.11.21.02.51.55.96.03.4VdcVdcVdcVdcnshttp://onsemi.com310

MC10133ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 13 8 1, 16Input Current IinH 34513Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 222Threshold Voltage Logic 1 VOHA 22222222Threshold Voltage Logic 0 VOLA 222222345138888(VCC)Gnd1, 161, 161, 161, 16IinL 3 3 8 1, 163, 43, 13133, 5, 1343, 443, 43333, 44433Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt3+2+t4+2+t5–2+tsetupthold2223343*Rise Time (20 to 80%) t2+ 2 4 3 2 8 1, 16Fall Time (20 to 80%) t2– 2 4 3 2 8 1, 16Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)3334135345335431322222VIHmaxVILminData input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured afterdevice has latched.* Latch set to zero state before test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.8888888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com311

The MC10134 is a dual multiplexer with clocked D type latches.Each latch may be clocked separately by holding the common clock inthe low state, and using the clock enable inputs for the clockingfunction. If the common clock is to be used to clock the latch, the clockenable (CE) inputs must be in the low state. In this mode, the enableinputs perform the function of controlling the common clock (CC).The data select inputs determine which data input is enabled. A high(H) level on the A0 input enables data input D12 and a low (L) level onthe A0 input enables data input D11. A high (H) level on the A1 inputenables data input D22 and a low (L) level on the A1 input enablesdata input D21.Any change on the data input will be reflected at the outputs whilethe clock is low. The outputs are latched on the positive transition ofthe clock. While the clock is in the high state, a change in theinformation present at the data inputs will not affect the outputinformation.• PD = 225 mW typ/pkg (No Load)• tpd = 3.0 ns typ• tr, tf = 2.5 ns typ (20%–80%)A0A1D11D12CEOCCCE1D21D226114510791312VCC1Q1Q1D11D12A0CCVEELOGIC DIAGRAMDIP PIN ASSIGNMENT12345678161514131211109VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8VCC2Q2Q2D21D22A1CEOCE12 Q13 Q115 Q214 Q2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10134L CDIP–16 25 Units / RailMC10134P PDIP–16 25 Units / RailMC10134FN PLCC–20 46 Units / Rail1161MC10134LAWLYYWWMC10134PAWLYYWW110134AWLYYWWTRUTH TABLEC A0 D11 D12 Qn+1LLLLHC = CE + CCLLHHXLHXXXXXLHXLHLHQn© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6312 Publication Order Number:MC10134/D

MC10134ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 60 55 60 mAdcInput Current IinH 456710Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 22Threshold Voltage Logic 1 VOHA 22Threshold Voltage Logic 0 VOLA 22Switching Times (50Ω Load)Propagation DelaySetup TimeHold TimeDataClockSelectDataSelectDataSelect460460425460425290290265290265290290265290265µAdcIinL 4* 0.5 0.5 0.3 µAdct4+2+t10–2+t6+2+tsetuptsetuptholdthold2222222–1.060–1.060–1.890–1.890–1.080–1.0801.01.01.02.53.51.51.0–0.890–0.890–1.675–1.675–1.655–1.6553.56.04.8–0.960–0.960–1.850–1.850–0.980–0.9801.01.01.0–0.810–0.810–1.650–1.650–1.630–1.6303.35.74.6–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.5 3.7 1.5 3.5 1.5 3.8Fall Time (20 to 80%) t2– 2 1.5 3.7 1.5 3.5 1.5 3.8* All other inputs tested in the same manner.2.53.51.51.01.01.01.02.53.51.51.0–0.700–0.700–1.615–1.615–1.595–1.5953.66.35.0VdcVdcVdcVdcnshttp://onsemi.com313

MC10134ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 456710Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 22 6Threshold Voltage Logic 1 VOHA 22 6Threshold Voltage Logic 0 VOLA 22 6456710888(VCC)Gnd1, 161, 161, 16IinL 4* 4 8 1, 1645,66,7,107,104,6,7,105,7,10Switching Times (50Ω Load) +1.11 V +0.31 V Pulse In Pulse Out –3.2 V +2.0 VPropagation DelaySetup TimeHold TimeDataClockSelectDataSelectDataSelectt4+2+t10–2+t6+2+tsetuptsetuptholdthold2224522 522 5Rise Time (20 to 80%) t2+ 2 6,7,10 4 2 8 1, 16Fall Time (20 to 80%) t2– 2 6,7,10 4 2 8 1, 16* All other inputs tested in the same manner.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.6,7,107,106,7,107,106,7,1077,106,77,116,77,114541064,106,104,106,104522222228888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com314

The MC10135 is a dual master–slave dc coupled J–K flip–flop.Asynchro– nous set (S) and reset (R) are provided. The set and resetinputs override the clock.A common clock is provided with separate J–K inputs. When theclock is static, the J–K inputs do not effect the output.The output states of the flip–flop change on the positive transition ofthe clock.• PD = 280 mW typ/pkg (No Load)• fTog = 140 MHz typ• tpd = 3.0 ns typ• tr, tf = 2.5 ns typ (20%–80%)http://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10135LAWLYYWWVCC1Q1Q1R1S1K1J1VEEDIP PIN ASSIGNMENT12345678161514131211109VCC2Q2Q2R2S2K2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin ConversionTables on page 18.J2CS1 5J1 7K1 6R1 4C 9S2 12J2 10K2 11R2 13LOGIC DIAGRAMQ1Q1Q2Q2VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8231514PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATION1MC10135PAWLYYWW110135AWLYYWWR–S TRUTH TABLECLOCK J–K TRUTH TABLE*R S Qn+1 J K Qn+1LLHHLHLHQnHLN.D.LHLHLLHHQnLHQnDevice Package ShippingMC10135L CDIP–16 25 Units / RailMC10135P PDIP–16 25 Units / RailMC10135FN PLCC–20 46 Units / RailN.D. = Not Defined*Output states change on positivetransition of clock for J–K inputcondition present.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6315 Publication Order Number:MC10135/D

MC10135ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 75 54 68 75 mAdcInput Current IinH 6,7,9,10,114,5,12,13IinL 4,5,6,7,9,10,11,12,13Output Voltage Logic 1 VOH 22 (3.)Output Voltage Logic 0 VOL 33 (3.)Threshold Voltage Logic 1 VOHA 22 (4.)Threshold Voltage Logic 0 VOLA 33 (4.)Switching Times (50Ω Load)Clock InputPropagation Delayt9+2+t9+2–220.50.5–1.060–1.060–1.890–1.890–1.080–1.0801.81.8425620–0.890–0.890–1.675–1.675–1.655–1.6550.50.5–0.960–0.960–1.850–1.850–0.980–0.980265390–0.810–0.810–1.650–1.650–1.630–1.6300.30.3–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+, t3+ 2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.7Fall Time (20 to 80%) t2–, t3– 2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.75.05.01.81.83.03.04.54.51.81.8265390–0.700–0.700–1.615–1.615–1.595–1.5954.64.6µAdcµAdcVdcVdcVdcVdcnsSet InputnsPropagation Delayt5+2+t12+15+t5+3–t12+14–2153141.81.81.81.85.65.65.65.61.81.81.81.83.03.03.03.05.05.05.05.01.8 5.25.25.25.2Reset InputnsPropagation Delayt4+2–t4+3–t13+15–t13+14+2315141.81.81.81.85.65.65.65.61.81.81.81.83.03.03.03.05.05.05.05.01.81.81.81.85.25.25.25.2Setup Time tsetup 7 2.5 2.5 1.0 2.5 nsHold Time thold 7 1.5 1.5 1.0 2.5 nsToggle Frequency (Max) ftog 2 125 125 140 125 MHz1. Individually test each input; apply VIHmax to pin under test.2. Individually test each input; apply VILmin to pin under test.3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)VIHmaxVILminVIHAmaxVILAminhttp://onsemi.com316

MC10135ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 6,7,9,10,114,5,12,13IinL 4,5,6,7,9,10,11,12,13Output Voltage Logic 1 VOH 22 (3.)Output Voltage Logic 0 VOL 33 (3.)Note 1.Note 1.Threshold Voltage Logic 1 VOHA 22 (4.) 6Threshold Voltage Logic 0 VOLA 33 (4.) 65656Note 2.Note 2.888888885 885 88(VCC)GndSwitching Times (50Ω Load)Clock Input Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt9+2+t9+2–22Rise Time (20 to 80%) t2+, t3+ 2, 3 9 2, 3 8 1, 16Fall Time (20 to 80%) t2–, t3– 2, 3 9 2, 3 8 1, 169922881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16Set InputPropagation Delayt5+2+t12+15+t5+3–t12+14–21531451251221531488881, 161, 161, 161, 16Reset InputPropagation Delayt4+2–t4+3–t13+15–t13+14+23151444131323151488881, 161, 161, 161, 16Setup Time tsetup 7 6, 9 2 8 1, 16Hold Time thold 7 6, 9 2 8 1, 16Toggle Frequency (Max) ftog 2 9 2 8 1, 161. Individually test each input; apply VIHmax to pin under test.2. Individually test each input; apply VILmin to pin under test.3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)VIHmaxVILminVIHAmax4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)VILAminEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com317

The MC10136 is a high speed synchronous counter that can countup, count down, preset, or stop count at frequencies exceeding 100MHz. The flexibility of this device allows the designer to use one basiccounter for most applications, and the synchronous count featuremakes the MC10136 suitable for either computers or instrumentation.Three control lines (S1, S2, and Carry In) determine the operationmode of the counter. Lines S1 and S2 determine one of fouroperations; preset (program), increment (count up), decrement (countdown), or hold (stop count). Note that in the preset mode a clock pulseis necessary to load the counter, and the information present on thedata inputs (D0, D1, D2, and D3) will be entered into the counter.Carry Out goes low on the terminal count, or when the counter is beingpreset.This device is not designed for use with gated clocks. Control is viaS1 and S2.• PD = 625 mW typ/pkg (No Load)• fcount = 150 MHz typ• tpd = 3.3 ns typ (C-Q)• 7.0 ns typ (C-Cout)• 5.0 ns typ (Cin-Cout)DIP PIN ASSIGNMENThttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10136LAWLYYWWMC10136PAWLYYWW110136AWLYYWWVCC1Q2Q3123161514VCC2Q1Q0A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekCout413CLOCKD3512D0ORDERING INFORMATIOND2611D1Device Package ShippingS2VEE78109CinS1MC10136L CDIP–16 25 Units / RailMC10136P PDIP–16 25 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page18.MC10136FN PLCC–20 46 Units / RailFUNCTION TABLECin S1 S2 Operating ModeX L L Preset (Program)L L H Increment (Count Up)H L H Hold CountL H L Decrement (Count Down)H H L Hold CountX H H Hold (Stop Count)© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6318 Publication Order Number:MC10136/D

MC10136LOGIC DIAGRAMS1 9S2 7Carry In10TTQ0Q0CT Q1T Q1T CTTQ3C T T CTVCC1 = PIN 1VCC2 = PIN 16T Q2TTTQ3VEE = PIN 8Clock1312 D0 14 Q0 11 D1 15 Q1 6 D2 2 Q2 5 D3 3 Q3 4 Carry OutNOTE: Flip-flops will toggle when all T inputs are low.SEQUENTIAL TRUTH TABLE*INPUTSS1 S2 D0 D1 D2 D3CarryInOUTPUTSClock** Q0 Q1 Q2 Q3CarryOutL L L L H H X H L L H H LL H X X X X L H H L H H HL H X X X X L H L H H H HL H X X X X L H H H H H LL H X X X X H L H H H H HL H X X X X H H H H H H HH H X X X X X H H H H H HL L H H L L X H H H L L LH L X X X X L H L H L L HH L X X X X L H H L L L HH L X X X X L H L L L L LH L X X X X L H H H H H H* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.** A clock H is defined as a clock input transition from a low to a high logic level.http://onsemi.com319

MC10136ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 138 100 125 138 mAdcInput Current IinH 5,6,11,1279,1013350425390460220265245290220265245290µAdcIinL All 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 14 (2.) –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 14 (2.) –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load) nsPropagation DelayClock InputCarry In to Carry Outt13+14+t13+14–t13+4+t13+4–t10–4–t10+4+Setup Time Data Inputs t12+13+t12–13+Select Inputs t9+13+t7+13+Carry In Input t10–13+t10+13+Hold Time Data Inputs t13+12+t13+12–Select Inputs t13+9+t13+7+Carry In Input t13+10–t13+10+Counting FrequencyfcountupfcountdownRise Time (20 to 80%) t4+t14+Fall Time (20 to 80%) t4–t14–1414444 (3.)414141414141414141414141414144144140.80.82.02.01.61.63.53.56.06.02.51.500–1.0–1.0001251250.90.90.90.91. Individually test each input; apply VILmin to pin under test.2. Measure output after clock pulse VIH appears at clock input (Pin 13).VIL3. Before test set all Q outputs to a logic high.4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C onlywhen 500lfpm blown air or equivalent heat sinking is provided.4.84.810.910.97.47.43.33.33.33.31.01.02.52.51.61.63.53.56.06.02.51.500–1.0–1.0001251251.11.11.11.13.33.37.07.05.05.01501502.02.02.02.04.54.510.510.56.96.93.33.33.33.31.41.42.42.41.91.93.53.56.06.03.01.500–1.0–1.0001251251.11.11.11.15.05.011.511.57.57.53.53.53.53.5MHznshttp://onsemi.com320

MC10136ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 5,6,11,1279,10135,6,11,1279,10138888(VCC)Gnd1, 161, 161, 161, 16IinL All Note 1. 8 1, 16Output Voltage Logic 1 VOH 14 (2.) 12 7, 9 8 1, 16Output Voltage Logic 0 VOL 14 (2.) 7, 9 8 1, 16Threshold Voltage Logic 1 VOHA 14 (2.) 7, 9 12 8 1, 16Threshold Voltage Logic 0 VOLA 14 (2.) 7, 9 12 8 1, 16Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delay Clock Input t13+14+ 14 1213 14 8 1, 16t13+14– 1413 14 8 1, 16t13+4+ 4 713 48 1, 16t13+4– 4 713 48 1, 16Carry In to Carry Outt10–4–t10+4+Setup Time Data Inputs t12+13+t12–13+Select Inputs t9+13+t7+13+Carry In Inputs t10–13+t10+13+Hold Time Data Inputs t13+12+t13+12–Select Inputs t13+9+t13+7+Carry In Inputs t13+10–t13+10+Counting FrequencyfcountupfcountdownRise Time (20 to 80%) t4+t14+Fall Time (20 to 80%) t4–t14–4 (3.)4141414141414141414141414141441441477777779777713137, 97, 9997, 97, 9101012, 1312, 139, 137, 1310, 1310, 1312, 1312, 139, 137, 139 10, 1310, 131. Individually test each input; apply VILmin to pin under test.2. Measure output after clock pulse VIH appears at clock input (Pin 13).VIL3. Before test set all Q outputs to a logic high.4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C onlywhen 500lfpm blown air or equivalent heat sinking is provided.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.131313131313441414141414141414141414141414414414888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com321

MC10136SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°CVINVCC1 = VCC2 = +2.0 VDCVOUTNOTE:tsetup is the minimum time before the positivetransition of the clock pulse (C) that information mustbe present at the input D or S.thold is the minimum time after the positive transitionof the clock pulse (C) that information mustremain unchanged at the input D or S.INPUT PULSET+ = T– = 2.0 ±0.2 NS(20 TO 80%)ClockQ Output50%tC+Q+80%50%20%tQ+tC+Q–tQ–CLOCKINPUT+1.11 V+0.31 VCOAXTPin25 µF1CIN Q0CD0Q1D1D2Q2D3 Q3S1S2 COUT816VEE = –3.2 VDC0.1 µF0.1 µFCOAXTPoutD or SCQ50%t hold Htsetup H50%t hold Ltsetup L+1.11 V+0.31 V50-ohm termination to ground locatedin each scope channel input.All input and output cables to thescope are equal lengths of 50-ohmcoaxial cable. Wire length should be< 1/4 inch from TPin to input pin andTPout to output pin.Unused outputs are connected to a50-ohm resistor to ground.CARRY INSET UP AND HOLD TIMESCarry intset (L)thold (L)tset (N)thold (N)Chttp://onsemi.com322

MC10136APPLICATIONS INFORMATIONTo provide more than four bits of counting capabilityseveral MC10136 counters may be cascaded. The Carry Ininput overrides the clock when the counter is either in theincrement mode or the decrement mode of operation. Thisinput allows several devices to be cascaded in a fullysynchronous multistage counter as illustrated in Figure 1.The carry is advanced between stages as shown with noexternal gating. The Carry In of the first device may be leftopen. The system clock is common to all devices.The various operational modes of the counter make ituseful for a wide variety of applications. If used with MECLIII devices, prescalers with input toggle frequencies inexcess of 300 MHz are possible. Figure 2 shows such aprescaler using the MC10136 and MC1670. Use of theMC10231 in place of the MC1670 permits 200 MHzoperation.The MC10136 may also be used as a programmablecounter. The configuration of Figure 3 requires no additionalgates, although maximum frequency is limited to about 50MHz. The divider modulus is equal to the program inputplus one (M = N + 1), therefore, the counter will divide bya modulus varying from 1 to 16.A second programmable configuration is also illustratedin Figure 4. A pulse swallowing technique is used to speedthe counter operation up to 110 MHz typically. The dividermodulus for this figure is equal to the program input (M =N). The minimum modulus is 2 because of the pulseswallowing technique, and the modulus may vary from 2 to15. This programmable configuration requires an additionalgate, such as 1/2MC10109 and a flip-flop such as1/2MC10131.SystemClockFigure 1. 12 BIT SYNCHRONOUS COUNTERLSBNOTE: S1 and S2 are set either for increment or decrement operation.Figure 2. 300 MHz PRESCALERLogic HighQ0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3C in C out C in C outD QCCCInput CFrequencyQMC1670MSBMC10136S1S2CQ3Input Frequency32C in1 f out =Figure 3. 50 MHz PROGRAMMABLE COUNTERFigure 4. 100 MHz PROGRAMMABLE COUNTERProgram InputProgram Inputf in CD0 D1 D2 D3S2 MC10136fD0 D1 D2 D3inCS1C inC outfS2outQ0 Q2 Q3S1DQf out1 f out =f inProgram Input + 12 f max ≅ 50 MHz Typ.3 Divide Ratio is from 1 to 16.1/2MC10109f inProgram Input2 f max ≅ 110 MHz Typ.3 Divide Ratio is from 2 to 15.C1/2MC10131Qhttp://onsemi.com323

The MC10137 is a high speed synchronous counter that can countup, down, preset, or stop count at frequencies exceeding 100 MHz.The flexibility of this device allows the designer to use one basiccounter for most applications. The synchronous count feature makesthe MC10137 suitable for either computers or instrumentation.Three control lines (S1, S2, and Carry In) determine the operationmode of the counter. Lines S1 and S2 determine one of fouroperations; preset (program), increment (count up), decrement (countdown), or hold (stop count). Note that in the preset mode a clock pulseis necessary to load the counter, and the information present on thedata inputs (D0, D1, D2, and D3) will be entered into the counter.Carry Out goes low on the terminal count. The Carry Out on theMC10137 is partially decoded from Q1 and Q2 directly, so in thepreset mode the condition of the Carry Out after the Clock’s positiveexcursion will depend on the condition of Q1 and/or Q2. The counterchanges state only on the positive going edge of the clock. Any otherinput may change at any time except during the positive transition ofthe clock. The sequence for counting out of improper states is asshown in the State Diagrams.• PD = 625 mW typ/pkg (No Load)• fcount = 150 MHz typ• tpd = 3.3 ns typ (C–Q)• = 7.0 ns typ (C–Cout)• = 5.0 ns typ (Cin–Cout)COUNT UP1514COUNT DOWNSTATE DIAGRAMS0 1 2 3 49 8 7 6 50 1 2 3 4129 8 7 6 5VCC123COUTD3D2S2VEE13DIP PIN ASSIGNMENT123456781615141312111091012VCC2Q1Q0CD0D1CINS1Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.111413151110http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10137L CDIP–16 25 Units / RailMC10137P PDIP–16 25 Units / RailMC10137FN PLCC–20 46 Units / Rail1161MC10137LAWLYYWWMC10137PAWLYYWW110137AWLYYWWFUNCTION SELECT TABLES1 S2 Operating ModeL L Preset (Program)L H Increment (Count Up)H L Decrement (Count Down)H H Hold (Stop Count)© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6324 Publication Order Number:MC10137/D

MC10137LOGIC DIAGRAMS1 9S2 710Carry InTTQ0Q0CTJTTQ1Q1CKTTJTQ2Q2CJTJTTQ3Q3C13ClockVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 812 D0 14 Q0 11 D1 15 Q1 6D2 2Q2 5D3 3Q3 4 Carry OutNOTE: Flip–flops will toggle when all T inputs are low.INPUTSSEQUENTIAL TRUTH TABLE*OUTPUTSS1 S2 D0 D1 D2 D3CarryInClock** Q0 Q1 Q2 Q3CarryOutL L H H H L X H H H H L HL H X X X X L H L L L H HL H X X X X L H H L L H LL H X X X X L H L L L L HL H X X X X L H H L L L HL H X X X X H L H L L L HL H X X X X H H H L L L HH H X X X X X H H L L L HL L H H L L X H H H L L HH L X X X X L H L H L L HH L X X X X L H H L L L HH L X X X X L H L L L L L* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.** A clock H is defined as a clock input transition from a low to a high logic level.http://onsemi.com325

MC10137ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 165 120 150 165 mAdcInput Current IinH 5,6,11,1279,1013350425390460220265245290220265245290µAdcIinL All 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 14 (2.) –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 14 (2.) –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load) nsPropagation DelayClock InputCarry In to Carry Outt13+14+t13+14–t13+4+t13+4–t10–4–t10+4+Setup Time Data Inputs t12+13+t12–13+Select Inputs t9+13+t7+13+Carry In Input t10–13+t13+10+Hold Time Data Inputs t13+12+t13+12–Select Inputs t13+9+t13+7+Carry In Input t13+10–t10+13+Counting FrequencyfcountupfcountdownRise Time (20 to 80%) t4+t14+Fall Time (20 to 80%) t4–t14–1414444 (3.)414141414141414141414141414144144141. Individually apply VILmin to pin under test.2. Measure output after clock pulse VIHVIL3. Before test set Q1 and Q2 outputs to a logic low.0.80.82.02.01.61.63.53.57.57.54.5–1.000–2.5–2.5–1.64.01251250.90.90.90.94.84.810.910.97.47.43.33.33.33.31.01.02.52.51.61.63.53.57.57.53.7–1.000–2.5–2.5–1.63.11251251.11.11.11.1appears at clock input (Pin 13).3.33.37.07.05.05.01501502.02.02.02.04.54.510.510.56.96.93.33.33.33.31.11.12.42.41.91.93.53.57.57.54.5–1.000–2.5–2.5–1.64.01251251.11.11.11.15.05.011.511.57.57.53.53.53.53.5MHznshttp://onsemi.com326

MC10137ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 5,6,11,1279,10135,6,11,1279,10138888(VCC)Gnd1, 161, 161, 161, 16IinL All Note 1. 8 1, 16Output Voltage Logic 1 VOH 14 (2.) 12 7, 9 8 1, 16Output Voltage Logic 0 VOL 14 (2.) 7, 9 8 1, 16Threshold Voltage Logic 1 VOHA 14 (2.) 7, 9 12 8 1, 16Threshold Voltage Logic 0 VOLA 14 (2.) 7, 9 12 8 1, 16Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delay Clock Input t13+14+ 14 1213 14 8 1, 16t13+14– 1413 14 8 1, 16t13+4+ 4 713 48 1, 16t13+4– 4 713 48 1, 16Carry In to Carry Outt10–4–t10+4+Setup Time Data Inputs t12+13+t12–13+Select Inputs t9+13+t7+13+Carry In Inputs t10–13+t13+10+Hold Time Data Inputs t13+12+t13+12–Select Inputs t13+9+t13+7+Carry In Inputs t13+10–t10+13+Counting FrequencyfcountupfcountdownRise Time (20 to 80%) t4+t14+Fall Time (20 to 80%) t4–t14–4 (3.)41414141414141414777713137, 97, 9997, 97, 91. Individually test each input; apply VILmin to pin under test.2. Measure output after clock pulse VIH appears at clock input (Pin 13).VIL3. Before test set all Q outputs to a logic high.1414141414144144147779777799101012, 1312, 139, 137, 1310, 1310, 1312, 1312, 139, 137, 1310, 1310, 13Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.131313131313441414141414141414141414141414414414888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com327

MC10137SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°CCarry In(b)(a) is the minimum time to wait after thecounter has been enabled to clock it.Clock(a)(b) is the minimum time before the counterhas been disabled that it may be clocked.(c) is the minimum time before the counteris enabled that a clock pulse may beapplied with no effect on the state of thecounter.Carry in(c)(d) is the minimum time to wait after thecounter is disabled that a clock pulse maybe applied with no effect in the state of thecounter.(b) and (c) may be negative numbers.Clock(d)VinVCC1 = VCC2 = +2.0 VdcVoutNOTE:tsetup is the minimum time before the positivetransition of the clock pulse (C) that information mustbe present at the input D or S.thold is the minimum time after the positivetransition of the clock pulse (C) that information mustremain unchanged at the input D or S.Coax25 µF1Cin16Q00.1 µFCoaxInput Pulset+ = t– = 2.0 ±0.2 ns(20 to 80%)Clock InputCD0D1D2Q1Q2+1.11 VTPinD3S1Q3TPoutClock50%tC+Q+tC+Q–+0.31 VS2Cout8Q Output80%50%20%tQ+tQ–VEE = –3.2 Vdc0.1 µFC50%+1.11 V+0.31 Vthold Hthold L50-ohm termination to ground locatedin each scope channel input.D or Stsetup H50%tsetup LAll input and output cables to thescope are equal lengths of 50-ohmcoaxial cable. Wire length should be< 1/4 inch from TPin to input pin andTPout to output pin.QUnused outputs are connected to a50-ohm resistor to ground.http://onsemi.com328

The MC10138 is a four bit counter capable of divide by two, five, orten functions. It is composed of four set–reset master–slave flip–flops.Clock inputs trigger on the positive going edge of the clock pulse.Set or reset input override the clock, allowing asynchronous “set” or“clear.” Individual set and common reset inputs are provided, as wellas complementary outputs for the first and fourth bits.• PD = 370 mW typ/pkg (No Load)• ftog = 150 MHz typ• tr, tf = 2.5 ns typ (20%–80%)12Clock9ResetS011SD1 QQ’C1 QRQ01514Q0VCC1Q3LOGIC DIAGRAM6S1 Q1S2 Q210 134C2 7 SSD1D2QQ’D1C1QQ’C2 QC2 QRRVCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8DIP PIN ASSIGNMENT121615VCC2Q0S35SD1 Q’D2QC2 QRQ323Q3http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1161MARKINGDIAGRAMSMC10138LAWLYYWWMC10138PAWLYYWW110138AWLYYWWQ3Q2S3S2C2VEE34567814131211109Q0Q1C1S0S1RESETORDERING INFORMATIONDevice Package ShippingMC10138L CDIP–16 25 Units / RailMC10138P PDIP–16 25 Units / RailMC10138FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6329 Publication Order Number:MC10138/D

MC10138BI–QUINARY(Clock connected to C2and Q3 connected to C1)COUNTER TRUTH TABLESBCD(Clock connected to C1and Q0 connected to C2)COUNT Q1 Q2 Q3 Q0 COUNT Q0 Q1 Q2 Q30 L L L L 0 L L L L1 H L L L 1 H L L L2 L H L L 2 L H L L3 H H L L 3 H H L L4 L L H L 4 L L H L5 L L L H 5 H L H L6 H L L H 6 L H H L7 L H L H 7 H H H L8 H H L H 8 L L L H9 L L H H 9 H L L HCOUNTER STATE DIAGRAM — POSITIVE LOGICCLOCK CONNECTED TO C20Q0 CONNECTED TO C20 1 2 3 44 7 1141011651512133 29 8 7 6 5http://onsemi.com330

MC10138ELECTRICAL CHARACTERISTICSCharacteristicPower Supply Drain CurrentSymbolInput Current IinH 125,6,10,1179Output Voltage Logic 1 VOH 3,14 (3.)2,4,13,15 (2.)Output Voltage Logic 0 VOL 3,14 (2.)2,4,13,15 (3.)Threshold Voltage Logic 1 VOHA 2,4,13,15 (2.)3,14 (3.)13,15 (2.)Threshold Voltage Logic 0 VOLA 2,4,13,15 (3.)3,14 (2.)13,15 (3.)Switching Times (50ΩLoad)PropagationDelaySet DelayReset DelayClock DelaysTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitIE 8 97 70 88 97 mAdc350390460650220245290410220245290µAdcIinL All 0.5 0.5 0.3 µAdct12+15+t12+14+t7+13+t7+4+t7+2+t7+3+t12+15–t12+14–t7+13–t7+4–t7+2–t7+3–t11+15+t11+14–t9+14+t9+15–Rise Time (20 to 80%) t14+t15+151413423151413423151414151415Fall Time (20 to 80%) t14– 14t15– 15Counting Frequency fcount 215–1.060–1.060–1.890–1.890–1.080–1.080–1.0801.41.41.41.41.41.41.41.41.41.41.41.41.41.41.41.41.11.11.11.1125125–0.890–0.890–1.675–1.675–1.655–1.655–1.6555.05.05.25.25.25.25.05.05.25.25.25.25.25.25.25.24.74.7–0.960–0.960–1.850–1.850–0.980–0.980–0.9801.51.51.51.51.51.51.51.51.51.51.51.51.51.51.51.51.11.13.53.53.53.53.53.53.53.53.53.53.53.52.52.5–0.810–0.810–1.650–1.650–1.630–1.630–1.6304.84.85.05.05.05.04.84.85.05.05.05.05.05.05.05.04.54.5–0.890–0.890–1.825–1.825–0.910–0.910–0.9101.51.51.51.51.51.51.51.51.51.51.51.51.51.51.51.51.11.1–0.700–0.700–1.615–1.615–1.595–1.595–1.5951. Individually test each input; apply VILmin to pin under test.2. Set all four flip–flops by applying pulseVIHmaxto pins 5, 6, 10, and 11 prior to applying test voltage indicated.VILmin3. Reset all four flip–flops by applying pulseVIHmaxVILminto pin 9 prior to applying test voltage indicated.4.74.71.11.11251252.52.51501504.54.51.11.11251255.35.35.55.55.55.55.35.35.55.55.55.55.55.55.55.55.05.05.05.0VdcVdcVdcVdcnsMHzhttp://onsemi.com331

MC10138ELECTRICAL CHARACTERISTICS (continued)NOTE: Each MECL 10,000 series circuit hasbeen designed to meet the dc specificationsTEST VOLTAGE VALUES (Volts)shown in the test table, after thermalequilibrium has been established. The circuit @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEEis in a test socket or mounted on a printedcircuit board and transverse air flow greater–30°C –0.890 –1.890 –1.205 –1.500 –5.2than 500 linear fpm is maintained. Outputs areterminated through a 50–ohm resistor to –2.0volts. Test procedures are shown for only one+25°C –0.810 –1.850 –1.105 –1.475 –5.2gate. The other gates are tested in the samemanner. +85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWCharacteristicSymbolUnderTest VIHmax VILmin VIHAmin VILAmax VEE(VCC)GndPower Supply Drain Current IE 8 9 8 1, 16Input Current IinH 125,6,10,1179Output Voltage Logic 1 VOH 3,14 (3.)2,4,13,15 (2.)Output Voltage Logic 0 VOL 3,14 (2.)2,4,13,15 (3.)Threshold Voltage Logic 1 VOHA 2,4,13,15 (2.)3,14 (3.)13,15 (2.)Threshold Voltage Logic 0 VOLA 2,4,13,15 (3.)3,14 (2.)13,15 (3.)125,6,10,117988881, 161, 161, 161, 16IinL All Note 1. 8 1, 1695,6,10,115,6,10,1195,6,10,1197,125,6,10,1197,12Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delay Clock DelaysSet DelayReset Delayt12+15+t12+14+t7+13+t7+4+t7+2+t7+3+t12+15–t12+14–t7+13–t7+4–t7+2–t7+3–t11+15+t11+14–t9+14+t9+15–Rise Time (20 to 80%) t14+t15+151413423151413423151414151415Fall Time (20 to 80%) t14– 14t15– 15Counting Frequency fcount 2151. Individually test each input; apply VILmin to pin under test.2. Set all four flip–flops by applying pulseVIHmaxto pins 5, 6, 10, and 11 prior to applying test voltage indicated.VILmin3. Reset all four flip–flops by applying pulseVIHmaxVILminto pin 9 prior to applying test voltage indicated.12127777121277771111991111997121514134231514134231514141514151415215888888888888888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com332

The MC10141 is a four–bit universal shift register which performsshift left, or shift right, serial/parallel in, and serial/parallel outoperations with no external gating. Inputs S1 and S2 control the fourpossible operations of the register without external gating of the clock.The flip–flops shift information on the positive edge of the clock. Thefour operations are stop shift, shift left, shift right, and parallel entry ofdata. The other six inputs are all data type inputs; four for parallelentry data, and one for shifting in from the left (DL) and one forshifting in from the right (DR).• PD = 425 mW typ/pkg (No Load)• fShift = 200 MHz typ• tr, tf = 2.0 ns typ (20%–80%)S1S2DR1 of 4DecoderD3Parallel EnterShift RightShift LeftLOGIC DIAGRAMD2 D1 D0http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10141LAWLYYWWMC10141PAWLYYWW110141AWLYYWWHoldD QD QD QD QDLA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekCCCCCDIP PIN ASSIGNMENTVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8Q3Q2 Q1 Q0TRUTH TABLESELECTOUTPUTSS1 S2 OPERATING MODE Q0n+1 Q1n+1 Q2n+1 Q3n+1L L Parallel Entry D0 D1 D2 D3L H Shift Right* Q1n Q2n Q3n DRH L Shift Left* DL Q0n Q1n Q2nH H Stop Shift Q0n Q1n Q2n Q3n*Outputs as exist after pulse appears at “C” input with input conditions asshown. (Pulse = Positive transition of clock input).VCC1Q2Q3CDRD3S2VEE12345678161514131211109VCC2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.Q1Q0DLD0D1S1D2ORDERING INFORMATIONDevice Package ShippingMC10141L CDIP–16 25 Units / RailMC10141P PDIP–16 25 Units / RailMC10141FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6333 Publication Order Number:MC10141/D

MC10141SHIFT FREQUENCY TEST CIRCUITCOAXVIN25 uFVCC1 = VCC2+2.0 VDC0.1 µFVOUTCoaxAll input and output cables to thescope are equal lengths of 50–ohmcoaxial cable. Wire length should be< 1/4 inch from TPin to input pin andTPout to output pin.INPUTPULSE GENERATOR50–ohm termination to groundlocated in each scope channel input.DLCD0D1D2D3S1S2DR1 16Q0Q1Q2Q38TEST PROCEDURES:1. SET D1, D2, D3 = +0.31 VDC (LOGIC L)D0 = +1.11 VDC (LOGIC H)2. APPY CLOCK PULSE — VIH TO SET Q0 HIGH.VIL3. MAINTAIN CLOCK LOW.SET S1 = +0.31 VDC (LOGIC L)S2 = +1.11 VDC (LOGIC H)4. TEST SHIFT FREQUENCY0.1 µFVEE = –3.2VDChttp://onsemi.com334

MC10141ELECTRICAL CHARACTERISTICSCharacteristicPower Supply Drain CurrentSymbolInput Current IinH 5674Test LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitIE 8 112 82 102 112 mAdc350350390425220220245265220220245265µAdcIinL 12 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 3 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 3 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA(Note 1.)Threshold Voltage Logic 0 VOLA(Note 1.)Switching Times (50ΩLoad)Propagation DelaySetup TIme (tsetup)Hold Time (thold)t4+3+t12+4+t10+4+t4+12+333333333141414–1.080–1.080–1.080–1.0801.72.55.51.5–1.655–1.655–1.655–1.655–0.980–0.980–0.980–0.9803.9 1.82.55.01.5–1.630–1.630–1.630–1.630–0.910–0.910–0.910–0.9102.9 3.8 2.02.55.51.5Rise Time (20 to 80%) t3+ 3 1.0 3.4 1.1 2.0 3.3 1.1 3.6Fall Time (20 to 80%) t3– 3 1.0 3.4 1.1 2.0 3.3 1.1 3.6–1.595–1.595–1.595–1.595Shift Frequency fshift 150 150 200 150 MHz4.2VdcVdcns1. These tests to be performed in sequence as shown.P1VIHVILP2VIHAVILP3VILAVIL2. See shift frequency test circuit for test procedures.3. Reset to zero before performing test.4. Reset to one before performing test.http://onsemi.com335

MC10141ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEE P1 P2 P3Power Supply Drain Current IE 8 8 1, 16Input Current IinH 5674IinL 1256744,5,6,7,9,10,11,138888(VCC)Gnd1, 161, 161, 161, 1612 8 1, 16Output Voltage Logic 1 VOH 3 6 8 4 1, 16Output Voltage Logic 0 VOL 3 8 4 1, 16Threshold Voltage Logic 1 VOHA(Note 1.)Threshold Voltage Logic 0 VOLA(Note 1.)3333663333 6Note 3.Note 3.Note 4.Note 4.Switching Times (50Ω Load) –3.2 V +2.0 VPropagation DelaySetup TIme (tsetup)Hold Time (thold)t4+3+t12+4+t10+4+t4+12+3141414Rise Time (20 to 80%) t3+ 3 8 1, 16Fall Time (20 to 80%) t3– 3 8 1, 16Shift Frequency fshift Note 2. 8 1, 166767888888888888444444441, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161. These tests to be performed in sequence as shown.P1VIHVILP2VIHAVILP3VILAVIL2. See shift frequency test circuit for test procedures.3. Reset to zero before performing test.4. Reset to one before performing test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com336

The MC10153 is a high speed, low power, MECL quad latchconsisting of four bistable latch circuits with D type inputs and gatedQ outputs. Open emitters allow a large number of outputs to bewire-ORed together. Latch outputs are gated, allowing direct wiring toa bus. When the clock is low, outputs will follow D inputs. Informationis latched on positive going transition of the clock. The MC10153provides the same logic function as the MC10133, except for inversionof the clock.• PD = 310 mW typ/pkg (No Load)• tpd = 4.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)D0G0D1CECCCED2G135741312910LOGIC DIAGRAMQ0Q1Q22 Q06 Q1VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 811 Q2http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10153LAWLYYWWMC10153PAWLYYWW110153AWLYYWWD314Q3DIP PIN ASSIGNMENT15 Q3A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekVCC1Q0D0123161514VCC2Q3D3ORDERING INFORMATIONDevice Package ShippingCEG0Q1456131211CCCEQ2MC10153L CDIP–16 25 Units / RailMC10153P PDIP–16 25 Units / RailD1710G1MC10153FN PLCC–20 46 Units / RailVEE89D2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.TRUTH TABLEG C D Qn+1H X X LL H X QnL L L LL L H HC = C C + CE© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6337 Publication Order Number:MC10153/D

MC10153ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 83 75 83 mAdcInput Current IinH 34513Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 222Threshold Voltage Logic 1 VOHA 22222222Threshold Voltage Logic 0 VOLA 222222Switching Times (50Ω Load)Propagation Delay390390560460245245350290245245350290µAdcIinL 3 0.5 0.5 0.3 µAdct3+2+t4–2+t5–2+tsetupthold22233–1.060–1.060–1.890–1.890–1.890–1.080–1.080–1.080–1.080–1.080–1.080–1.080–1.0801.01.01.02.51.5–0.890–0.890–1.675–1.675–1.675–1.655–1.655–1.655–1.655–1.655–1.655–0.960–0.960–1.850–1.850–1.850–0.980–0.980–0.980–0.980–0.980–0.980–0.980–0.980–0.810–0.810–1.650–1.650–1.650–1.630–1.630–1.630–1.630–1.630–1.630–0.890–0.890–1.825–1.825–1.825–0.910–0.910–0.910–0.910–0.910–0.910–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.0 3.6 1.1 2.0 3.5 1.1 3.8Fall Time (20 to 80%) t2– 2 1.0 3.6 1.1 2.0 3.5 1.1 3.85.65.63.2–0.700–0.700–1.615–1.615–1.615–1.595–1.595–1.595–1.595–1.595–1.595Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)VIHmaxVILminData input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured afterdevice has latched.* Latch set to zero state before test.1.01.01.02.51.54.04.02.00.70.75.45.63.11.11.21.02.51.55.96.23.4VdcVdcVdcVdcnshttp://onsemi.com338

MC10153ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 13 8 1, 16Input Current IinH 34513Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 222Threshold Voltage Logic 1 VOHA 22222222Threshold Voltage Logic 0 VOLA 222222345138888(VCC)Gnd1, 161, 161, 161, 16IinL 3 3 8 1, 16333,533333333Switching Times (50Ω Load) +1.11 V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt3+2+t4–2+t5–2+tsetupthold222333*Rise Time (20 to 80%) t2+ 2 3 2 8 1, 16Fall Time (20 to 80%) t2– 2 3 2 8 1, 16Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)4133,13133,44444443534533541331322222VIHmaxVILminData input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured afterdevice has latched.* Latch set to zero state before test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.8888888888888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com339

The MC10154 is a four–bit counter capable of divide–by–two,divide–by– four, divide–by–eight or a divide–by–sixteen function.Clock inputs trigger on the positive going edge of the clock pulse.Set and Reset inputs override the clock, allowing asynchronous “set”or “clear.” Individual Set and common Reset inputs are provided, aswell as complemen– tary outputs for the first and fourth bits. Trueoutputs are available at all bits.• PD=370 mW typ/pkg (No Load)• ftoggle= 150 MHz (typ)• tpd=3.5 ns typ (C to Q0)• tpd=11 ns typ (C to Q3)12Clock 110Clock 2S011DSQQ’C1C2 QR Q ’Q0 S115 7LOGIC DIAGRAMDC1SQQ’R Q ’Q1S213 6DC1SQQ’R Q ’Q2 S34 5DSQQ’C1RQQ32http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10154LAWLYYWWMC10154PAWLYYWW110154AWLYYWW9Reset14Q0VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 83Q3A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekINPUTSTRUTH TABLEOUTPUTSR S0 S1 S2 S3 C1 C2 Q0 Q1 Q2 Q3HLLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLLHLLLLLLLLLLLLLLLLLLXXHX****************XXXH* Clock transitions from VIL to VIH may be applied to C1 or C2or both for same effect.VIL****************LHHLHLHLHLHLHLHLHLL LH HNo CountNo CountHHLLHHLLHHLLHHLLHHHHLLLLHHHHLLLLLHHHHHHHHHLLLLLLLLVIHVCC1Q3Q3Q2S3S2S1VEEDIP PIN ASSIGNMENT12345678161514131211109VCC2Q0Q0Q1CLOCK 1ORDERING INFORMATIONDevice Package ShippingMC10154L CDIP–16 25 Units / RailMC10154P PDIP–16 25 Units / RailMC10154FN PLCC–20 46 Units / RailS0CLOCK 2RESETPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6340 Publication Order Number:MC10154/D

MC10154ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 97 88 97 mAdcInput Current IinH 12119Output Voltage Logic 1 VOH 1415Output Voltage Logic 0 VOL 1415Threshold Voltage Logic 1 VOHA 31415Threshold Voltage Logic 0 VOLA 31415Switching Times (50Ω Load)Clock InputPropagation Delay390350650245220410245220410µAdcIinL * 0.5 0.5 0.3 µAdct12+15+t12–13–t12+4–t12–3+151343–1.060–1.060–1.890–1.890–1.080–1.080–1.0801.41.92.93.9–0.890–0.890–1.675–1.675–1.655–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910–0.910Rise Time (20 to 80%) t15+ 15 1.1 4.7 1.1 2.5 4.5 1.1 5.0Fall Time (20 to 80%) t15– 15 1.1 4.7 1.1 2.5 4.5 1.1 5.0Set InputReset Inputt11–15+t9–15+15151.41.45.09.412.314.91.52.03.04.03.56.08.511.04.89.212.014.51.52.03.04.0–0.700–0.700–1.615–1.615–1.595–1.595–1.595Counting Frequency fcount 15 125 125 150 125 MHz* Individually test each input applying VIL to input under test.5.25.21.51.55.05.01.51.55.39.812.815.55.55.5VdcVdcVdcVdcnshttp://onsemi.com341

MC10154ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 9 8 1, 16Input Current IinH 12119Output Voltage Logic 1 VOH 1415Output Voltage Logic 0 VOL 1415Threshold Voltage Logic 1 VOHA 31415Threshold Voltage Logic 0 VOLA 3141512119888(VCC)Gnd1, 161, 161, 16IinL * * 8 1, 16911119Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0VClock InputPropagation Delayt12+15+t12–13–t12+4–t12–3+151343Rise Time (20 to 80%) t15+ 15 12 15 8 1, 16Fall Time (20 to 80%) t15– 15 12 15 8 1, 16Set InputReset Inputt11–15+t9–15+1515Counting Frequency fcount 15 12 15 8 1, 16* Individually test each input applying VIL to input under test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.5119121212121195119151343151588888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com342

(Non–Inverting)The MC10158 is a quad two channel multiplexer. A common selectinput determines which data inputs are enabled. A high (H) levelenables data inputs D00, D10, D20, and D30 and a low (L) levelenables data inputs D01, D11, D21, and D31.• PD=197 mW typ/pkg (No Load)• tpd=2.5 ns typ (Data to Q)• 3.2 ns typ (Select to Q)• tr, tf=2.5 ns typ (20%–80%)SE-LECT 9D01 5D00 6D11 3D10 4LOGIC DIAGRAMVCC = PIN 16VEE = PIN 81 Q02 Q1http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10158LAWLYYWWMC10158PAWLYYWW110158AWLYYWWD21 12D20 1315 Q2A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekD31 10D30 1114 Q3TRUTH TABLESelect D0 D1QDIP PIN ASSIGNMENTQ0 1 16 VCCLLHHXXLHLHXXLHLHQ1215Q2D11314Q3D10413D20ORDERING INFORMATIOND01512D21Device Package ShippingD00611D30MC10158L CDIP–16 25 Units / RailN CVEE78109D31SELECTMC10158P PDIP–16 25 Units / RailMC10158FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6343 Publication Order Number:MC10158/D

MC10158ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 53 38 48 53 mAdcInput Current IinH 95360400225250225250µAdcIinL 5 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 1 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 1 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 1 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 1 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)PropagationDelayData InputSelect Inputt5–1–t9+1+111.32.5Rise Time (20 to 80%) t1+ 1 1.6 3.4 1.5 2.5 3.3 1.6 3.4Fall Time (20 to 80%) t1– 1 1.6 3.4 1.5 2.5 3.3 1.6 3.43.14.81.22.42.53.23.04.51.32.53.24.8nsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 16Input Current IinH 959588(VCC)GndIinL 5 5 8 16Output Voltage Logic 1 VOH 1 5 8 16Output Voltage Logic 0 VOL 1 8 16Threshold Voltage Logic 1 VOHA 1 5 8 16Threshold Voltage Logic 0 VOLA 1 5 8 16Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation DelayData InputSelect Inputt5–1–t9+1+11 6Rise Time (20 to 80%) t1+ 1 5 1 8 16Fall Time (20 to 80%) t1– 1 5 1 8 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.59118816161616http://onsemi.com344

(Inverting)The MC10159 is a quad two channel multiplexer with enable. Itincorporates common enable and common data select inputs. Theselect input determines which data inputs are enabled. A high (H) levelenables data inputs D00, D10, D20, and D30. A low (L) level enablesdata inputs D01, D11, D21, and D31. Any change on the data inputswill be reflected at the outputs while the enable is low. Input levels areinverted at the output.• PD=218 mW typ/pkg (No Load)• tpd=2.5 ns typ (Data to Q)• 3.2 ns typ (Select to Q)• tr, tf=2.5 ns typ (20%–80%)SELECT9D01 5D00 6D11 3LOGIC DIAGRAMVCC = PIN 16VEE = PIN 81 Q02 Q1http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10159LAWLYYWWMC10159PAWLYYWW110159AWLYYWWD10 4ENABLE7D21 12D20 1315 Q2A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekD31 10D30 11DIP PIN ASSIGNMENTQ0Q1D11D10D01D00ENABLEVEE12345678161514131211109VCCQ2Q3D20D21D30D31SELECT14 Q3Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.TRUTH TABLEEnable Select D0 D1 QLLLLHLLHHXXXLHXLHXXXORDERING INFORMATIONDevice Package ShippingHLHLLMC10159L CDIP–16 25 Units / RailMC10159P PDIP–16 25 Units / RailMC10159FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6345 Publication Order Number:MC10159/D

MC10159ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 58 42 53 58 mAdcInput Current IinH 95360400225250225250µAdcIinL 5 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 1 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 1 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 1 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 1 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)PropagationDelayData InputSelect InputEnable Inputt5+1–t9+1–t7+1–1111.11.51.4Rise Time (20 to 80%) t1+ 1 1.0 3.7 1.1 2.5 3.5 1.0 3.7Fall Time (20 to 80%) t1– 1 1.0 3.7 1.1 2.5 3.5 1.0 3.73.85.35.31.21.51.52.53.22.53.35.05.01.11.51.43.85.35.3nsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 16Input Current IinH 959588(VCC)GndIinL 5 5 8 16Output Voltage Logic 1 VOH 1 8 16Output Voltage Logic 0 VOL 1 5 8 16Threshold Voltage Logic 1 VOHA 1 9 6 8 16Threshold Voltage Logic 0 VOLA 1 9 6 8 16Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation DelayData InputSelect InputEnable Inputt5+1–t9+1–t7+1–11163, 12Rise Time (20 to 80%) t1+ 1 9 5 1 8 16Fall Time (20 to 80%) t1– 1 9 5 1 8 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.5971118816161616http://onsemi.com346

The MC10160 consists of nine Exclusive-OR gates in a singlepackage, internally connected to provide odd parity checking orgeneration. Output goes high when an odd number of inputs are high.Unconnected inputs are pulled to low logic levels allowing paritydetection and generation for less than 12 bits.• PD = 320 mW typ/pkg (No Load)• tpd = 5.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)345679101112131415VCC1OUTIN1IN2IN3IN4IN5VEELOGIC DIAGRAMDIP PIN ASSIGNMENT123456781615141312111092VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8VCC2IN12IN11IN10Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.IN9IN8IN7IN6http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10160L CDIP–16 25 Units / RailMC10160P PDIP–16 25 Units / RailMC10160FN PLCC–20 46 Units / Rail1161MC10160LAWLYYWWMC10160PAWLYYWW110160AWLYYWWINPUTOUTPUTSum of High Level Inputs Pin 2EvenLowOddHigh© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7347 Publication Order Number:MC10160/D

MC10160ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 86 62 78 86 mAdcInput CurrentIinH(Note 1.)34425350265220265220µAdcIinL 3 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 2 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 2 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)Propagation Delayt3+2+t3+2–t3–2–t3–2+t4+2+t4+2–t4–2–t4–2+222222221.81.81.81.81.81.81.81.8Rise Time (20 to 80%) t2+ 2 1.1 3.5 1.1 2.0 3.3 1.0 3.5Fall Time (20 to 80%) t2– 2 1.1 3.5 1.1 2.0 3.3 1.0 3.51. Pins 3, 6, 7, 11, 12, 15 are similar. Pins 4, 5, 9, 10, 13, 14 are similar.8.18.18.18.18.18.18.18.12.02.02.02.02.02.02.02.05.05.05.05.05.05.05.05.07.57.57.57.57.57.57.57.52.02.02.02.02.02.02.02.08.08.08.08.08.08.08.08.0nshttp://onsemi.com348

MC10160ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbolPower Supply Drain Current IE 8Input CurrentIinH(Note 1.)–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2PinTEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEE4,5,9,10,13,14Output Voltage Logic 1 VOH 2 3Output Voltage Logic 0 VOL 2Threshold Voltage Logic 1 VOHA 2Threshold Voltage Logic 0 VOLA 23434(VCC)Gnd8 1,16881,161,16IinL 3 3 8 1,164,5,6,7,9,10,11,12,13,14,153,4,5,6,7,9,10,11,12,13,14,154,5,6,7,9,10,11,12,13,14,153,5,6,7,9,10,11,12,13,14,158 1,168 1,163 8 1,164 8 1,16Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt3+2+t3+2–t3–2–t3–2+t4+2+t4+2–t4–2–t4–2+222222224433Rise Time (20 to 80%) t2+ 2 3 2 8 1,16Fall Time (20 to 80%) t2– 2 3 2 8 1,161. Pins 3, 6, 7, 11, 12, 15 are similar. Pins 4, 5, 9, 10, 13, 14 are similar.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.3333444422222222888888881,161,161,161,161,161,161,161,16http://onsemi.com349

The MC10161 is designed to decode a three bit input word to a oneof eight line output. The selected output will be low while all otheroutputs will be high. The enable inputs, when either or both are high,force all outputs high.The MC10161 is a true parallel decoder. No series gating is usedinternally, eliminating unequal delay times found in other decoders.This design provides the identical 4 ns delay from any address or enableinput to any output.A complete mux/demux operation on 16 bits for data distribution isillustrated in Figure 1. This system, using the MC10136 controlcounters, has the capability of incrementing, decrementing or holdingdata channels. When both S0 and S1 are low, the index counters reset,thus initializing both the mux and demux units. The four binaryoutputs of the counter are buffered by the MC10161s to sendtwisted–pair select data to the multiplexer/demultiplexer to units.• PD = 315 mW typ/pkg (No Load)• tpd = 4.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)E0 2E1 15A 7B 9C 14LOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8TRUTH TABLEENABLEINPUTS INPUTS OUTPUTS6 Q05 Q14 Q23 Q313 Q412 Q511 Q610 Q7E1 E0 C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7L L L L L L H H H H H H HL L L L H H L H H H H H HL L L H L H H L H H H H HL L L H H H H H L H H H HL L H L L H H H H L H H HL L H L H H H H H H L H HL L H H L H H H H H H L HL L H H H H H H H H H H LH X X X X H H H H H H H HX H X X X H H H H H H H Hhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekVCC1E0Q3Q2Q1Q0AVEEORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10161L CDIP–16 25 Units / RailMC10161P PDIP–16 25 Units / RailMC10161FN PLCC–20 46 Units / Rail116DIP PIN ASSIGNMENT123456781615141312111091MC10161LAWLYYWWMC10161PAWLYYWW110161AWLYYWWVCC2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.E1CQ4Q5Q6Q7B© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6350 Publication Order Number:MC10161/D

MC10161ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 84 61 76 84 mAdcInput Current IinH 14 350 220 220 µAdcOutput Voltage Logic 1 VOH 1313IinL 14 0.5 0.5 0.3 µAdc–1.060–1.060–0.890–0.890–0.960–0.960–0.810–0.810–0.890–0.890–0.700–0.700Output Voltage Logic 0 VOL 13 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 1313–1.080–1.080–0.980–0.980–0.910–0.910Threshold Voltage Logic 0 VOLA 13 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)Propagation Delayt14+13–t14–13+13131.51.5Rise Time (20 to 80%) t13+ 13 1.0 3.3 1.1 2.0 3.3 1.1 3.5Fall Time (20 to 80%) t13– 13 1.0 3.3 1.1 2.0 3.3 1.1 3.56.26.21.51.54.04.06.06.01.51.56.46.4VdcVdcnsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 2,7,9,14,15 8 1,16Input Current IinH 14 14 8 1,16Output Voltage Logic 1 VOH 1313(VCC)GndIinL 14 14 8 1,16215Output Voltage Logic 0 VOL 13 14 8 1,16Threshold Voltage Logic 1 VOHA 1313Threshold Voltage Logic 0 VOLA 13 14 8 1,16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt14+13–t14–13+1313Rise Time (20 to 80%) t13+ 13 14 13 8 1,16Fall Time (20 to 80%) t13– 13 14 13 8 1,16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.215141413138888881,161,161,161,161,161,16http://onsemi.com351

MC10161FIGURE 1 — HIGH SPEED 16-BIT MULTIPLEXER/DEMULTIPLEXERControl SelectionMC10161 MC10115MC10161 MC10115S0S1Start/StopS0S1MC10136C RA B C DS0S1MC10136C RA B C D15 14 13 12 11 10 9 8E1CBAE1CBAMC10164D0E0MC10161E1CBAE1CBA7 6 5 4 3 2 1 0MC10164D0E0MC1016115 14 13 12 11 10 9 87 6 5 4 3 2 1 0http://onsemi.com352

The MC10162 is designed to convert three lines of input data to aone–of–eight output. The selected output will be high while all otheroutputs are low. The enable inputs, when either or both are high, forceall outputs low.The MC10162 is a true parallel decoder. No series gating is usedinternally, eliminating unequal delay times found in other decoders.This device is ideally suited for demultiplexer applications. One ofthe two enable inputs is used as the data input, while the other is usedas a data enable input.A complete mux/demux operation on 16 bits for data distribution isillustrated in Figure 1 of the MC10161 data sheet.• PD = 315 ns typ/pkg (No Load)• tpd = 4.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)E0 2E1 15A 7B 9C 14INPUTSLOGIC DIAGRAMVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8TRUTH TABLEOUTPUTS6 Q05 Q14 Q23 Q313 Q412 Q511 Q610 Q7E0 E1 C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7L L L L L H L L L L L L LL L L L H L H L L L L L LL L L H L L L H L L L L LL L L H H L L L H L L L LL L H L L L L L L H L L LL L H L H L L L L L H L LL L H H L L L L L L L H LL L H H H L L L L L L L HH X X X X L L L L L L L LX H X X X L L L L L L L LVCC1E0http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekMARKINGDIAGRAMS16ORDERING INFORMATIONDevice Package ShippingMC10162L CDIP–16 25 Units / Rail116DIP PIN ASSIGNMENTQ3Q2Q1Q0AVEE123456781615141312111091MC10162LAWLYYWWMC10162PAWLYYWW110162AWLYYWWVCC2Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.E1CQ4Q5Q6Q7BMC10162P PDIP–16 25 Units / RailMC10162FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6353 Publication Order Number:MC10162/D

MC10162ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 84 61 76 84 mAdcInput Current IinH 14 350 220 220 µAdcIinL 14 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 13 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 1313–1.890–1.890–1.675–1.675–1.850–1.850–1.650–1.650–1.825–1.825–1.615–1.615Threshold Voltage Logic 1 VOHA 13 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 1313Switching Times (50Ω Load)Propagation Delayt14+13–t14–13+13131.51.5–1.655–1.6556.26.21.51.54.04.0–1.630–1.630Rise Time (20 to 80%) t13+ 13 1.0 3.3 1.1 2.0 3.3 1.1 3.5Fall Time (20 to 80%) t13– 13 1.0 3.3 1.1 2.0 3.3 1.1 3.56.06.01.51.5–1.595–1.5956.46.4VdcVdcnsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1,16Input Current IinH 14 14 8 1,16(VCC)GndIinL 14 14 8 1,16Output Voltage Logic 1 VOH 13 14 8 1,16Output Voltage Logic 0 VOL 1313215Threshold Voltage Logic 1 VOHA 13 14 8 1,16Threshold Voltage Logic 0 VOLA 1313Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt14+13+t14–13–1313Rise Time (20 to 80%) t+ 13 14 13 8 1,16Fall Time (20 to 80%) t– 13 14 13 8 1,16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.215141413138888881,161,161,161,161,161,16http://onsemi.com354

The MC10164 is a high speed, low power eight–channel dataselector which routes data present at one–of–eight inputs to the output.The data is routed according to the three bit code present on theaddress inputs. An enable input is provided for easy bit expansion.• PD = 310 mW typ/pkg (No Load)• tpd = 3.0 ns typ (Data to Output)• tr, tf = 2.0 ns typ (20%–80%)A 7B 9C 10Enable 2X0 6X1 5X2 4X3 3LOGIC DIAGRAM15 Zhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10164LAWLYYWWMC10164PAWLYYWW110164AWLYYWWX4 11X5 12X6 13X7 14TRUTH TABLEADDRESS INPUTSENABLE C B A ZL L L L X0L L L H X1L L H L X2L L H H X3L H L L X4L H L H X5L H H L X6L H H H X7H X X X LVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8VCC2ENABLEX3X2X1X0AVEEA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDIP PIN ASSIGNMENT12345678161514131211109VCC1Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.ZX7X6X5X4CBORDERING INFORMATIONDevice Package ShippingMC10164L CDIP–16 25 Units / RailMC10164P PDIP–16 25 Units / RailMC10164FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6355 Publication Order Number:MC10164/D

MC10164ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 83 60 75 83 mAdcInput Current IinH 2 425 265 265 µAdcIinL 4 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 15 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 15 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 15 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 15 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)Propagation Delayt4+15+ 15 1.5 4.9 1.5 3.0 4.7 1.6 5.0t4–15– 15 1.5 4.9 1.5 3.0 4.7 1.6 5.0t7+15+ 15 1.9 6.5 2.0 4.0 6.2 2.2 6.7t7–15– 15 1.9 6.5 2.0 4.0 6.2 2.2 6.7t2+15– 15 0.9 3.5 1.0 2.0 3.1 1.0 3.3t2–15+ 15 0.9 3.5 1.0 2.0 3.1 1.0 3.3Rise Time (20 to 80%) t+ 15 0.9 3.3 1.1 2.0 3.3 1.2 3.6Fall Time (20 to 80%) t– 15 0.9 3.3 1.1 2.0 3.3 1.2 3.6nsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1,16Input Current IinH 2 4 8 1,16(VCC)GndIinL 4 4 8 1,16Output Voltage Logic 1 VOH 15 4,9 8 1,16Output Voltage Logic 0 VOL 15 9 8 1,16Threshold Voltage Logic 1 VOHA 15 4,9 2 8 1,16Threshold Voltage Logic 0 VOLA 15 9 2 8 1,16Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+15+ 15 94 15 8 1,16t4–15– 15 94 15 8 1,16t7+15+ 15 57 15 8 1,16t7–15– 15 57 15 8 1,16t2+15– 15 7,52 15 8 1,16t2–15+ 15 7,52 15 8 1,16Rise Time (20 to 80%) t+ 15 9 4 15 8 1,16Fall Time (20 to 80%) t– 15 9 4 15 8 1,16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com356

MC10164APPLICATION INFORMATIONThe MC10164 can be used wherever data multiplexing orparallel to serial conversion is desirable. Full parallel gatingpermits equal delays through any data path. The output ofthe MC10164 incorporates a buffer gate with eight datainputs and an enable. A high level on the enable forces theoutput low. The MC10164 can be connected directly to adata bus, due to its open emitter output and output enable.Figure 1 illustrates how a 1–of–64 line multiplexer can bebuilt with eight MC10164’s wire ORed at their outputs andone MC10161 to drive the enables on each multiplexer,without speed degradation over a single MC10164 beingexperienced.FIGURE 1 — 1–OF–64 LINE MULTIPLEXEREA B CMC10164Z outEA B CMC10164Z outEA B CMC10164Z out1497MSBLSBMC10161Q7Q6Q5Q4Q3Q2Q1Q0EEA B CMC10164A B CMC10164Z outZ outThe Bit chosen is dependent on six–bitcode present on inputs 7, 9, 14 of theMC10161 and the A, B, C inputs of theMC10164.EA B CMC10164Z outEA B CMC10164Z outEA B CMC10164Z outhttp://onsemi.com357

The MC10165 is a device designed to encode eight inputs to abinary coded output. The output code is that of the highest order input.Any input of lower priority is ignored. Each output incorporates alatch allowing synchronous operation. When the clock is low theoutputs follow the inputs and latch when the clock goes high. Thisdevice is very useful for a variety of applications in checking systemstatus in control processors, peripheral controllers, and testingsystems.The input is active when high, (e.g., the three binary outputs are lowwhen input D0 is high). The Q3 output is high when any input is high.This allows direct extension into another priority encoder when morethan eight inputs are necessary. The MC10165 can also be used todevelop binary codes from random logic inputs, for addressing ROMs,RAMs, or for multiplexing data.• PD = 545 mW typ/pkg (No Load)• tpd = 4.5 ns typ (Data to Output)• tr, tf = 2.0 ns typ (20%–80%)DIP PIN ASSIGNMENThttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10165LAWLYYWWMC10165PAWLYYWW1VCC1Q1121615VCC2Q2PLCC–20FN SUFFIXCASE 77510165AWLYYWWQ0314Q3CLOCKD0D7456131211D2D5D4A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekD1VEE78Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.TRUTH TABLEDATA INPUTSOUTPUTSD0 D1 D2 D3 D4 D5 D6 D7 Q3 Q2 Q1 Q0H X X X X X X X H L L LL H X X X X X X H L L HL L H X X X X X H L H LL L L H X X X X H L H HL L L L H X X X H H L LL L L L L H X X H H L HL L L L L L H X H H H LL L L L L L L H H H H HL L L L L L L L L L L L109D3D6ORDERING INFORMATIONDevice Package ShippingMC10165L CDIP–16 25 Units / RailMC10165P PDIP–16 25 Units / RailMC10165FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7358 Publication Order Number:MC10165/D

MC10165LOGIC DIAGRAMC 4D0 5VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8D1 7D2 133 Q0D3 10D4 112 Q1D5 1215 Q2D6 9D7 614 Q3http://onsemi.com359

MC10165ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 144 105 131 144 mAdcInput Current IinH 45IinL 45Output Voltage Logic 1 VOH 231415Output Voltage Logic 0 VOL 231415Threshold Voltage Logic 1 VOHA 231415Threshold Voltage Logic 0 VOLA 231415Switching Times (50Ω Load)Propagation DelayData InputSetup TimeHold TimeClock Inputt5+14+t5–14–t7+3+t11+15+t13+2+t4–3+t4–3–t4–14+t4–14–tsetupHtsetupLtholdHtholdL141431523 (2.)3 (3.)14 (2.)14 (3.)33330.50.5–1.060–1.060–1.060–1.060–1.890–1.890–1.890–1.890–1.080–1.080–1.080–1.0802.02.02.02.02.01.51.51.51.56.06.01.01.0390350–0.890–0.890–0.890–0.890–1.675–1.675–1.675–1.675–1.655–1.655–1.655–1.6557.07.07.07.07.00.50.5–0.960–0.960–0.960–0.960–1.850–1.850–1.850–1.850–0.980–0.980–0.980–0.9803.03.03.03.03.0245220–0.810–0.810–0.810–0.810–1.650–1.650–1.650–1.650–1.630–1.630–1.630–1.6307.07.07.07.07.00.30.3–0.890–0.890–0.890–0.890–1.825–1.825–1.825–1.825–0.910–0.910–0.910–0.910Rise Time (20 to 80%) t3+ 3 1.1 3.5 1.1 2.0 3.3 1.1 3.54.54.54.54.52.02.02.02.04.04.04.04.02.02.02.02.02.01.51.51.51.5245220–0.700–0.700–0.700–0.700–1.615–1.615–1.615–1.615–1.595–1.595–1.595–1.595Fall Time (20 to 80%) t3– 3 1.1 3.5 1.1 2.0 3.3 1.1 3.51. The same limit applies for all D type input pins. To test input currents for other D inputs, individually apply proper voltage to pin under test.2. Output latched to low state prior to test.3. Output latched to high state prior to test.* To preserve reliable performance, the MC10165P (plastic packaged device only) is to be operated in ambient temperatures above 70°C onlywhen 500 lfpm blown air or equivalent heat sinking is provided.6.06.01.01.03.43.0–2.3–2.76.06.01.01.08.08.08.08.08.04.54.54.54.5µAdcµAdcVdcVdcVdcVdcnshttp://onsemi.com360

MC10165ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 45IinL 45Output Voltage Logic 1 VOH 231415Output Voltage Logic 0 VOL 231415Threshold Voltage Logic 1 VOHA 231415Threshold Voltage Logic 0 VOLA 23141545 (1.)6666Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0Propagation Delay Data Input t5+14+t5–14–t7+3+t11+15+t13+2+Clock Input t4–3+t4–3–t4–14+t4–14–Setup TimetsetupHtsetupLHold TimetholdHtholdL141431523 (2.)3 (3.)14 (2.)14 (3.)333377Rise Time (20 to 80%) t3+ 3 4 7 3 8 1, 16Fall Time (20 to 80%) t3– 3 4 7 3 8 1, 1645 (1.)44444444444444444444466665571113444466661414315233141488888888888888888888888888888(VCC)Gnd1. The same limit applies for all D type input pins. To test input currents for other D inputs, individually apply proper voltage to pin under test.2. Output latched to low state prior to test.3. Output latched to high state prior to test.* To preserve reliable performance, the MC10165P (plastic packaged device only) is to be operated in ambient temperatures above 70°C onlywhen 500 lfpm blown air or equivalent heat sinking is provided.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.4,74,74,74,7333388881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com361

MC10165APPLICATION INFORMATIONA typical application of the MC10165 is the decoding ofsystem status on a priority basis. A 64 line priority encoderis shown in the figure below. System status lines areconnected to this encoder such that, when a given conditionexists, the respective input will be at a logic high level. Thisscheme will select the one of 64 different system conditions,as represented at the encoder inputs, which has priority indetermining the next system operation to be performed. Thebinary code showing the address of the highest priority inputpresent will appear at the encoder outputs to control othersystem logic functions.64–LINE PRIORITY ENCODERLSBZ Z ZMC10164 MC10164 MC10164SystemClockHighestPriorityInputCD0D7CD0D71/2 MC10165MC10165MC10165Q0Q1Q2Q3Q0Q1Q2Q3X0. . . . . . . X7 A B CX0. . . . . . . X7 A B C X0 . . . . . . . X7 A B CCD0D7Q0Q1Q2MSBSix bit outputword yieldingnumber ofhighest prioritychannel presentat inputCD0D7MC10165Q0Q1Q2Q3CD0D7MC10165Q0Q1Q2Q3CD0D7MC10165Q0Q1Q2Q3CD0D7MC10165Q0Q1Q2Q3CD0D7MC10165Q0Q1Q2Q3LowestPriorityInputCD0D7MC10165Q0Q1Q2Q3http://onsemi.com362

The MC10166 is a high speed expandable 5–bit comparator forcomparing the magnitude of two binary words. Two outputs areprovided: A < B and A > B. A = B can be obtained by NORing the twooutputs with an additional gate. A high level on the enable functionforces both outputs low. Multiple MC10166s may be used for largerword comparisons.• PD = 440 mW typ/pkg (No Load)• tpd =Data to Output 6.0 ns typ• E to output 2.5 ns typ• tr, tf = 2.0 ns typ (20%–80%)A4 9B4 10LOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10166LAWLYYWWMC10166PAWLYYWW1A3 12B3 11A2 13B2 142 A > BPLCC–20FN SUFFIXCASE 775A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDIP PIN ASSIGNMENT10166AWLYYWWA1 6B1 7A0 5B0 4E 15InputsTRUTH TABLEOutputs3 A < BVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8E A B A < B A > BH X X L LL Word A = Word B L LL Word A > Word B L HL Word A < Word B H LVCC1A>BA

MC10166ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 117 85 106 117 mAdcInput Current IinH 5 350 220 220 µAdcOutput Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23Switching Times (50Ω Load)PropagationDelayData to OutputEnable to OutputIinL 5 0.5 0.5 0.3 µAdct9+2+t9–2–t11–2+t11+2–t7+3+t7–3–t15–3+t15+3–22223333–1.060–1.060–1.890–1.890–1.080–1.0801.01.01.01.01.01.01.01.0–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.0 3.6 1.1 2.0 3.5 1.1 3.8Fall Time (20 to 80%) t2– 2 1.0 3.6 1.1 2.0 3.5 1.1 3.88.08.08.08.08.08.03.83.81.01.01.01.01.01.01.01.06.06.06.06.06.06.02.52.57.67.67.67.67.67.63.63.61.01.01.01.01.01.01.01.0–0.700–0.700–1.615–1.615–1.595–1.5958.48.48.48.48.48.44.04.0VdcVdcVdcVdcnshttp://onsemi.com364

MC10166ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 4,7,10,11,14 8 1, 16Input Current IinH 5 5 8 1, 16Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23(VCC)GndIinL 5 5 8 1, 16545, 154, 155454Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0Propagation Delay Data to OutputEnable to Outputt9+2+t9–2–t11–2+t11+2–t7+3+t7–3–t15–3+t15+3–222233331212661010Rise Time (20 to 80%) t2+ 2 9 2 8 1, 16Fall Time (20 to 80%) t2– 2 9 2 8 1, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.151599111177151515152222333388888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com365

MC10166B24A24B23A23B22A22B21A21B20A20B19A19B18A18B17A17B16A16B15A15B4A4B3A3B2A2B1A1B0A0B4A4B3A3B2A2B1A1B0A0A < BA > BA < BA > BAPPLICATION INFORMATIONFIGURE 1 — 9–BIT MAGNITUDECOMPARATORA0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8A0 A1 A2 A3 A4B0 B1 B2 B3 B4A > BMC10166A < BA0 A1 A2 A3 A4B0 B1 B2 B3 B4A > BMC10166A < BA>B A BA < BA > BA < BA > BB4A4B3A3 A < BB2A2B1 A > BA1B0A0FIGURE 2 — 25–BIT MAGNITUDE COMPARATORA = BA < BA > BThe MC10166 compares the magnitude of two 5–bitwords. Two outputs are provided which give a highlevel for A > B and A < B. The A = B function can beobtained by wire–ORing these outputs (a low level indicatesA = B) or by NORing the outputs (a high level indicatesA = B).For longer word lengths, the MC10166 can be seriallyexpanded or cascaded. Figure 1 shows two devicesin a serial expansion for a 9–bit word length. The A >B and A < B outputs are fed to the A0 and B0 inputsrespectively of the next device. The connection for anA = B output is also shown. The worst case delay timeof serial expansion is equal to the number of comparatorstimes the data–to–output delay.For shorter delay times than possible with serialexpansion, devices can be cascaded. Figure 2 shows a25–bit cascaded comparator whose worst case delay istwo data–to–output delays. The cascaded scheme canbe extended to longer word lengths.http://onsemi.com366

The MC10168 is a Quad Latch with common clocking to all fourlatches. Separate output enabling gates are provided for each latch,allowing direct wiring to a bus. When the clock is high, outputs willfollow the D inputs. Information is latched on the negative–goingtransition of the clock.• PD = 310 mW typ/pkg (No Load)• tpd = G to Q = 2 ns typD to Q = 3 ns typC to Q = 4 ns typ• tr, tf = 2.0 ns typ (20%–80%)D0G0G1354LOGIC DIAGRAMQ0Q12 Q06 Q1http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775MARKINGDIAGRAMS161161MC10168LAWLYYWWMC10168PAWLYYWW110168AWLYYWWD1CCD27139A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDIP PIN ASSIGNMENTG2G31210Q2Q311 Q215 Q3VCC1Q0D0123161514VCC2Q3D3D314VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8G1G0Q1456131211CCG2Q2D1710G3TRUTH TABLEVEE89D2G C D Qn+1H X X LL L X QnL H L LL H H HPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.ORDERING INFORMATIONDevice Package ShippingMC10168L CDIP–16 25 Units / RailMC10168P PDIP–16 25 Units / RailMC10168FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7367 Publication Order Number:MC10168/D

MC10168ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 82 60 75 82 mAdcInput Current IinH 3,7,9,144,5,10,1213Output Voltage Logic 1 VOH 26Output Voltage Logic 0 VOL 26Threshold Voltage Logic 1 VOHA 26Threshold Voltage Logic 0 VOLA 26Switching Times (50Ω Load)Propagation DelayDataGateClock390425460245265290245265290µAdcIinL * 0.5 0.5 0.3 µAdct3+2+t5–2+t13+2+222–1.060–1.060–1.890–1.890–1.080–1.080–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630Setup Time t3+13+ 2 2.5 2.5 2.5Hold Time t13+3+ 2 1.0 1.0 1.01.01.01.0–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.0 3.6 1.1 2.0 3.5 1.1 3.8Fall Time (20 to 80%) t2– 2 1.0 3.6 1.1 2.0 3.5 1.1 3.8* Individually test each input applying VIH or VIL to input under test.5.63.25.81.01.01.03.02.04.05.43.15.61.11.01.2–0.700–0.700–1.615–1.615–1.595–1.5955.93.46.2VdcVdcVdcVdcnshttp://onsemi.com368

MC10168ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 3,7,9,144,5,10,1213Output Voltage Logic 1 VOH 26Output Voltage Logic 0 VOL 26Threshold Voltage Logic 1 VOHA 26Threshold Voltage Logic 0 VOLA 26**13888(VCC)Gnd1, 161, 161, 16IinL * * 8 1, 163, 137, 133, 54, 713131313Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation DelayDataGateClockt3+2+t5–2+t13+2+222Setup Time t3+13+ 2 8 1, 16Hold Time t13+3+ 2 8 1, 16Rise Time (20 to 80%) t2+ 2 3 2 8 1, 16Fall Time (20 to 80%) t2– 2 3 2 8 1, 16* Individually test each input applying VIH or VIL to input under test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.37351337222888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com369

The MC10170 is a 11–bit parity circuit, which is segmented into 9data bits and 2 control bits.Output A generates odd parity on 9 bits; that is, Output A goes highfor an odd number of high logic levels on the bit inputs in only 2 gatedelays.The Control Inputs can be used to expand parity to larger numbersof bits with minimal delay or can be used to generate even parity. Toexpand parity to larger words, the MC10170 can be used with theMC10160 or other MC10170’s. The MC10170 can generate both evenand odd parity.• PD = 300 mW typ/pkg (No Load)• tpd = 2.5 ns typ (Control Inputs to B Output)4.0 ns typ (Data Inputs to A Output)6.0 ns typ (Data Inputs to B Output)• tr, tf = 2.0 ns typ (20%–80%)CONTROLINPUTS13 HIGH14 LOWD0 3D1 4D2 5D3 6D4 7D5 9D6 10D7 11D8 12INPUTSLOGIC DIAGRAMOUTPUTSVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8Sum ofOdd ParityEven ParityDIInputsat High Level Output A Output BEven Low HighOdd High Low15 BEVEN PARITY2 AODD PARITYVCC1Ahttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775MARKINGDIAGRAMS16116A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekD0D1D2D3D4VEEDIP PIN ASSIGNMENT123456781615141312111091MC10170LAWLYYWWMC10170PAWLYYWW110170AWLYYWWVCC2BLOWHIGHD8D7D6D5Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.ORDERING INFORMATIONDevice Package ShippingMC10170L CDIP–16 25 Units / RailMC10170P PDIP–16 25 Units / RailMC10170FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7370 Publication Order Number:MC10170/D

MC10170ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 78 57 71 78 mAdcInput Current IinH 35Output Voltage Logic 1 VOH 215Output Voltage Logic 0 VOL 215Threshold Voltage Logic 1 VOHA 215Threshold Voltage Logic 0 VOLA 215Switching Times (50Ω Load)Propagation Delay350350200220220220µAdcIinL 3 0.5 0.5 0.3 µAdct13+15+t14–15–t3+2–t3–15+1515215–1.060–1.060–1.890–1.890–1.080–1.0801.51.52.04.0–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.5 4.3 1.5 2.0 3.9 1.5 4.3Fall Time (20 to 80%) t2– 2 1.5 4.3 1.5 2.0 3.9 1.5 4.34.24.26.69.51.51.52.04.02.52.54.06.04.04.06.08.81.51.52.04.0–0.700–0.700–1.615–1.615–1.595–1.5954.44.46.69.5VdcVdcVdcVdcnshttp://onsemi.com371

MC10170ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 1, 16Input Current IinH 35Output Voltage Logic 1 VOH 215Output Voltage Logic 0 VOL 215Threshold Voltage Logic 1 VOHA 215Threshold Voltage Logic 0 VOLA 2153588(VCC)Gnd1, 161, 16IinL 3 3 8 1, 163, 4, 5144, 513, 14Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0Propagation Delayt13+15+t14–15–t3+2–t3–15+1515215Rise Time (20 to 80%) t2+ 2 3 2 8 1, 16Fall Time (20 to 80%) t2– 2 3 2 8 1, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.51313143351315152158888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com372

The MC10171 is a binary coded 2 line to dual 4 line decoder withselected outputs low. With either E0 or E1 high, the correspondingselected 4 outputs are high. The common enable E, when high, forcesall outputs high.• PD = 325 mW typ/pkg (No Load)• tpd = 4.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)E0 14A 9LOGIC DIAGRAM10 Q0 311 Q0 212 Q0 113 Q0 0http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10171LAWLYYWWMC10171PAWLYYWW1B 73 Q1 34 Q1 2PLCC–20FN SUFFIXCASE 77510171AWLYYWWE 15E1 25 Q1 16 Q1 0A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekVCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8TRUTH TABLEENABLE INPUTS INPUTS OUTPUTSE E0 E1 A B Q10 Q11 Q12 Q13 Q00 Q01 Q02 Q03L L L L L L H H H L H H HL L L L H H L H H H L H HL L L H L H H L H H H L HL L L H H H H H L H H H LL L H L L H H H H L H H HL H L L L L H H H H H H HH X X X X H H H H H H H HVCC1E1Q13Q12Q11Q10BVEEDIP PIN ASSIGNMENT12345678161514131211109VCC2EE0Q00Q01Q02Q03Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.AORDERING INFORMATIONDevice Package ShippingMC10171L CDIP–16 25 Units / RailMC10171P PDIP–16 25 Units / RailMC10171FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6373 Publication Order Number:MC10171/D

MC10171ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 85 65 77 85 mAdcInput Current IinH 14 350 220 220 µAdcOutput Voltage Logic 1 VOH 613IinL 14 0.5 0.5 0.3 µAdc–1.060–1.060–0.890–0.890–0.960–0.960–0.810–0.810–0.890–0.890–0.700–0.700Output Voltage Logic 0 VOL 13 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 613Threshold Voltage Logic 0 VOLA 613Switching Times (50Ω Load)Propagation Delayt7+6+t7–6–t7+13+t7–13–Rise Time (20 to 80%) t6+t13+Fall Time (20 to 80%) t6–t13–661313613613–1.080–1.0801.51.51.51.51.01.01.01.0–1.655–1.6556.26.26.26.23.33.33.33.3–0.980–0.9801.51.51.51.51.11.11.11.14.04.04.04.02.02.02.02.0–1.630–1.6306.06.06.06.03.33.33.33.3–0.910–0.9101.51.51.51.51.11.11.11.1–1.595–1.5956.46.46.46.43.43.43.43.4VdcVdcVdcnshttp://onsemi.com374

MC10171ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 2,7,9,14,15 8 1, 16Input Current IinH 14 14 8 1, 16Output Voltage Logic 1 VOH 613(VCC)GndIinL 14 14 8 1, 161515Output Voltage Logic 0 VOL 13 2,7,9,14,15 8 1, 16Threshold Voltage Logic 1 VOHA 613Threshold Voltage Logic 0 VOLA 6132,9,14,152,7,14,15Switching Times (50Ω Load) +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt7+6+t7–6–t7+13+t7–13–Rise Time (20 to 80%) t6+t13+Fall Time (20 to 80%) t6–t13–6613136136132,9,14,152,9,14,152,9,14,152,9,14,15Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.15157777777779661313613613888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com375

The MC10172 is a binary-coded 2 line to dual 4 line decoder withselected outputs high. With either E0 or E1 low, the correspondingselected 4 outputs are low. The common enable E, when high, forcesall outputs low.• PD = 325 mW typ/pkg (No Load)• tpd = 4.0 ns typ• tr, tf = 2.0 ns typ (20%–80%)E0 14VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8A 9B 7E 15LOGIC DIAGRAM10 Q0 311 Q0 212 Q0 113 Q0 03 Q1 34 Q1 25 Q1 1http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161161MARKINGDIAGRAMSMC10172LAWLYYWWMC10172PAWLYYWW110172AWLYYWWE1 2DIP PIN ASSIGNMENTVCC1 1 16 VCC26 Q1 0A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekE1215EQ13314E0ORDERING INFORMATIONQ12413Q00Device Package ShippingQ11512Q01MC10172L CDIP–16 25 Units / RailQ10611Q02MC10172P PDIP–16 25 Units / RailBVEE78109Q03AMC10172FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.TRUTH TABLEE E1 E0 A B Q10 Q11 Q12 Q13 Q00 Q01 Q02 Q03L H H L L H L L L H L L LL H H L H L H L L L H L LL H H H L L L H L L L H LL H H H H L L L H L L L HL L H L L L L L L H L L LL H L L L H L L L L L L LH X X X X L L L L L L L L© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6376 Publication Order Number:MC10172/D

MC10172ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 85 65 77 85 mAdcInput Current IinH 14 350 220 220 µAdcOutput Voltage Logic 1 VOH 613IinL 14 0.5 0.5 0.3 µAdc–1.060–1.060–0.890–0.890–0.960–0.960–0.810–0.810–0.890–0.890–0.700–0.700Output Voltage Logic 0 VOL 13 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 613Threshold Voltage Logic 0 VOLA 613Switching Times (50Ω Load)Propagation Delayt7+6–t7–6+t7+13–t7–13+Rise Time (20 to 80%) t6+t13+Fall Time (20 to 80%) t6–t13–661313613613–1.080–1.0801.51.51.51.51.01.01.01.0–1.655–1.6556.26.26.26.23.33.33.33.3–0.980–0.9801.51.51.51.51.11.11.11.14.04.04.04.02.02.02.02.0–1.630–1.6306.06.06.06.03.33.33.33.3–0.910–0.9101.51.51.51.51.11.11.11.1–1.595–1.5956.46.46.46.43.43.43.43.4VdcVdcVdcnshttp://onsemi.com377

MC10172ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 14 14 8 1, 16Output Voltage Logic 1 VOH 613(VCC)GndIinL 14 14 8 1, 16214Output Voltage Logic 0 VOL 13 15 2,7,9,14 8 1, 16Threshold Voltage Logic 1 VOHA 613Threshold Voltage Logic 0 VOLA 6132,9,142,7,14Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt7+6–t7–6+t7+13–t7–13+Rise Time (20 to 80%) t6+t13+Fall Time (20 to 80%) t6–t13–661313613613221414214214Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.9, 149, 142, 92,99, 142, 99, 142, 92147777777779661313613613888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com378

The MC10173 is a quad two channel multiplexer with latch. Itincorporates common clock and common data select inputs. The selectinput determines which data input is enabled. A high (H) level enablesdata inputs D00, D10, D20, and D30 and a low (L) level enables datainputs D01, D11, D21, D31. Any change on the data input will bereflected at the outputs while the clock is low. The outputs are latchedon the positive transition of the clock. While the clock is in the highstate, a change in the information present at the data inputs will notaffect the output information.• PD = 275 mW typ/pkg (No Load)• tpd = 2.5 ns typ• tr, tf = 2.0 ns typ (20%–80%)SELECT 9LOGIC DIAGRAMhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10173LAWLYYWWMC10173PAWLYYWW1D00 6D01 51 Q0PLCC–20FN SUFFIXCASE 77510173AWLYYWWD10 4D11 32 Q1A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDIP PIN ASSIGNMENTD20 13D21 12D30 11D31 10CLOCK 7TRUTH TABLESELECT CLOCK Q0n+1H L D00L L D01X H Q0n15 Q214 Q3VCC = PIN 16VEE = PIN 8Q0Q1D11D10D01D00CLOCKVEE12345678VCCQ2Q3D20D21D30D31SELECTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.ORDERING INFORMATIONDevice Package ShippingMC10173L CDIP–16 25 Units / RailMC10173P PDIP–16 25 Units / RailMC10173FN PLCC–20 46 Units / Rail161514131211109© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6379 Publication Order Number:MC10173/D

MC10173ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 73 66 73 mAdcInput Current IinH 5679Output Voltage Logic 1 VOH 12Output Voltage Logic 0 VOL 12Threshold Voltage Logic 1 VOHA 12Threshold Voltage Logic 0 VOLA 12Switching Times (50Ω Load)PropagationDelaySetup TImeHold TImeData InputClock InputSelect InputData InputSelect InputData InputSelect Input470470400400295295250250295295250250µAdcIinL All 0.5 0.5 0.3 µAdct6+1+t6–1–t5+1+t5–1–t7–1+t7–1–t9+1+t9+1–t9–1+t9–1–tsetuptsetuptholdthold11111111111111–1.060–1.060–1.890–1.890–1.080–1.0800.80.80.80.81.61.61.11.11.11.12.03.02.51.5–0.890–0.890–1.675–1.675–1.655–1.6553.73.73.73.77.27.2–0.960–0.960–1.850–1.850–0.980–0.9801.01.01.01.01.61.62.52.52.52.54.54.5–0.810–0.810–1.650–1.650–1.630–1.6303.53.53.53.56.86.8–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t+ 1 1.2 4.0 1.5 2.0 3.5 1.4 4.0Fall Time (20 to 80%) t– 1 1.2 4.0 1.5 2.0 3.5 1.4 4.0*VILmin applied to each input pin, one at a time.6.26.26.26.21.31.31.31.32.03.02.51.53.53.53.53.51.52.50.0–0.55.75.75.75.71.11.11.11.11.41.41.21.21.21.22.03.02.51.5–0.700–0.700–1.615–1.615–1.595–1.5955.35.35.35.36.86.86.76.76.76.7VdcVdcVdcVdcnshttp://onsemi.com380

MC10173ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 16Input Current 5679Output Voltage Logic 1 VOH 12Output Voltage Logic 0 VOL 12Threshold Voltage Logic 1 VOHA 12Threshold Voltage Logic 0 VOLA 1256798888(VCC)GndIinL All * 8 166, 95779 779 779 77Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delay Data Input t6+1+t6–1–t5+1+t5–1–Clock Input t7–1+t7–1–Select Input t9+1+t9+1–t9–1+t9–1–Setup TImeHold TImeData InputSelect InputData InputSelect Inputtsetuptsetuptholdthold111111111199655611 611 6Rise Time (20 to 80%) t+ 1 5 7 1 8 16Fall Time (20 to 80%) t– 1 7 1 8 16*VILmin applied to each input pin, one at a time.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.777777776566555, 75, 799995, 77, 95, 77, 9651111111111111188888888888888888888881616161616161616161616161616161616161616161616161616http://onsemi.com381

The MC10174 is a high speed dual channel multiplexer with outputenable capability. The select inputs determine one of four active datainputs for each multiplexer. An output enable forces both outputs lowwhen in the high state.• PD = 305 mW typ/pkg (No Load)• tpd = 3.5 ns typ (Dta to output)• tr, tf = 2.0 ns typ (20%–80%)D00 3D01 5D02 4D03 6LOGIC DIAGRAM2 Q0http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10174LAWLYYWWMC10174PAWLYYWW1A 7B 9ENABLE 14D10 13VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8PLCC–20FN SUFFIXCASE 775A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week10174AWLYYWWD11 11D12 12D13 1015 Q1DIP PIN ASSIGNMENTVCC1Q0DO0123161514VCC2Q1ENABLETRUTH TABLEENABLE ADDRESS INPUTS OUTPUTSE B A Q0 Q1H X X L LL L L D00 D10L L H D01 D11L H L D02 D12L H H D03 D13DO2DO1DO3AVEE45678131211109D10D12D11D13Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.BORDERING INFORMATIONDevice Package ShippingMC10174L CDIP–16 25 Units / RailMC10174P PDIP–16 25 Units / RailMC10174FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6382 Publication Order Number:MC10174/D

MC10174ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 80 58 73 80 mAdcInput Current IinH 414350525220330220330µAdcIinL 4 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 15 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 15 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 15 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 15 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)Propagation Delayt13+15+t13–15–t7+15–t7–15+t14+15–t14–15+1515151515151.41.41.91.91.01.0Rise Time (20 to 80%) t+ 15 1.0 3.4 1.1 2.0 3.3 1.1 3.6Fall Time (20 to 80%) t– 15 1.0 3.4 1.1 2.0 3.3 1.1 3.65.05.06.66.63.33.31.51.52.02.01.01.03.53.55.05.02.02.04.74.76.26.23.13.11.41.42.12.10.90.95.05.06.66.63.43.4nsELECTRICAL CHARACTERISTICS (continued)Each MECL 10,000 series circuit has been de-signed to meet the dc specifications shown in theTEST VOLTAGE VALUES (Volts)test table, after thermal equilibrium has been es-tablished. The circuit is in a test socket or mounted@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEEon a printed circuit board and transverse air flowgreater than 500 linear fpm is maintained. Outputsuts–30°C –0.890 –1.890 –1.205 –1.500 –5.2are terminated through a 50–ohm resistor to –2.0volts. Test procedures are shown for only one +25°C –0.810 –1.850 –1.105 –1.475 –5.2gate. The other gates are tested in the same manner.+85°C –0.700 –1.825 –1.035 –1.440 –5.2CharacteristicSymbolPin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 41441488(VCC)Gnd1, 161, 16IinL 4 4 8 1, 16Output Voltage Logic 1 VOH 15 13 8 1, 16Output Voltage Logic 0 VOL 15 14 8 1, 16Threshold Voltage Logic 1 VOHA 15 13 8 1, 16Threshold Voltage Logic 0 VOLA 15 14 8 1, 16Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt13+15+ 1513 15 8 1, 16t13–15– 1513 15 8 1, 16t7+15– 15 117 15 8 1, 16t7–15+ 15 117 15 8 1, 16t14+15– 15 1314 15 8 1, 16t14–15+ 15 1314 15 8 1, 16Rise Time (20 to 80%) t+ 15 13 14 15 8 1, 16Fall Time (20 to 80%) t– 15 13 14 15 8 1, 16http://onsemi.com383

The MC10175 is a high speed, low power quint latch. It features fiveD type latches with common reset and a common two–input clock.Data is transferred on the negative edge of the clock and latched on thepositive edge. The two clock inputs are “OR”ed together.Any change on the data input will be reflected at the outputs whilethe clock is low. The outputs are latched on the positive transition ofthe clock. While the clock is in the high state, a change in theinformation present at the data inputs will not affect the outputinformation. The reset input is enabled only when the clock is in thehigh state.• PD = 400 mW typ/pkg (No Load)• tpd = 2.5 ns typ (Data to Output)• tr, tf = 2.0 ns typ (20%–80%)D0LOGIC DIAGRAM10 D Q 14 Q0C Rhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10175LAWLYYWWMC10175PAWLYYWW1D112DCRQ15Q1PLCC–20FN SUFFIXCASE 77510175AWLYYWWD2 13D Q 2CRQ2A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekD3D4C0C1RESET956711D QC RDCRTRUTH TABLED C0 C1 Reset Qn+1L L L X LH L L X HX H X L Q nX X H L Q nX H X H LX X H H LQ34Q3Q4VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8VCC1Q2DIP PIN ASSIGNMENTQ3Q4D4C0C1VEE12345678VCC2Q1Q0ORDERING INFORMATIONDevice Package ShippingMC10175L CDIP–16 25 Units / Rail161514131211109D2D1RESETPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.D0D3MC10175P PDIP–16 25 Units / RailMC10175FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6384 Publication Order Number:MC10175/D

MC10175ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 107 78 97 107 mAdcInput Current IinH 671011Output Voltage Logic 1 VOH 1415Output Voltage Logic 0 VOL 1415Threshold Voltage Logic 1 VOHA 1415Threshold Voltage Logic 0 VOLA 1415Switching Times (50Ω Load)Setup TImeHold TimeData InputClock InputReset Input4604604601000290290290650290290290650µAdcIinL All 0.5 0.5 0.3 µAdct10+14+t10–14–t6–14+t6–14–t11+4–t11+14–tsetupthold141414144141414–1.060–1.060–1.890–1.890–1.080–1.0801.01.01.01.01.01.02.51.5–0.890–0.890–1.675–1.675–1.655–1.6553.63.6–0.960–0.960–1.850–1.850–0.980–0.9801.01.0–0.810–0.810–1.650–1.650–1.630–1.6303.53.5–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t+ 14 1.0 3.6 1.1 3.5 1.1 3.7Fall Time (20 to 80%) t– 14 1.0 3.6 1.1 3.5 1.1 3.71. Individually test each input; apply VILmin to pin under test.2. Output latched to high logic state prior to test.4.74.74.04.01.01.01.01.02.51.54.34.33.93.91.01.01.01.01.01.02.51.5–0.700–0.700–1.615–1.615–1.595–1.5953.63.64.44.44.24.2VdcVdcVdcVdcnshttp://onsemi.com385

MC10175ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 671011Output Voltage Logic 1 VOH 1415Output Voltage Logic 0 VOL 1415Threshold Voltage Logic 1 VOHA 1415Threshold Voltage Logic 0 VOLA 14156710118888(VCC)Gnd1, 161, 161, 161, 16IinL All Note 1. 8 1, 161012Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 VSetup TImeHold TimeData InputClock InputReset Inputt10+14+t10–14–t6–14+t6–14–t11+4–t11+14–tsetupthold141414144141414510Rise Time (20 to 80%) t+ 14 6, 7 10 14 8 1, 16Fall Time (20 to 80%) t– 14 6, 7 10 14 8 1, 161. Individually test each input; apply VILmin to pin under test.2. Output latched to high logic state prior to test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.666, 106, 1266666, 76, 77766771012101010, 610, 67, 117, 116, 106, 101012141414144 (2.)14 (2.)141488888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com386

The MC10176 contains six high-speed, master slave type “D”flip-flops. Clocking is common to all six flip-flops. Data is enteredinto the master when the clock is low. Master to slave data transfertakes place on the positive-going Clock transition. Thus, outputs maychange only on a positive-going Clock transition. A change in theinformation present at the data (D) input will not affect the outputinformation any other time due to the master-slave construction of thisdevice.• PD = 460 mW typ/pkg (No Load)• ftoggle = 150 MHz (typ)• tr, tf = 2.0 ns typ (20%–80%)D05LOGIC DIAGRAM2Q0http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10176LAWLYYWWMC10176PAWLYYWW1D163 Q1PLCC–20FN SUFFIXCASE 77510176AWLYYWWD274 Q2A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekD31013 Q3DIP PIN ASSIGNMENTVCC1 1 16 VCC2Q0215Q5D4 11D5 12CLOCK 914 Q415 Q5VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8Q1Q2D0D1D2345671413121110Q4Q3D5D4D3VEE89CLOCKCLOCKED TRUTH TABLEC D Qn+1L X QnH* L LH* H H*A clock H is a clock transitionfrom a low to a high state.Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.ORDERING INFORMATIONDevice Package ShippingMC10176L CDIP–16 25 Units / RailMC10176P PDIP–16 25 Units / RailMC10176FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6387 Publication Order Number:MC10176/D

MC10176ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 121 88 110 121 mAdcInput Current IinH 59IinL 59Output Voltage Logic 1 VOH 215Output Voltage Logic 0 VOL 215Threshold Voltage Logic 1 VOHA 215Threshold Voltage Logic 0 VOLA 215Switching Times (50Ω Load)Clock InputPropagation Delayt9+2+t9+2–220.50.5–1.060–1.060–1.890–1.890–1.080–1.0801.61.6350495–0.890–0.890–1.675–1.675–1.655–1.6550.50.5–0.960–0.960–1.850–1.850–0.980–0.980220310–0.810–0.810–1.650–1.650–1.630–1.6300.30.3–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.0 4.1 1.1 4.0 1.1 4.4Fall Time (20 to 80%) t2– 2 1.0 4.1 1.1 4.0 1.1 4.4220310–0.700–0.700–1.615–1.615–1.595–1.595Setup Time tsetup 2 2.5 2.5 2.5 nsHold Time thold 2 1.5 1.5 1.5 nsToggle Frequency (Max) ftog 2 125 125 150 125 MHz4.64.61.61.64.54.51.61.65.05.0µAdcµAdcVdcVdcVdcVdcnsOutput level to be measured after a clock pulse has been applied to the C Input (Pin 9)VIHmaxVILminhttp://onsemi.com388

MC10176ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 59IinL 59Output Voltage Logic 1 VOH 215Output Voltage Logic 0 VOL 215Threshold Voltage Logic 1 VOHA 215Threshold Voltage Logic 0 VOLA 2155951259888888(VCC)GndSwitching Times (50Ω Load) +1.11Vdc +0.31V Pulse In Pulse Out –3.2 V +2.0 VClock InputPropagation Delayt9+2+t9+2–22Rise Time (20 to 80%) t2+ 2 5, 9 2 8 1, 16Fall Time (20 to 80%) t2– 2 5, 9 2 8 1, 16Setup Time tsetup 2 5, 9 2 8 1, 16Hold Time thold 2 5, 9 2 8 1, 16Toggle Frequency (Max) ftog 2 8 1, 165125125, 95, 951222888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16Output level to be measured after a clock pulse has been applied to the C Input (Pin 9)VIHmaxVILminEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com389

The MC10178 is a four–bit counter capable of divide–by–two,divide–by–four, divide–by–eight or a divide–by–sixteen function.Clock inputs trigger on the positive going edge of the clock pulse.Set and Reset inputs override the clock, allowing asynchronous “set”or “clear.” Individual Set and common Reset inputs are provided, aswell as complementary outputs for the first and fourth bits. Trueoutputs are available at all bits.• PD = 370 mW typ/pkg (No Load)• ftoggle=150 MHz (typ)• tr, tf = 2.7 ns typ (20%–80%)LOGIC DIAGRAMV IHV IL same effect.MC10178FN PLCC–20 46 Units / Rail** Clock transition from V IL to V IH may be applied to C 1 or C 2 or both forMC10178P PDIP–16 25 Units / Railhttp://onsemi.comMARKINGDIAGRAMS16S0 Q0 S1 Q1 S2 Q2 S3 Q3CDIP–16L SUFFIXMC10178LCASE 620AWLYYWW111 15 7 13 64 5216PDIP–16MC10178PP SUFFIXAWLYYWWCASE 64812 D1SQ’D1SQ’D1SQ’D1SQ1Clock 1 C1 Q’C1 Q’C1 Q’C1 Q’110Clock 2 C2 QQQPLCC–2010178R Q RRRQFN SUFFIXCASE 775 AWLYYWW9Reset143A = Assembly LocationQ0Q3VCC1 = PIN 1WL = Wafer LotVCC2 = PIN 16YY = YearVEE = PIN 8WW = Work WeekTRUTH TABLEDIP PIN ASSIGNMENTINPUTSOUTPUTSR S0 S1 S2 S3 C1 C2 Q0 Q1 Q2 Q3VCC1 1 16 VCC2H L L L L X X L L L LQ3 2 15 Q0L H H H H X X H H H HL L L L L H X No CountQ3 3 14 Q0L L L L L X H No CountQ2 4 13 Q1L L L L L ** L L L LL L L L L ** H L L LS3 5 12 CLOCK 1L L L L L ** L H L LS2 6 11 S0L L L L L ** H H L LL L L L L ** L L H LS1 7 10 CLOCK 2L L L L L ** H L H LVEE 8 9 RESETL L L L L ** L H H LL L L L L ** H H H LPin assignment is for Dual–in–Line Package.L L L L L ** L L L H For PLCC pin assignment, see the Pin Conversion TablesL L L L L ** H L L Hon page 18.L L L L L ** L H L HL L L L L ** H H L HL L L L L ** L L H HORDERING INFORMATIONL L L L L ** H L H HL L L L L ** L H H HDevice Package ShippingL L L L L ** H H H H MC10178L CDIP–16 25 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6390 Publication Order Number:MC10178/D

MC10178ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 97 88 97 mAdcInput Current IinH 12119Output Voltage Logic 1 VOH 1415Output Voltage Logic 0 VOL 1415Threshold Voltage Logic 1 VOHA 31415Threshold Voltage Logic 0 VOLA 31415Switching Times (50Ω Load)PropagationDelayClock Input390350650245220410245220410µAdcIinL * 0.5 0.5 0.3 µAdct12+15+t12–13–t12+4–t12–3+151343–1.060–1.060–1.890–1.890–1.080–1.080–1.0801.41.92.93.9–0.890–0.890–1.675–1.675–1.655–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910–0.910Rise Time (20 to 80%) t15+ 15 1.1 4.7 1.1 2.5 4.5 1.1 5.0Fall Time (20 to 80%) t15– 15 1.1 4.7 1.1 2.5 4.5 1.1 5.0Set InputReset Inputt11–15+t9–15+15151.41.45.09.412.314.91.52.03.04.03.56.08.511.04.89.212.014.51.52.03.04.0–0.700–0.700–1.615–1.615–1.595–1.595–1.595Counting Frequency fcount 15 125 125 150 125 MHz* Individually test each input applying VIL to input under test.5.25.21.51.55.05.01.51.55.39.812.815.55.55.5VdcVdcVdcVdcnshttp://onsemi.com391

MC10178ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 9 8 1, 16Input Current IinH 12119Output Voltage Logic 1 VOH 1415Output Voltage Logic 0 VOL 1415Threshold Voltage Logic 1 VOHA 31415Threshold Voltage Logic 0 VOLA 3141512119888(VCC)Gnd1, 161, 161, 16IinL * * 8 1, 16911119Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delay Data Input t12+15+t12–13–t12+4–t12–3+151343Rise Time (20 to 80%) t+ 15 12 15 8 1, 16Fall Time (20 to 80%) t– 15 12 15 8 1, 16Set InputReset Inputt11–15+t9–15+1515Counting Frequency fcount 15 12 15 8 1, 16* Individually test each input applying VIL to input under test.Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.5119121212121195119151343151588888888888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com392

The MC10181 is a high–speed arithmetic logic unit capable ofperforming 16 logic operations and 16 arithmetic operations on twofour–bit words. Full internal carry is incorporated for ripple throughoperation.Arithmetic logic operations are selected by applying the appropriatebinary word to the select inputs (S0 through S3) as indicated in thetables of arithmetic/logic functions. Group carry propagate (PG) andcarry generate (GG) are provided to allow fast operations on very longwords using a second order look ahead. The internal carry is enabledby applying a low level voltage to the mode control input (M).• PD = 600 mW typ/pkg (No Load)• tpd (typ): A1 to F = 6.5 ns• Cn to Cn + 4 = 3.1 ns• A1 to PG = 5.0 ns• A1 to GG = 4.5 ns• A1 to Cn + 4 = 5.0131517142120181916111092223LOGIC DIAGRAMS0 S1 S2 S3A0 F0B0F1A1B1 F2A2F3B2A3 GGB3PGCnM Cn+4VCC1 = PIN 1VCC2 = PIN 24VEE = PIN 12Function SelectLogic FunctionsArithmetic OperationM is High C = D.C. M is Low Cn is lowS3 S2 S1 S0FFLLLLLLLLHHHHHHHHLLLLHHHHLLLLHHHHLLHHLLHHLLHHLLHHLHLHLHLHLHLHLHLHF = AF = A + BF = A + BF = Logical “1”F = A • BF = BF = A BF = A + BF = A • BF = A BF = BF = A + BF = Logical “0”F = A • BF = A • BF = A2376485F = AF = A plus (A • B)F = A plus (A • B)F = A times 2F = (A + B) plus 0F = (A + B) plus (A • B)F = A plus BF = A plus (A + B)F = (A + B) plus 0F = A minus B minus 1F = (A + B) plus (A • B)F = A plus (A + B)F = minus 1 (two’s complement)F = (A • B) minus 1F = (A • B) minus 1F = A minus 1VCC1F0http://onsemi.com24A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekF1GGCN + 4F3F2PGB3A3B2VEECDIP–24L SUFFIXCASE 623ORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC10181L CDIP–24 15 Units / Rail1PIN ASSIGNMENT123456789101112242322212019181716151413MC10181LAWLYYWWVCC2MCNA0B0B1A1S1A2S2S0S3© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 7393 Publication Order Number:MC10181/D

MC10181S3 13S2 15S1 17POSITIVE LOGIC DIAGRAMS0 142 F0B0 20A0 213 F1B1 19A1 187 F2B2 11A2 166 F3B3 98 P GA3 104 G G5 C n+4C n 22M 23http://onsemi.com394

MC10181ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 12 159 145 159 mAdcInput Current IinH 910111314151617181920212223Input Leakage Current IinL 9101113141516171819202122230.50.50.50.50.50.50.50.50.50.50.50.50.50.5Output Voltage Logic 1 VOH * –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL * –2.000 –1.675 –1.990 –1.650 –1.920 –1.615 VdcThreshold Voltage Logic 1 VOHA * –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA * –1.655 –1.630 –1.595 Vdc* Test all input–output combinations according to Function Table.** For threshold level test, apply threshold input level to only one input pin at a time.3903503903204254253504253503903903504603200.50.50.50.50.50.50.50.50.50.50.50.50.50.52452202452002652652202652202452452202902000.30.30.30.30.30.30.30.30.30.30.30.30.30.3245220245200265265220265220245245220290200µAdcµAdchttp://onsemi.com395

MC10181ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 12 12 1, 24Input Current IinH 910111314151617181920212223Input Leakage Current IinL 910111314151617181920212223910111314151617181920212223Output Voltage Logic 1 VOH * * * 12 1, 24Output Voltage Logic 0 VOL * * * 12 1, 24Threshold Voltage Logic 1 VOHA * ** ** 12 1, 24Threshold Voltage Logic 0 VOLA * ** ** 12 1, 24* Test all input–output combinations according to Function Table.** For threshold level test, apply threshold input level to only one input pin at a time.91011131415161718192021222312121212121212121212121212121212121212121212121212121212(VCC)GndEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.1, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 241, 24http://onsemi.com396

MC10181AC Switching Characteristics–30°C * +25°C +85°C *Characteristic Symbol Input Output Conditions† Min Max Min Typ Max Min Max UnitPropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall TimePropagation DelayRise Time, Fall Timet++,t– –t+,t–t++,t+–t–+,t– –t+,t–t++,t+–t–+,t– –t+,t–t++,t– –t+,t–t++,t– –t+,t–t+–,t–+t+,t–t++,t–+t+,t–t++,t– –t+,t–t++,t– –t+,t–t+–,t–+t+,t–t++,t+–t+,t–t+–,t–+t+,t–t–+,t+–t+,t–t+–,t–+t+,t–t+–,t–+t+,t–CnCnCnCnCnA1A1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1MMS1S1S1S1S1S1S1S1Cn+4Cn+4F1F1F1F1F1F1PGPGGGGGCn+4Cn+4F1F1PGPGGGGGCn+4Cn+4F1F1F1F1PGPGCn+4Cn+4GGGG† Logic high level (+1.11 Vdc) applied to pins listed. All otherinput pins are left floating or tied to +0.31 Vdc.VCC1 = VCC2 = +2.0 Vdc, VEE = –3.2 VdcA0,A1,A2,A3A0,A1,A2,A3A0A0A0———S0,S3S0,S3A0,A2,A3,CnA0,A2,A3,CnA0,A2,A3,CnA0,A2,A3,CnS3,CnS3,CnS0,A1S0,A1S3,CnS3,CnS3,CnS3,Cn——A1,B1A1,B1A3,B3A3,B3A3,B3A3,B3A3,B3A3,B31.01.01.71.71.32.62.61.31.60.81.11.21.71.02.71.21.61.01.71.41.80.92.41.12.51.01.70.81.60.91.50.85.13.27.27.25.310.410.45.47.03.77.45.17.33.111.35.37.73.68.25.28.23.110.35.110.75.48.35.19.35.39.66.2* L Suffix Only1.11.02.02.01.53.03.01.52.01.12.01.52.01.03.01.52.01.12.01.52.01.03.01.53.01.52.01.12.01.12.00.83.12.04.54.53.06.56.53.05.02.04.54.05.02.08.03.56.02.06.03.06.02.06.54.06.53.06.03.06.03.06.03.05.03.07.07.05.010105.06.53.57.05.07.03.0115.07.53.58.05.08.03.0105.0105.08.05.09.05.09.06.01.11.02.02.01.53.03.01.52.01.11.31.22.01.03.01.52.01.12.01.22.01.03.01.53.01.52.01.12.01.01.90.85.43.27.57.55.310.810.85.37.03.87.75.37.83.211.95.38.03.98.65.48.73.210.85.310.85.48.45.29.95.29.76.5nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnshttp://onsemi.com397

The MC10186 contains six high–speed, master slave type “D”flip–flops. Clocking is common to all six flip–flops. Data is enteredinto the master when the clock is low. Master to slave data transfertakes place on the positive–going Clock transition. Thus, outputs maychange only on a positive–going Clock transition. A change in theinformation present at the data (D) input will not affect the outputinformation any other time due to the master–slave construction of thisdevice. A COMMON RESET IS INCLUDED IN THIS CIRCUIT.RESET ONLY FUNCTIONS WHEN CLOCK IS LOW.• PD = 460 mW typ/pkg (No Load)• ftoggle = 150 MHz (typ)• tr, tf = 2.0 ns typ (20%–80%)D05LOGIC DIAGRAM2Q0http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10186LAWLYYWWMC10186PAWLYYWW1D163 Q1PLCC–20FN SUFFIXCASE 77510186AWLYYWWD274 Q2A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDIP PIN ASSIGNMENTD31013 Q3RESET116VCCQ0215Q5D41114 Q4Q1314Q4Q2413Q3CLOCK 9RESET 1D5 1215 Q5VCC = PIN 16VEE = PIN 8D0D1D2VEE56781211109D5D4D3CLOCKCLOCKED TRUTH TABLER C D Qn + 1L L X QnL H* L LL H* H HH L X L*A clock H is a clock transitionfrom a low to a high state.Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.ORDERING INFORMATIONDevice Package ShippingMC10186L CDIP–16 25 Units / RailMC10186P PDIP–16 25 Units / RailMC10186FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6398 Publication Order Number:MC10186/D

MC10186ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 121 88 110 121 mAdcInput Current IinH 591Output Voltage Logic 1 VOH 215Output Voltage Logic 0 VOL 215Threshold Voltage Logic 1 VOHA 215Threshold Voltage Logic 0 VOLA 215Switching Times (50Ω Load)Propagation Delay350495920220310575220310575µAdcIinL 5 0.5 0.5 0.3 µAdct1+3–t1+4–t9+2+t9+2–3422–1.060–1.060–1.890–1.890–1.080–1.0801.61.61.61.6–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 1.0 4.1 1.1 1.8 4.0 1.1 4.4Fall Time (20 to 80%) t2– 2 1.0 4.1 1.1 1.8 4.0 1.1 4.4–0.700–0.700–1.615–1.615–1.595–1.595Setup Time tsetup 2 2.5 2.5 2.5 2.5 nsHold Time thold 2 1.5 1.5 –1.5 1.5 nsToggle Frequency (Max) ftog 2 125 125 150 125 MHz4.64.64.64.61.61.61.61.62.52.53.53.54.54.54.54.51.61.61.61.65.05.05.05.0VdcVdcVdcVdcnsOutput level to be measured after clock pulse.VILVIHappears at clock input (Pin 9).http://onsemi.com399

MC10186ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 16Input Current IinH 591Output Voltage Logic 1 VOH 215Output Voltage Logic 0 VOL 215Threshold Voltage Logic 1 VOHA 215Threshold Voltage Logic 0 VOLA 215591888(VCC)GndIinL 5 5 8 16512Switching Times (50Ω Load) +1.11Vdc +0.31V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt1+3–t1+4–t9+2+t9+2–3422Rise Time (20 to 80%) t2+ 2 5, 9 2 8 16Fall Time (20 to 80%) t2– 2 5, 9 2 8 16Setup Time tsetup 2 5, 9 2 8 16Hold Time thold 2 5, 9 2 8 16Toggle Frequency (Max) ftog 2 8 16675125121, 91, 95, 95, 95123422888888888888161616161616161616161616161616Output level to be measured after clock pulse.VILVIHappears at clock input (Pin 9).Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com400

The MC10188 is a high–speed hex buffer with a common Enableinput. When Enable is in the high state, all outputs are in the low state.When Enable is in the low state, the outputs take the same state as theinputs.• Power Dissipation = 180 mW typ/pkg (No Load)• Propagation Delay = 2.0 ns typ (B – Q)2.5 ns typ (A – Q)956XYLOGIC DIAGRAMOUT23http://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10188LAWLYYWW10VCC1 = PIN 111VCC2 = PIN 16VEE = PIN 8 1274131415PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775161MC10188PAWLYYWW110188AWLYYWWDIP PIN ASSIGNMENTVCC1AOUTBOUTCOUTAINBINCINVEE12345678161514131211109VCC2FOUTEOUTDOUTFINEINDINCOMMONPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10188L CDIP–16 25 Units / RailMC10188P PDIP–16 25 Units / RailMC10188FN PLCC–20 46 Units / RailTRUTH TABLEInputs OutputX Y OUTL L LL H HH L LH H L© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6401 Publication Order Number:MC10188/D

MC10188ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Max Min Max UnitPower Supply Drain Current IE 8 46 42 46 mAdcInput Current IinH 5 425 265 265 µAdcIinH 9 460 290 290 µAdcOutput Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 2 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 2 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load) nsPropagation DelayEnableDatatPHLtPLH221.11.03.93.31.11.03.52.91.11.03.93.3Rise/Fall Time (20 to 80%) tTLHtTHL2 1.1 3.7 1.1 3.3 1.1 3.7ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 5 5 8 1, 16(VCC)GndIinH 9 9 8 1, 16Output Voltage Logic 1 VOH 2 5 8 1, 16Output Voltage Logic 0 VOL 2 9 8 1, 16Threshold Voltage Logic 1 VOHA 2 5 8 1, 16Threshold Voltage Logic 0 VOLA 2 5 8 1, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation DelayEnableDatatPHLtPLH22Rise/Fall Time (20 to 80%) tTLH2 5 2 8 1, 16tTHLEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.9522881, 161, 16http://onsemi.com402

The MC10189 provides a high-speed Hex Inverter with a commonEnable input. The hex inverting function is provided when Enable is inthe low state. When Enable is in the high state all outputs are low.• PD = 200 mW typ/pkg (No Load)• tpd = 2.0 ns (Y–Q)= 2.5 ns (X–Q)956710XYLOGIC DIAGRAMOUT23413http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10189LAWLYYWWMC10189PAWLYYWW111VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8 121415PLCC–20FN SUFFIXCASE 77510189AWLYYWWDIP PIN ASSIGNMENTVCC1AOUTBOUTCOUTAINBINCINVEE12345678161514131211109VCC2FOUTEOUTDOUTFINEINDINCOMMONA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10189L CDIP–16 25 Units / RailMC10189P PDIP–16 25 Units / RailMC10189FN PLCC–20 46 Units / RailPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.TRUTH TABLEInputs OutputX Y OUTL L HL H LH L LH H L© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6403 Publication Order Number:MC10189/D

MC10189ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Max Min Max UnitPower Supply Drain Current IE 8 44 40 44 mAdcInput Current IinH 5 425 265 265 µAdcIinL 9 890 555 555 µAdcOutput Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 2 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 2 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load) nsPropagation DelayEnableDatatPHLtPLH221.11.03.93.31.11.03.52.91.11.03.93.3Rise/Fall Time (20 to 80%) tTLHtTHL2 1.1 3.7 1.1 3.3 1.1 3.7ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 5 5 8 1, 16(VCC)GndIinL 9 9 8 1, 16Output Voltage Logic 1 VOH 2 5 8 1, 16Output Voltage Logic 0 VOL 2 9 8 1, 16Threshold Voltage Logic 1 VOHA 2 5 8 1, 16Threshold Voltage Logic 0 VOLA 2 5 8 1, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation DelayEnableDatatPHLtPLH22Rise/Fall Time (20 to 80%) tTLH2 5 2 8 1, 16tTHLEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.9522881, 161, 16http://onsemi.com404

The MC10192 contains four line drivers with complementaryoutputs. Each driver has a Data (D) input and shares an Enable (E)input with another driver. The two driver outputs are the uncommittedcollectors of a pair of NPN transistors operating as a current switch.Each driver accepts 10K MECL input signals and provides a nominalsignal swing of 800 mV across a 50 Ω load at each output collector.Outputs can drive higher values of load resistance, provided that thecombination of IR drop and load return voltage VLR does not cause anoutput collector to go more negative than –2.4 V with respect to VCC.To avoid output transistor breakdown, the load return voltage shouldnot be more positive than +5.5 V with respect to VCC. When the Einput is high, both output transistors of a driver are nonconducting.When not used, the E inputs, as well as the D inputs, may be left open.• Open Collector Outputs Drive Terminated Lines orTransformers• 50 kW Input Pulldown Resistors on All Inputs (UnusedInputs May Be Left Open)• Power Dissipation = 575 mW typ/pkg (No Load)• Propagation Delay = 3.5 ns typ (E — Output)3.0 ns typ (D — Output)E1 7D1D256LOGIC DIAGRAM3412Z1Z1Z2Z2http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 775MARKINGDIAGRAMS16116A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDIP PIN ASSIGNMENT1MC10192LAWLYYWWMC10192PAWLYYWW110192AWLYYWWD3 1015Z3Z2116VCCD4 11E2 9VCC = PIN 16VEE = PIN 8141312Z3Z4Z4Z2Z1Z1D1D2E1234567151413121110Z3Z3Z4Z4D4D3TRUTH TABLEVEE89E2InputsOutputE D Z ZH X H HPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.L H H LL L L HNote: Unused outputs must be terminatedto V CC for proper operation.ORDERING INFORMATIONDevice Package ShippingMC10192L CDIP–16 25 Units / RailMC10192P PDIP–16 25 Units / RailMC10192FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6405 Publication Order Number:MC10192/D

MC10192ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Max Min Max UnitPower Supply Drain Current IE 8 154 140 154 mAdcInput Current IinH 5 350 220 220 µAdcIinL 5 0.5 0.5 0.3 µAdcOutput Current High Logic 1 IOH 2 2.0 mAdcOutput Current Low Logic 0 IOL 2 13.5 18.0 14.0 18.0 14.0 19.0 mAdcThreshold Current High Logic 1 IOHC 2 2.0 2.0 2.0 mAdcThreshold Current Low Logic 0 IOLC 2 13.5 14.0 14.0 mAdcOutput Sink Current Low Logic 0 IOS 2 13.3 13.9 13.3 mAdcLoad Return Voltage Absolute MaxRating (Note 1.)VLR 5.5 5.5 5.5 VOutput Voltage Low (Note 2.) VOLS –2.4 VSwitching Times (50Ω Load) nsPropagation DelayE to OutputD to OutputtPHLtPLHRise/Fall Time (20 to 80%) tTLHtTHL1. The 5.5V value is a maximum rating, do not exceed. A 270Ω resistor will prevent output transistor breakdown.2. Limitations of load resistor and load return voltage combinations. Refer to page 405 description.2.01.56.04.53.3ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 16Input Current IinH 5 5 8 16(VCC)GndIinL 5 5 8 16Output Current High Logic 1 IOH 2 5,6,10,11 8 16Output Current Low Logic 0 IOL 2 5,6,10,11 8 16Threshold Current High Logic 1 IOHC 2 5,7,9,10,11 6 8 16Threshold Current Low Logic 0 IOLC 5,10,11 7,9 6 8 16Output Sink Current Low Logic 0 IOS 2 5,6,10,11 8 16Load Return Voltage Absolute MaxRating (Note 1.)VLR 8 16Output Voltage Low (Note 2.) VOLS 8 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com406

The MC10195 is a Hex Buffer Inverter which is built using sixEXCLUSIVE NOR gates. There is a common input to these gateswhich when placed low or left open allows them to act as inverters.With the common input connected to a high logic level the MC10195is a hex buffer, useful for high fanout clock driving and reducing stublengths on long bus lines.• PD = 200 mW typ/pkg (No Load)• tpd = 2.8 ns typ (B–Q)• tpd = 3.8 ns typ (A–Q)• tr, tf = 2.5 ns typ (20%–80%)956ABLOGIC DIAGRAMQ23http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10195LAWLYYWWMC10195PAWLYYWW174PLCC–20FN SUFFIXCASE 77510195AWLYYWW1013A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1114DIP PIN ASSIGNMENT1215VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8VCC1Q1Q2Q3123416151413VCC2Q6Q5Q4TRUTH TABLEInputs OutputA B QL L HL H LH L LH H HB1B2B3VEE56781211109Pin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.B6B5B4AORDERING INFORMATIONDevice Package ShippingMC10195L CDIP–16 25 Units / RailMC10195P PDIP–16 25 Units / RailMC10195FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6407 Publication Order Number:MC10195/D

MC10195ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 54 39 49 54 mAdcInput Current IinH 59425460265290265290µAdcIinL 5 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 2 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 2 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)Propagation Delayt5+2– 2 1.1 4.2 1.1 2.8 4.0 1.1 4.4t7–4+ 4 1.1 4.2 1.1 2.8 4.0 1.1 4.4t10+13+ 13 1.1 4.2 1.1 2.8 4.0 1.1 4.4t11–14– 14 1.1 4.2 1.1 2.8 4.0 1.1 4.4t9–14– 14 1.1 5.2 1.1 3.8 5.0 1.1 5.4Rise Time (20 to 80%) t2+ 2 1.1 4.7 1.1 2.5 4.5 1.1 5.0Fall Time (20 to 80%) t2– 2 1.1 4.7 1.1 2.5 4.5 1.1 5.0nsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 595988(VCC)Gnd1, 161, 16IinL 5 5 8 1, 16Output Voltage Logic 1 VOH 2 8 1, 16Output Voltage Logic 0 VOL 2 9 8 1, 16Threshold Voltage Logic 1 VOHA 2 5 8 1, 16Threshold Voltage Logic 0 VOLA 2 5 8 1, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt5+2–t7–4+t10+13+t11–14–t9–14–24131414Rise Time (20 to 80%) t2+ 2 5 2 8 1, 16Fall Time (20 to 80%) t2– 2 5 2 8 1, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.571011924131414888881, 161, 161, 161, 161, 16http://onsemi.com408

The MC10197 provides a high speed hex AND function with strobecapability.• PD = 200 mW typ/pkg (No Load)• tpd = 2.8 ns typ (B–Q)• tpd = 3.8 ns typ (A–Q)• tr, tf = 2.5 ns typ (20%–80%)956BLOGIC DIAGRAMAQ23http://onsemi.comCDIP–16L SUFFIXCASE 620161MARKINGDIAGRAMSMC10197LAWLYYWW710413PDIP–16P SUFFIXCASE 648161MC10197PAWLYYWW1VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 811121415PLCC–20FN SUFFIXCASE 77510197AWLYYWWVCC1AOUTBOUTCOUTAINBINCINVEEDIP PIN ASSIGNMENT12345678161514131211109VCC2FOUTEOUTDOUTFINEINDINCOMMONPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekORDERING INFORMATIONDevice Package ShippingMC10197L CDIP–16 25 Units / RailMC10197P PDIP–16 25 Units / RailMC10197FN PLCC–20 46 Units / RailTRUTH TABLEInputs OutputA B QL L LL H LH L LH H H© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6409 Publication Order Number:MC10197/D

MC10197ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 54 39 49 54 mAdcInput Current IinH 59425460265290265290µAdcIinL 5 0.5 0.5 0.3 µAdcOutput Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 VdcOutput Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 VdcThreshold Voltage Logic 1 VOHA 2 –1.080 –0.980 –0.910 VdcThreshold Voltage Logic 0 VOLA 2 –1.655 –1.630 –1.595 VdcSwitching Times (50Ω Load)Propagation Delayt5+2+t9+2+221.11.1Rise Time (20 to 80%) t2+ 2 1.1 4.7 1.1 2.5 4.5 1.1 5.0Fall Time (20 to 80%) t2– 2 1.1 4.7 1.1 2.5 4.5 1.1 5.04.25.31.11.12.83.54.05.01.11.14.45.5nsELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 595988(VCC)Gnd1, 161, 16IinL 5 5 8 1, 16Output Voltage Logic 1 VOH 2 5, 9 8 1, 16Output Voltage Logic 0 VOL 2 8 1, 16Threshold Voltage Logic 1 VOHA 2 9 5 8 1, 16Threshold Voltage Logic 0 VOLA 2 9 5 8 1, 16Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt5+2+t9+2+22Rise Time (20 to 80%) t2+ 2 9 5 2 8 1, 16Fall Time (20 to 80%) t2– 2 9 5 2 8 1, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.955922881, 161, 16http://onsemi.com410

The MC10198 is a retriggerable monostable multivibrator. Twoenable inputs permit triggering on any combination of positive ornegative edges as shown in the accompanying table. The trigger inputis buffered by Schmitt triggers making it insensitive to input rise andfall times.The pulse width is controlled by an external capacitor and resistor.The resistor sets a current which is the linear discharge rate of thecapacitor. Also, the pulse width can be controlled by an externalcurrent source or voltage (see applications information).For high–speed response with minimum delay, a hi–speed input isalso provided. This input bypasses the internal Schmitt triggers and theoutput responds within 2 nanoseconds typically.Output logic and threshold levels are standard MECL 10,000. Testconditions are per Table 2. Each “Precondition” referred to in Table 2is per the sequence of Table 1.• PD = 415 mW typ/pkg (No Load)• tpd = 4.0 ns typ Trigger Input to Q• 2.0 ns typ Hi–Speed Input to Q• Min Timing Pulse Width PWQmin 10 ns typ1• Max Timing Pulse Width PWQmax >10 ms typ2• Min Trigger Pulse Width PWT 2.0 ns typ• Min Hi–Speed PWHS 3.0 ns typTrigger Pulse Width• Enable Setup Time tset 1.0 ns typ• Enable Hold Time thold 1.0 ns typ• 1 CExt = 0 (Pin 4 open), RExt = 0(Pin 6 to VEE)• 2 CExt = 10 mF, RExt = 2.7 kWhttp://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1161MARKINGDIAGRAMSMC10198LAWLYYWWMC10198PAWLYYWW110198AWLYYWWORDERING INFORMATIONDevice Package ShippingMC10198L CDIP–16 25 Units / RailMC10198P PDIP–16 25 Units / RailMC10198FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6411 Publication Order Number:MC10198/D

MC10198LOGIC DIAGRAMVEEVCCDIPPIN ASSIGNMENT116V CC2571013156 4REXT CEXTE posQEXTERNAL PULSEWIDTH CONTROLENEGTRIGGERINPUTHI–SPEEDINPUTQ3VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 82V CC1QQC EXTE POSR EXTEXT.PULSEWIDTH CONTROLV EE23456781514131211109HIGH–SPEEDINPUTN/CTRIGGER INPUTN/CN/CE NEGN/CINPUTTRUTH TABLEOUTPUTPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.EPosLLHHENegLHLHTriggers on both positive & negative input slopesTriggers on positive input slopeTriggers on negative input slopeTrigger is disabledTABLE 1 — PRECONDITION SEQUENCEPin 4 Voltage (Vdc)0(Gnd)–1.0–2.0–3.0–4.0 10 ns 10 nsPin 1open1. At t = 0 a.) Apply V IHmax to Pin 5 and 10.b.) Apply V ILmin to Pin 15.c.) Ground Pin 4.2. At t 10 ns a.) Open Pin 1.b.) Apply –3.0 Vdc to Pin 4.Hold these conditions for10 ns.3. Return Pin 4 to Ground and perform test asindicated in Table 2.–5.0010 20t(ns)30TABLE 2 — CONDITIONS FOR TESTING OUTPUT LEVELS(See Table 1 for Precondition Sequence)V IH maxV ILA maxV IHA maxP1V IL minP2V IL minP3V IL minPins 1, 16 = V CC = GroundPins 6, 8 = V EE = –5.2 VdcOutputs loaded 50 Ω to –2.0 Vdchttp://onsemi.com412

MC10198Pin ConditionsPin ConditionsTest P.U.T. 5 10 13 15 Test P.U.T. 5 10 13 15PreconditionPreconditionVOH 2 VIL min VOHA 2 VIHA min P1VOH 3 P1 VOHA 3 VILA max P1PreconditionPreconditionVOL 3 VIL min VOLA 3 VILA maxVOL 2 P1 VOLA 2 VIHA minPreconditionPreconditionVOHA 2 VILA max VOLA 2 VIL minVOHA 3 VIHA min VOLA 3 VIL minPreconditionPreconditionVOHA 2 VIL min VOLA 3 P2VOHA 3 P3 VOLA 2 P3PreconditionPreconditionVOHA 2 P2 VOLA 3 VIH max P2VOHA 3 P3 VOLA 2 VIH max P3PreconditionPreconditionVOHA 2 VIH max P2 VOLA 3 VIHA min VIH max P1VOHA 3 VIH max P3 VOLA 2 VILA max VIH max P1PreconditionPreconditionVOHA 2 VIH max P1 VOLA 3 VIH max VIHA min P1VOHA 3 VIH max P1 VOLA 2 VIH max VILA max P1http://onsemi.com413

MC10198ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 110 80 100 110 mAdcInput Current IinH 5, 101315Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23Switching Times (50Ω Load)Trigger Input415350560260220350260220350µAdcIinL 5 0.5 0.5 0.3 µAdctT+Q+tT–Q+33–1.060–1.060–1.890–1.890–1.080–1.0802.52.5–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.980–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910–0.700–0.700–1.615–1.615–1.595–1.595High Speed Trigger Input tHS+Q+ 3 1.5 3.2 1.5 2.0 2.8 1.5 3.2 nsMinimum Timing PulseWidthMaximum Timing PulseWidth6.56.52.52.5PWQmin 3 10.0 nsPWQmax 3 >10 msMin Trigger Pulse Width PWT 3 2.0 nsMin Hi–Spd Trig Pulse Width PWHS 3 3.0 nsRise Time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 nsFall Time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 nsEnable Setup Time tsetup (E) 3 1.0 nsEnable Hold Time thold (E) 3 1.0 ns1. The monostable is in the timing mode at the time of this test.2. CEXT = 0 (Pin 4 Open); REXT = 0 (Pin 6 tied to VEE).3. CEXT = 10µF (Pin); REXT = 2.7k (Pin 6).4.04.05.55.52.52.56.56.5VdcVdcVdcVdcns4.P1VIHmaxVILminhttp://onsemi.com414

MC10198ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEE(VCC)GndPower Supply Drain Current IE 8 6, 8 1, 4, 16Input Current IinH 5, 1013155,101315Output Voltage Logic 1 VOH 23 13 (4.)Output Voltage Logic 0 VOL 236, 86, 86, 81, 4, 161, 4, 161, 4, 16IinL 5 5 6, 8 1, 4, 1613 (4.)Threshold Voltage Logic 1 VOHA 23 15Threshold Voltage Logic 0 VOLA 2313 6, 86, 813156, 86, 815 6, 86, 8156, 86, 81, 4, 161, 4, 161, 4, 161, 4, 161, 16, 41, 16, 41, 16, 41, 16, 4Switching Times (50Ω Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 VTrigger InputtT+Q+tT–Q+331051313336, 86, 81, 16, 41, 16, 4High Speed Trigger Input tHS+Q+ 3 15 3 6, 8 1, 16, 4Minimum Timing Pulse Width PWQmin 3 Note 2. 6, 8 1, 16, 4Maximum Timing Pulse Width PWQmax 3 Note 3. 6, 8 1, 16, 4Minimum Trigger Pulse Width PWT 3 13 3 6, 8 1, 16, 4Minimum Hi–Spd Trigger PulseWidthPWHS 3 15 3 6, 8 1, 16, 4Rise Time (20 to 80%) 3 6, 8 1, 16, 4Fall Time (20 to 80%) 3 6, 8 1, 16, 4Enable Setup Time tsetup (E) 3 5 3 6, 8 1, 16, 4Enable Hold Time thold (E) 3 5 3 6, 8 1, 16, 41. The monostable is in the timing mode at the time of this test.2. CEXT = 0 (Pin 4 Open); REXT = 0 (Pin 6 tied to VEE).3. CEXT = 10µF (Pin); REXT = 2.7k (Pin 6).4.P1VIHmaxVILminEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com415

MC10198SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°CVinVCC1 = VCC2 = +2.0 VdcVout25 µF0.1 µFCoaxCoax5EPosInput0.1 µFTPinPulse Generator+1.11 VInput Pulse7101315External PulseWidth ControlENegTrigger InputHi–Speed InputQ3TPoutt+ = t– = 2.0 ± 0.2 ns(20 to 80%)6RExtQ24CExt50–ohm termination to ground locatedin each scope channel input.All input and output cables to the scopeare equal lengths of 50–ohm coaxialcable. Wire length should be < 1/4 inchfrom TP in to input pin and TP out tooutput pin.VEE = –3.2 Vdc0.1 µFUnused outputs are tied to a50–ohm resistor to ground.EPosTrigger Input50%tsetup (E)50%QtT+Q+PWTtT–Q+50%50%tHold(E)PWQHigh–SpeedTrigger InputQtHS+Q+PWHSPWQhttp://onsemi.com416

MC10198APPLICATIONS INFORMATIONCircuit Operation:3. PULSE WIDTH TIMING — The pulse width is determined by the external resistor and capacitor. The MC10198also has an internal resistor (nominally 284 ohms) that can be used in series with RExt. Pin 7, the external pulsewidth control, is a constant voltage node (–3.60 V nominally). A resistance connected in series from this node toVEE sets a constant timing current IT. This current determines the discharge rate of the capacitor:where∆T = pulse width∆V = 1.9 V change in capacitor voltageFIGURE 2 – TIMING PULSE WIDTH versus CExt and RExt100Then: IT = CExt∆V∆TIf RExt + RInt are in series to VEE:1010 kΩIT = [(–3.60 V) – (–5.2 V)] ÷ [RExt + 284 Ω]3 kΩIT = 1.6 V/(RExt + 284)1500 ΩThe timing equation becomes: ∆T = CExt 1.9 VIT100∆T = [(CExt)(1.9 V)] ÷ [1.6 V/(RExt + 284)]RExt = 0 NOTE: TOTAL RESISTANCE= RExt + RInt∆T = CExt (RExt + 284) 1.1910where ∆T = Sec10 pF 100 pF 1000 pF 0.01 µF 0.1 µFRExt = OhmsCExt – TIMING CAPACITANCECExt = FaradsFigure 2 shows typical curves for pulse width versus CExtand RExt (total resistance includes RInt). Any low leakage capacitorcan be used and RExt can vary from 0 to 16 k–ohms.4. TRIGGERING —The Epos and ENeg inputs control the trigger input. The MC10198 can be programmed to triggeron the positive edge, negative edge, or both. Also, the trigger input can be totally disabled. The truth table isshown on the first page of the data sheet.The device is totally retriggerable. However, as duty cycleapproaches 100%, pulse width jitter can occur due to the recoverytime of the circuit. Recovery time is basically dependenton capacitance CExt. Figure 3 shows typical recoverytime versus capacitance at IT = 5 mA.FIGURE 3 — RECOVERY TIME versusFIGURE 1 —CExt @ IT = 5 mA4CExtPULSE WIDTH ( µ s)10 µsMC10198RInt284 Ω7–3.60 V ExternalPulse Width ControlRECOVERY TIME1 µs100 ns610 nsRExtVEE = –5.2 V1 ns10 pF100 pF 1000 pF 0.01 µFCExt – TIMING CAPACITANCE0.1 µFhttp://onsemi.com417

MC101985. HI–SPEED INPUT — This input is used for stretching very narrow pulses with minimum delay between the outputpulse and the trigger pulse. The trigger input should be disabled when using the high–speed input. The MC10198triggers on the rising edge, using this input, and input pulse width should narrow, typically less than 10 nanoseconds.USAGE RULES:1. Capacitor lead lengths should be kept very short to minimize ringing due to fast recovery rise times.2. The E inputs should not be tied to ground to establish a high logic level. A resistor divider or diode can be used toestablish a –0.7 to –0.9 voltage level.3. For optimum temperature stability; 0.5 mA is the best timing current IT. The device is designed to have a constantvoltage at the EXTERNAL PULSE WIDTH CONTROL over temperature at this current value.4. Pulse Width modulation can be attained with the EXTERNAL PULSE WIDTH CONTROL. The timing current canbe altered to vary the pulse width. Two schemes are:a. The internal resistor is not used. A dependent currentsource is used to set the timing current asshown in Figure 4. A graph of pulse width versustiming current (CExt = 13 pF) is shown in Figure5.b. A control voltage can also be used to vary the pulsewidth using an additional resistor (Figure 6). Thecurrent (IT + IC) is set by the voltage drop acrossRInt + RExt. The control current IC modifies IT andalters the pulse width. Current IC should neverforce IT to zero. RC typically 1 kΩ.FIGURE 4 —1000FIGURE 5 — PULSE WIDTH versus IT @ CExt = 13 pF4CExtMC101987PULSE WIDTH (ns)100I100.01 mA 0.1 mA 1 mA 10 mAIT – TIMING CURRENTFIGURE 6 —4CExt284IT7–3.6VICRCControlVoltage6IT + ICRExt–5.2 Vhttp://onsemi.com418

MC101985. The MC10198 can be made non–retriggerable. TheQ output is fed back to disable the trigger input duringthe triggered state (Logic Diagram). Figure 7shows a positive triggered configuration; a similarconfiguration can be made for negative triggering.FIGURE 7 —VEEVCCRExtCExt6 4E PosQExternal PulseWidth Control–0.9 VENegTriggerInputHi–SpeedInputQhttp://onsemi.com419

The MC10210 is designed to drive up to six transmission linessimul– taneously. The multiple outputs of this device also allow thewire “OR”–ing of several levels of gating for minimization of gate andpackage count.The ability to control three parallel lines with minimum propagationdelay from a single point makes the MC10210 particularly useful inclock distribution applications where minimum clock skew is desired.• PD = 160 mW typ/pkg (No Loads)• tpd = 1.5 ns typ (All Output Loaded)• tr, tf = 1.5 ns typ (20%–80%)567LOGIC DIAGRAM10 9 121113234http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648161161MARKINGDIAGRAMSMC10210LAWLYYWWMC10210PAWLYYWW1VCC1 = PIN 1, 15VCC2 = PIN 16VEE = PIN 814PLCC–20FN SUFFIXCASE 77510210AWLYYWWDIPPIN ASSIGNMENTA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekVCC1AOUTAOUTAOUTAINAIN123456161514131211VCC2VCC1BOUTBOUTBOUTBINORDERING INFORMATIONDevice Package ShippingMC10210L CDIP–16 25 Units / RailMC10210P PDIP–16 25 Units / RailMC10210FN PLCC–20 46 Units / RailAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6420 Publication Order Number:MC10210/D

MC10210ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 42 38 42 mAdcInput Current IinH 5, 6, 7 650 410 410 µAdcOutput Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234Switching Times (50Ω Load)Propagation DelayIinL 5, 6, 7 0.5 0.5 0.3 µAdct5+2+t5–2–t5+3+t5–3–t5+4+t5–4–Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–223344234234–1.060–1.060–1.060–1.890–1.890–1.890–1.080–1.080–1.0801.01.01.01.01.01.01.01.01.01.01.01.0–0.890–0.890–0.890–1.675–1.675–1.675–1.655–1.655–1.6552.62.62.62.62.62.62.62.62.62.62.62.6–0.960–0.960–0.960–1.850–1.850–1.850–0.980–0.980–0.9801.01.01.01.01.01.01.01.01.01.01.01.01.51.51.51.51.51.51.51.51.51.51.51.5–0.810–0.810–0.810–1.650–1.650–1.650–1.630–1.630–1.6302.52.52.52.52.52.52.52.52.52.52.52.5–0.890–0.890–0.890–1.825–1.825–1.825–0.910–0.910–0.9101.01.01.01.01.01.01.01.01.01.01.01.0–0.700–0.700–0.700–1.615–1.615–1.615–1.595–1.595–1.5952.82.82.82.82.82.82.82.82.82.82.82.8VdcVdcVdcVdcnshttp://onsemi.com421

MC10210ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWCharacteristicSymbolUnderTest VIHmax VILmin VIHAmin VILAmax VEE(VCC)GndPower Supply Drain Current IE 8 8 1, 15, 16Input Current IinH 5, 6, 7 * 8 1, 15, 16Output Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234IinL 5, 6, 7 * 8 1, 15, 165675675678888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt5+2+t5–2–t5+3+t5–3–t5+4+t5–4–Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–* Individually test each input using the pin connections shown.2233442342345555555555552233442342348888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com422

The MC10211 is designed to drive up to six transmission linessimul– taneously. The multiple outputs of this device also allow thewire “OR”–ing of several levels of gating for minimization of gate andpackage count.The ability to control three parallel lines with minimum propagationdelay from a single point makes the MC10211 particularly useful inclock distribution applications where minimum clock skew is desired.• PD = 160 mW typ/pkg (No Loads)• tpd = 1.5 ns typ (All Output Loaded)• tr, tf = 1.5 ns typ (20%–80%)567LOGIC DIAGRAMVCC1 = PIN 1, 15VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT1210 9 131411234http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10211LAWLYYWWMC10211PAWLYYWW110211AWLYYWWVCC1AOUTAOUTAOUT123416151413VCC2VCC1BOUTBOUTORDERING INFORMATIONDevice Package ShippingMC10211L CDIP–16 25 Units / RailAIN512BOUTMC10211P PDIP–16 25 Units / RailAIN611BINMC10211FN PLCC–20 46 Units / RailAIN710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6423 Publication Order Number:MC10211/D

MC10211ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 42 30 38 42 mAdcInput Current IinH 5, 6, 7 650 410 410 µAdcOutput Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234Switching Times (50Ω Load)Propagation DelayIinL 5, 6, 7 0.5 0.5 0.3 µAdct5+2–t5–2+t5+3–t5–3+t5+4–t5–4+Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–223344234234–1.060–1.060–1.060–1.890–1.890–1.890–1.080–1.080–1.0801.01.01.01.01.01.01.01.01.01.01.01.0–0.890–0.890–0.890–1.675–1.675–1.675–1.655–1.655–1.6552.62.62.62.62.62.62.62.62.62.62.62.6–0.960–0.960–0.960–1.850–1.850–1.850–0.980–0.980–0.9801.01.01.01.01.01.01.01.01.01.01.01.01.51.51.51.51.51.51.51.51.51.51.51.5–0.810–0.810–0.810–1.650–1.650–1.650–1.630–1.630–1.6302.52.52.52.52.52.52.52.52.52.52.52.5–0.890–0.890–0.890–1.825–1.825–1.825–0.910–0.910–0.9101.01.01.01.01.01.01.01.01.01.01.01.0–0.700–0.700–0.700–1.615–1.615–1.615–1.595–1.595–1.5952.82.82.82.82.82.82.82.82.82.82.82.8VdcVdcVdcVdcnshttp://onsemi.com424

MC10211ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWCharacteristicSymbolUnderTest VIHmax VILmin VIHAmin VILAmax VEE(VCC)GndPower Supply Drain Current IE 8 8 1, 15, 16Input Current IinH 5, 6, 7 * 8 1, 15, 16Output Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234IinL 5, 6, 7 * 8 1, 15, 165675675678888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt5+2–t5–2+t5+3–t5–3+t5+4–t5–4+Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–* Individually test each input using the pin connections shown.2233442342345555555555552233442342348888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com425

The MC10212 is designed to drive up to six transmission linessimul– taneously. The multiple outputs of this device also allow thewire “OR”–ing of several levels of gating for minimization of gate andpackage count.The ability to control three parallel lines with minimum propagationdelay from a single point makes the MC10212 particularly useful inclock distribution applications where minimum clock skew is desired.• PD = 160 mW typ/pkg (No Load)• tpd = 1.5 ns typ (All Outputs Loaded)• tr, tf = 1.5 ns typ (20%–80%)567LOGIC DIAGRAMVCC1 = PIN 1, 15VCC2 = PIN 16VEE = PIN 8DIPPIN ASSIGNMENT1210 9 131411432http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10212LAWLYYWWMC10212PAWLYYWW110212AWLYYWWVCC1116VCC2AOUT215VCC1ORDERING INFORMATIONAOUT314BOUTDevice Package ShippingAOUT413BOUTMC10212L CDIP–16 25 Units / RailAIN512BOUTMC10212P PDIP–16 25 Units / RailAINAIN671110BINBINMC10212FN PLCC–20 46 Units / RailVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6426 Publication Order Number:MC10212/D

MC10212ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 42 30 38 42 mAdcInput Current IinH 5, 6, 7 650 410 410 µAdcOutput Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234Switching Times (50Ω Load)Propagation DelayIinL 5, 6, 7 0.5 0.5 0.3 µAdct5+2+t5–2–t5+3–t5–3+t5+4–t5–4+Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–223344234234–1.060–1.060–1.060–1.890–1.890–1.890–1.080–1.080–1.0801.01.01.01.01.01.01.01.01.01.01.01.0–0.890–0.890–0.890–1.675–1.675–1.675–1.655–1.655–1.6552.62.62.62.62.62.62.62.62.62.62.62.6–0.960–0.960–0.960–1.850–1.850–1.850–0.980–0.980–0.9801.01.01.01.01.01.01.01.01.01.01.01.01.51.51.51.51.51.51.51.51.51.51.51.5–0.810–0.810–0.810–1.650–1.650–1.650–1.630–1.630–1.6302.52.52.52.52.52.52.52.52.52.52.52.5–0.890–0.890–0.890–1.825–1.825–1.825–0.910–0.910–0.9101.01.01.01.01.01.01.01.01.01.01.01.0–0.700–0.700–0.700–1.615–1.615–1.615–1.595–1.595–1.5952.82.82.82.82.82.82.82.82.82.82.82.8VdcVdcVdcVdcnshttp://onsemi.com427

MC10212ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWCharacteristicSymbolUnderTest VIHmax VILmin VIHAmin VILAmax VEE(VCC)GndPower Supply Drain Current IE 8 8 1, 15, 16Input Current IinH 5, 6, 7 5, 6, 7* 8 1, 15, 16Output Voltage Logic 1 VOH 234Output Voltage Logic 0 VOL 234Threshold Voltage Logic 1 VOHA 234Threshold Voltage Logic 0 VOLA 234IinL 5, 6, 7 5, 6, 7* 8 1, 15, 165 88855555558888885 8881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt5+2+t5–2–t5+3–t5–3+t5+4–t5–4+Rise Time (20 to 80%) t2+t3+t4+Fall Time (20 to 80%) t2–t3–t4–* Individually test each input using the pin connections shown.2233442342345555555555552233442342348888888888881, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 161, 15, 16Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com428

The MC10216 is a high speed triple differential amplifier designedfor use in sensing differential signals over long lines. The base biassupply (VBB) is made available at pin 11 to make the device useful as aSchmitt trigger, or in other applications where a stable referencevoltage is necessary.Active current sources provide the MC10216 with excellentcommon mode noise rejection. If any amplifier in a package is notused, one input of that amplifier must be connected to VBB (pin 11) toprevent upsetting the current source bias network.Complementary outputs are provided to allow driving twisted pairlines, to enable cascading of several amplifiers in a chain, or simply toprovide complement outputs of the input logic function.• PD = 100 mW typ/pkg (No Load)• tpd = 1.8 ns typ (Single ended)• = 1.5 ns typ (Differential)• tr, tf = 1.5 ns typ (20%–80%)VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8459101213LOGIC DIAGRAMVBBDIP PIN ASSIGNMENT1511*V BB to be used to supply bias to the MC10216 only andbypassed (when used) with 0.01 µF to 0.1 µF capacitor.When the input pin with bubble goes positive, it’srespective output pin with bubble goes positive.236714http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648PLCC–20FN SUFFIXCASE 77516ORDERING INFORMATIONDevice Package ShippingMC10216L CDIP–16 25 Units / Rail116A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week1MARKINGDIAGRAMSMC10216LAWLYYWWMC10216PAWLYYWW110216AWLYYWWVCC1AOUT121615VCC2COUTMC10216P PDIP–16 25 Units / RailMC10216FN PLCC–20 46 Units / RailAOUT314COUTAIN413CINAIN512CINBOUT611VBBBOUT710BINVEE89BINPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tables on page 18.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6429 Publication Order Number:MC10216/D

MC10216ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 27 20 25 27 mAdcInput Current IinH 4 180 115 115 µAdcICBO 49Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 23Threshold Voltage Logic 1 VOHA 23Threshold Voltage Logic 0 VOLA 23–1.060–1.060–1.890–1.890–1.080–1.0801.51.5–0.890–0.890–1.675–1.675–1.655–1.655–0.960–0.960–1.850–1.850–0.980–0.9801.01.0–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.9101.01.0–0.700–0.700–1.615–1.615–1.595–1.595Reference Voltage VBB 11 –1.420 –1.280 –1.350 –1.230 –1.295 –1.150 VdcSwitching Times (50Ω Load)Propagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–* Delay is 1.5ns when inputs are driven differentially.Delay is 1.8ns when inputs are driven single ended.223323231.01.01.01.01.01.01.01.02.62.62.62.62.62.62.62.61.01.01.01.01.01.01.01.01.8*1.8*1.8*1.8*1.51.51.51.52.52.52.52.52.52.52.52.51.01.01.01.01.01.01.01.02.82.82.82.82.82.82.82.8µAdcVdcVdcVdcVdcnshttp://onsemi.com430

MC10216ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VBB VEESymbol–30°C –0.890 –1.890 –1.205 –1.500+25°C –0.810 –1.850 –1.105 –1.475+85°C –0.700 –1.825 –1.035 –1.440FromPin11–5.2–5.2–5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VBB VEEPower Supply Drain Current IE 8 4, 9, 12 5, 10, 13 8 1, 16Input Current IinH 4 4 9, 12 5, 10, 13 8 1, 16ICBO 49Output Voltage Logic 1 VOH 23Output Voltage Logic 0 VOL 2349, 129, 124Threshold Voltage Logic 1 VOHA 23 9, 12Threshold Voltage Logic 0 VOLA 23 9, 129, 124, 129, 12449, 129, 12 49, 12445, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 134 5, 10, 135, 10, 13Reference Voltage VBB 11 5, 10, 13 8 1, 168, 48, 9888888(VCC)GndSwitching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt4+2+t4–2–t4+3–t4–3+Rise Time (20 to 80%) t2+t3+Fall Time (20 to 80%) t2–t3–2233232344444444223323235, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 135, 10, 13Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.88888888881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16http://onsemi.com431

The MC10231 is a dual master–slave type D flip–flop.Asynchronous Set (S) and Reset (R) override Clock (CC) and ClockEnable (CE) inputs. Each flip–flop may be clocked separately byholding the common clock in the low state and using the enable inputsfor the clocking function. If the common clock is to be used to clockthe flip–flop, the Clock Enable inputs must be in the low state. In thiscase, the enable inputs perform the function of controlling thecommon clock.The output states of the flip–flop change on the positive transition ofthe clock. A change in the information present at the data (D) inputwill not affect the output information at any other time due tomaster–slave construction.• PD = 270 mW typ/pkg (No Load)• tpd = 2 ns typ• tTog = 225 MHz typ• tr, tf = 2.0 ns typ (20%–80%)http://onsemi.comCDIP–16L SUFFIXCASE 620PDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161161MC10231LAWLYYWWMC10231PAWLYYWW1S1 5LOGIC DIAGRAMPLCC–20FN SUFFIXCASE 77510231AWLYYWWD1 7CE1 6R1 4CC 9R2 13Q1Q123VCC1 = PIN 1VCC2 = PIN 16VEE = PIN 8A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekDIP PIN ASSIGNMENTCE2 11D2 10Q2Q21514VCC1Q1Q1123161514VCC2Q2Q2S2 12CLOCKED TRUTH TABLER–S TRUTH TABLEC D Qn+1 R S Qn+1L X Qn L L QnH L L L H HH H H H L LC = CE + CC. A clock H is a clocktransition from a low to a high state.H H N.D.N.D. = Not DefinedR1S1CE1D1VEE45678131211109R2S2CE2D2CCPin assignment is for Dual–in–Line Package.For PLCC pin assignment, see the Pin Conversion Tableson page 18.ORDERING INFORMATIONDevice Package ShippingMC10231L CDIP–16 25 Units / RailMC10231P PDIP–16 25 Units / RailMC10231FN PLCC–20 46 Units / Rail© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6432 Publication Order Number:MC10231/D

MC10231ELECTRICAL CHARACTERISTICSCharacteristicSymbolTest LimitsPinUnder–30°C +25°C +85°CTest Min Max Min Typ Max Min Max UnitPower Supply Drain Current IE 8 72 52 65 72 mAdcInput Current IinH 45679IinL 4, 5*6, 7, 9*Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 33Threshold Voltage Logic 1 VOHA 22Threshold Voltage Logic 0 VOLA 33Switching Times (50Ω Load)Clock InputPropagation Delayt9+2–t6+2+22–1.060–1.060–1.890–1.890–1.080–1.0801.51.5650650350350460–0.890–0.890–1.675–1.675–1.655–1.6550.50.5–0.960–0.960–1.850–1.850–0.980–0.980410410220220290–0.810–0.810–1.650–1.650–1.630–1.630–0.890–0.890–1.825–1.825–0.910–0.910Rise Time (20 to 80%) t2+ 2 0.9 3.3 1.0 1.3 3.1 1.0 3.6Fall Time (20 to 80%) t2– 2 0.9 3.3 1.0 1.3 3.1 1.0 3.63.43.41.51.52.02.03.33.31.61.6410410220220290–0.700–0.700–1.615–1.615–1.595–1.5953.73.7µAdcµAdcVdcVdcVdcVdcnsSet InputnsPropagation Delayt5+2+t12+15+t5+3–t12+14–2153141.11.11.11.13.43.43.43.41.11.11.11.12.02.02.02.03.33.33.33.31.21.21.21.23.73.73.73.7Reset InputnsPropagation Delayt4+2–t13+15–t4+3–t13+14+2153141.11.11.11.13.43.43.43.41.11.11.11.12.02.02.02.03.33.33.33.31.21.21.21.23.73.73.73.7Setup Time tsetup 7 1.5 1.0 1.5 nsHold Time thold 7 0.9 0.75 0.9 nsToggle Frequency (Max) ftog 2 200 200 225 200 MHz* Individually test each input; apply VILmin to pin under test.Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)VIHmaxVILminhttp://onsemi.com433

MC10231ELECTRICAL CHARACTERISTICS (continued)TEST VOLTAGE VALUES (Volts)Characteristic@ Test Temperature VIHmax VILmin VIHAmin VILAmax VEESymbol–30°C –0.890 –1.890 –1.205 –1.500 –5.2+25°C –0.810 –1.850 –1.105 –1.475 –5.2+85°C –0.700 –1.825 –1.035 –1.440 –5.2Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOWUnderTest VIHmax VILmin VIHAmin VILAmax VEEPower Supply Drain Current IE 8 8 1, 16Input Current IinH 45679IinL 4, 5*6, 7, 9*Output Voltage Logic 1 VOH 22Output Voltage Logic 0 VOL 33Threshold Voltage Logic 1 VOHA 22Threshold Voltage Logic 0 VOLA 33456795757**57 957 9888888888888888(VCC)GndSwitching Times (50Ω Load)Clock Input +1.11Vdc Pulse In Pulse Out –3.2 V +2.0 VPropagation Delayt9+2–t6+2+22 7Rise Time (20 to 80%) t2+ 2 7 9 2 8 1, 16Fall Time (20 to 80%) t2– 2 9 2 8 1, 169622881, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 161, 16Set InputPropagation Delayt5+2+t12+15+t5+3–t12+14–2153146951251221531488881, 161, 161, 161, 16Reset InputPropagation Delayt4+2–t13+15–t4+3–t13+14+2153146941341321531488881, 161, 161, 161, 16Setup Time tsetup 7 6, 7 2 8 1, 16Hold Time thold 7 6, 7 2 8 1, 16Toggle Frequency (Max) ftog 2 * * 6 2 8 1, 16* Individually test each input applying VIH or VIL to input under test.VIHmaxOutput level to be measured after a clock pulse has been applied to the CE Input (Pin 6)VILminEach MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has beenestablished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in thesame manner.http://onsemi.com434

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http://onsemi.com436CHAPTER 4Carrier Band Modem

The bipolar LSI MC68194 Carrier Band Modem (CBM) whencombined with the MC68824 Token Bus Controller provides an IEEE802.4 single channel, phase–coherent carrier band Local AreaNetwork (LAN) connection. The CBM performs the Physical Layerfunction including symbol encoding/decoding, signal transmissionand reception, and physical management. Features include:• Implements IEEE 802.4 single channel, phase–coherent FrequencyShift Keying (FSK) physical layer including receiver blanking.• Provides physical layer management including local loopback mode,transmitter enable, and reset.• Supports data rates from 1 to 10 Mbps. IEEE 802.4 standard uses 5or 10 Mbps.• Interfaces via standard serial interface to MC68824 Token BusController.• Crystal controlled transmit clock.• Recovery of clocked data through phase–locked loop.• RC controlled Jabber Inhibit Timer.• Single +5.0 volt power supply.• Available in 52–lead Cerquad package.PIN ASSIGNMENTS AND DEVICE MARKINGhttp://onsemi.comCERQUADFJ SUFFIXCASE 778BORDERING INFORMATIONDevice Package ShippingMC68194FJ CERQUAD 20 Units / RailMC68194FJR2 CERQUAD 450 Units / Reel8910111213141516171819207 6 5 4 3 21MC68194FJAWLYYWW52 51 50 49 48 47A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week4645444342414039383736353421 22 23 24 25 26 27 28 29 30 31 32 33© Semiconductor Components Industries, LLC, 1999February, 2000 – Rev. 6437 Publication Order Number:MC68194/D

MC68194TABLE OF CONTENTSPAGESECTION 1 — GENERAL DESCRIPTION1.1 TOKEN BUS LAN CARRIER BAND NODE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4391.2 CARRIER BAND MODULATION TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4391.3 MESSAGE (FRAME) FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4401.4 SYSTEM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440SECTION 2 — SIGNAL DESCRIPTION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442SECTION 3 — TRANSMITTER3.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4443.2 TRANSMIT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4443.3 JABBER INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4453.4 CLOCK GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4453.4.1 Parallel–Resonant, Fundamental Mode Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4453.4.2 Parallel–Resonant, Overtone Mode Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4463.4.3 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446SECTION 4 — RECEIVER AMPLIFIER/LIMITER WITH CARRIER DETECT4.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4474.2 AMPLIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4474.3 CARRIER DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447SECTION 5 — CLOCK RECOVERY5.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4485.2 ONE–SHOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4485.3 PHASE–LOCKED LOOP (PLL) COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4495.3.1 Phase Detector (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4495.3.2 Voltage Controlled Multivibrator (VCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4495.3.3 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4495.3.4 Loop Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450SECTION 6 — DATA RECOVERY6.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4506.2 RECEIVER END–OF–TRANSMISSION BLANKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451SECTION 7 — SERIAL INTERFACE7.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.2 PHYSICAL DATA REQUEST CHANNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.2.1 TXCLK — Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.2.2 SMREQ* — Station Management Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.2.3 TXSYM0, TXSYM1, and TXSYM2 — Transmit Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.3 PHYSICAL DATA INDICATION CHANNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.3.1 RXCLK — Receive Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.3.2 SMIND* — Station Management Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527.3.3 RXSYM0, RXSYM1, and RXSYM2 — Receive Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452SECTION 8 — PHYSICAL MANAGEMENT8.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4538.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4538.3 INTERNAL LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4538.4 STANDARD OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4538.5 IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4538.6 COMMAND RESPONSE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453SECTION 9 — ELECTRICAL SPECIFICATIONS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456http://onsemi.com438

MC68194SECTION 1GENERAL DESCRIPTION1.1 TOKEN BUS LAN CARRIER BAND NODE OVERVIEWThe MC68194 Carrier Band Modem (CBM) is part ofMotorola’s solution for an IEEE 802.4 token bus carrierband Local Area Network (LAN) node. The CBM integratesthe function of the single–channel, phase–coherentFrequency Shift Keying (FSK) physical layer. Figure 1–1illustrates the architecture of a token bus LAN node ascommonly used in Manufacturing Automation Protocol(MAP) industrial communications. Based on the ISO–OSImodel, the LLC Sublayer and additional upper layers aretypically supported by a local MPU subsystem, while theIEEE 802.4 token bus MAC Sublayer and Physical Layerare implemented by the MC68824 Token Bus Controller(TBC) and MC68194 CBM respectively.The MC68194 provides the three basic functions of thephysical layer including data transmission to the coax cable,data reception from the cable, and management of thephysical layer. For standard data mode (also called MACmode), the carrier band modem receives a serial transmitdata stream from the MC68824 TBC (called symbols oratomic symbols), encodes, modulates the carrier, andtransmits the signal to the coaxial cable. Also in the datamode, the CBM receives a signal from the cable,demodulates the signal, recovers the data, and sends thereceived data symbols to the TBC. Communication betweenthe TBC and CBM is through a standardized serial interfaceinconsistent with the IEEE 802.4 DTE–DCE serialinterface.SYSTEM BUSINTERFACEMODULATOR/TRANSMITTERMC68000PROCESSORTOKEN BUSCONTROLLERSTATI MGO MN TDEMODULATOR/RECEIVERMEMORYLLC&UPPERLAYERSMAC SUB–LAYERSERIAL INTERFACEPHYSICALLAYERMEDIA LAYERTOKEN BUS COAXFigure 1–1. IEEE 802.4 Token Bus Carrier Band NodeThe physical layer management provides the ability toreset the CBM, control the transmitter, and do loopbacktesting. Also, an onboard RC timer provides a “jabber”inhibit function to turn off the transmitter and report an errorcondition if the transmitter has been continuously on for toolong. Similar to the data mode, the CBM management modemakes use of the TBC serial interface.1.2 CARRIER BAND MODULATION TECHNIQUEThe CBM uses phase–coherent frequency shift keying(FSK) modulation on a single channel system. In thismodulation technique, the two signaling frequencies areintegrally related to the data rate, and transitions between thetwo signaling frequencies are made at zero crossings of thecarrier waveform. Figure 1–2 shows the data rate andsignaling frequencies. An {L} is represented as one halfcycle of a signal, starting and ending with a nominal zeroamplitude, whose period is equal to the period of the datarate, with the phase of one half cycle changing at eachsuccessive {L}. An {H} is represented as one full cycle ofa signal, starting and ending with a nominal zero amplitudewhose period is equal to half the period of the data rate. Ina 5 Mbps implementation, the frequency of {L} is 5.0 MHzand for {H} is 10 MHz. For a 10 Mbps implementation, thefrequency of {L} is 10 MHz and for {H} is 20 MHz. Theother possible physical symbol is when no signal occurs fora period equal to one half of the period of the data rate. Thiscondition is represented by {off}.Data RateMBPS510Frequency of LowerTone MHz {L}5.010Frequency of HigherTone MHz {H}1020Figure 1–2. Data Rate versus Signaling FrequenciesThe specified physical symbols ({L}, {H} and {off}) arecombined into pairs which are called MAC–symbols. TheMAC–symbols are transferred across the serial link. Theencodings for the five MAC–symbols are shown in Figure1–3. Figure 1–4 shows the phase coherent FSK modulationscheme for ONE, ZERO, and NON–DATA. The IEEE 802.4document does not specify the polarity used to transmit dataon the physical cable. The receiver must operate withoutrespect to polarity.Mac–SymbolEncodingSilencePad–Idle PairsZeroOneNon–DataND1ND2{off off}{L L} {H H}{H H}{L L}{H L}{L H}http://onsemi.com439

MC68194LHLHFigure 1–3. MAC Symbol EncodingONEZEROND1ND2Figure 1–4. Phase–Coherent Modulation SchemeHL1 BIT TIME =1/ BIT RATE1.3 MESSAGE (FRAME) FORMATLH1 BIT TIMEAlthough the CBM only uses MAC symbolsone–at–a–time, the MAC or TBC is responsible forcombining the above defined MAC symbols into messages(more correctly called frames). For the purposes of theCBM, a simplified frame format can be used consisting of:SILENCE || PAD–IDLE | START DELIMITER | DATA | ENDDELIMITER || SILENCEwhere:PAD–IDLE = alternating {LL} {HH} pairs which mustoccur in octets or groups of eight symbols.Pad–idle provides a training signalfor the receiver and occurs at the beginningof every transmission (and betweenframes in a multiple frame transmission).START = a unique pattern of eight symbols (one octet)that marks the beginning of a frame.DELIMITERThe pattern is:ND1 ND2 0 ND1 ND2 0 0 0where ND1 is the first symbol transmitted.DATA = octets of ZERO/ONE patterns that are theactual data or “information” containedwithin the frame.END = a unique pattern of symbols that marksDELIMITER the end of a frame. The pattern is:ND1 ND2 1 ND1 ND2 1 {I=0/1} {0/1}where ND1 is the first symbol transmitted.Note that unlike the Start Delimiter,the last two bits of the End Delimiteroctet are not always the same. Theseventh bit of the octet is called the I Bitor Intermediate bit which = 1 when thereis more to transmit and = 0 at the end ofa transmission.A single transmission can consist of one or more frames.In a multi–frame transmission, Pad–Idle is sent betweenconsecutive frames to separate them. If an End DelimiterNON-DATA PAIRoccurs within a multi–frame transmission its I Bit will = 1,and the last end delimiter will have its I Bit = 0.The CBM accepts a stream of MAC symbols from theTBC and modulates the phase–coherent transmit signalaccordingly. Conversely, the CBM receives aphase–coherent signal stream from the cable, decodes theMAC symbols, and reports them. On transmission there isa direct one–to–one correlation between MAC symbolsrequested and the modulated signal; however, duringreception exceptions can occur. The CBM is allowed toreport Silence or the actual Zero/One pattern duringpreamble which is done to allow the receiver to “train” to theincoming signal. Also, if noise in the system has corruptedthe data, it may show up as an incorrect MAC symbol or theCBM can report a BAD SIGNAL symbol if an incorrectcombination of ND symbols is detected (ND2 without anND1, ND2 followed by ND2, etc.)1.4 SYSTEM CONFIGURATIONFigure 1–5 illustrates the CBM and peripheral circuitryrequired for an IEEE 802.4 carrierband 5 Mbps or 10 Mbpsdata rate phase–coherent FSK physical layer. The CBMcommunicates with the MAC or TBC through a TTLcompatible serial interface that is consistent with the IEEE802.4 exposed DTE–DCE interface. Management andtransmission symbol requests are accepted via the CBMphysical data request channel (TXSYM0–TXSYM2,SMREQ*, and TXCLK). The physical data indicationchannel (RXSYM0–RXSYM2, SMIND*, and RXCLK) isused to send received symbols and management responsesto the MAC.The periphery circuitry is primarily associated withinterface to the LAN coaxial cable and data recovery. Anexternal crystal or clock source is required (20 MHz for 5Mbps data rate or 40 MHz for 10 Mbps data rate) for onboardtiming and transmit clock. Also, an RC timing network setsthe jabber timeout period.The coaxial cable interface combines the transmit andreceive signal functions. For transmission, the CBM providesdifferential drive signals (TXOUT and TXOUT*) whosesignaling is ECL levels referenced to VCC (logic high+4.1 V, logic low + 3.3 V) and a gate signal called TXDIS.The IEEE 802.4 standard puts specific requirements on thesignal transmitted to the cable:Between +63 dB and +66 dB (1.0 mV, 75 Ω) [dBmV]output voltage level.Transmitter–off leakage not to exceed –20 dB(1.0 mV, 75 Ω) [dBmV].Signal transition time window (eye pattern)dependent on data rate.Because of this, an external amplifier with waveshapingis required. The CBM TXOUT/TXOUT* outputs providecomplementary signals with virtually no slew, and theTXDIS is an enable signal helpful for turning the externalamp off “hard” to meet the low level leakage.http://onsemi.com440

MC68194On the reception side, the CBM requires a pre–amplifierto receive the low level signal from the cable. The signalavailable at the “F”–connector can range from +10 dB to +66dB (1.0 mV, 75 Ω) [dBmV]. The signal required at the CBMis about 12 dB above this (net gain through the transformer,pre–amp, and any filtering). The receiver can be used in fulldifferential or single–ended mode.A second part of the receiver function is the signal detector carrier detect function. The IEEE 802.4 requires that thereceiver detect a signal of +10 dBmV or above (i.e., beturned “on”) and report Silence for a signal of +4.0 dBmVRESETor below (i.e., be turned “off”). Therefore, a 6.0 dB (2:1voltage ratio) range or window is defined in which the signaldetect must switch. The CBM is optimized for this range(including the pre–amp gain), although it is trimmed via anexternal THRESHOLD.The remaining external components are associated withclock recovery. A capacitor and resistor (internal R alsoprovided) set one–shot timing, and an active filter for a PLLused in clock and data recovery is required. The active filtercan be implemented via an op amp, or if 5.0 volt operationis required, an alternate charge pump design can be used.TXDISAMPLIFICATIONANDWAVESHAPINGSMREQ*TXSYM2TXSYM1TXSYM0TXCLKXTAL1XTAL2SMIND*RXSYM2RXSYM1RXSYM0EOTDIS*RXCLKSERIALINTERFACEDECODERBUFFERCLOCKGENERATORSM MODEOUTPUTMUXBUFFERDATA COMMANDSSTATIONMANAGEMENTCOMMANDSPHYSICALMANAGEMENTRECEIVEDEMODULATORLOOPBACKTRANSMITMODULATORRECEIVEMUXONE SHOTBUFFERJABBERCONTROLRECEIVEAMPLIFIERAND SQUELCHCARRIERDETECTCLOCKRECOVERYANDSYNCHRONIZEJABFDBK*RXINRXIN*TXOUTTXOUT*JAB–RCV CCFDBKTHRESHOLDGAINCARDETRECEIVEPRE–AMPF–CONNECTORCPWRPWVCM–C1D* U* VCX+5 VSET–PWPLLFILTERThe clock recovery and data decoder is a synchronousdesign which provides superior performance minimizingclock jitter.Although primarily intended for the IEEE 802.4 carrierband, the CBM is also an excellent device for point–to–pointFigure 1–5. Functional Block Diagramdata links, fiberoptic modems, and proprietary LANs. TheMC68194 can be used over a wide range of frequencies andinterfaces easily into different kinds of media.http://onsemi.com441

MC68194SECTION 2SIGNAL DESCRIPTIONSymbol Type Name/DescriptionTXSYM0–TXSYM2 TTL/I* TRANSMIT SYMBOLS — These TTL inputs are request channel signals used to sendeither serial transmission symbols in the MAC mode or commands in stationmanagement mode. They are synchronized to TXCLK and are normally connected tothe TXSYMX outputs of the MC68824. SMREQ* selects the meaning of these signalsas either MAC mode or management mode.SMREQ* TTL/I* STATION MANAGEMENT REQUEST — A TTL input that selects the mode of therequest channel signals TXSYMX. Synchronized to TXCLK, SMREQ* is equal to onefor MAC mode and equal to zero for management mode. It is normally driven by theSMREQ* output of the MC68824.TXCLK TTL/O TRANSMIT CLOCK — A TTL clock output generated from the crystal oscillator (it is 1/4of the oscillator frequency) used to receive request channel symbols from the MC68824.TXCLK is equal to the data rate of the application (5.0 MHz or 10 MHz for IEEE 802.4).TXSYMX and SMREQ* are synchronized to the positive edge of TXCLK which issupplied to the MC68824.RXSYM0–RXSYM2 TTL/O RECEIVE SYMBOLS — These TTL outputs are indication channel signals used toprovide either serial receive symbols in MAC mode or command confirmation/indicationin station management mode. They are synchronized to RXCLK and are normallyconnected to the RXSYMX inputs of the MC68824. SMIND* selects the meaning ofthese signals as either MAC mode or management mode.SMIND* TTL/O STATION MANAGEMENT INDICATION — A TTL output that indicates the mode of theCBM and RXSYMX lines. Synchronized to RXCLK, SMIND* is equal to one for MACmode and equal to zero for management mode. It is normally connected to the SMIND*input of the MC68824.RXCLK TTL/O RECEIVE CLOCK — A TTL clock output used to send indication channel symbols tothe MC68824. Its frequency is nominally equal to the data rate (5.0 MHz or 10 MHz forIEEE 802.4). RXCLK is generated from a PLL that is locked to the local oscillator duringloopback, station management, or the absence of received data. During frame receptionthe PLL is locked to the incoming received data. RXSYMX and SMIND* aresynchronized to negative edge of RXCLK.EOTDIS* TTL/I* END–OF–TRANSMISSION DISABLE — When low, this TTL input disables theend–of–transmission receiver blanking required by the IEEE 802.4 Spec, Section12.7.6.3. When high the blanking works in accordance with the spec requirements.TXOUT,TXOUT* ECL/O TRANSMIT OUTPUTS — A differential output signal pair (MECL level referenced toVCC) used to drive the transmitter circuitry. The silence or “off” state is both outputs one(high). The output data stream is phase–coherent FSK encoded.TXDIS OC TRANSMIT DISABLE — An open collector output used to disable transmitter circuitry.This output is high when the transmitter is off (TXOUT and TXOUT* both high).JAB TTL/O JABBER — A TTL output signal generated from the jabber–inhibit timer. When equalto one, JAB indicates the timer has timed–out and an error has occurred.RESET TTL/I* RESET — A TTL input signal that when high asynchronously resets the CBM.*All TTL inputs include a 15 kΩ pullup resistor to VCC.http://onsemi.com442

MC68194Signal Description (Cont.)Symbol Type Name/DescriptionRXIN, RXIN* I RECEIVER INPUTS — A differential input signal pair for the receiver amplifier/limiter.These inputs may be used differentially or single ended.FDBK, FDBK*DC FEEDBACK BYPASS — These two points are provided to bypass dc feedbackaround the receiver amplifier.THRESHOLD I THRESHOLD ADJUST — The receiver threshold detect is trimmed with this pin.GAIN O GAIN — This output can be used to monitor the receiver amplifier output signal. Usedonly for test purposes.CARDET O CARRIER DETECT — This output can be used to filter the internal signal that issampled to sense carrier detect.RPW, CPW I PULSE–WIDTH RESISTOR/CAPACITOR — A resistor and capacitor set a one–shotpulse width used in the clock recovery circuitry.SET–PW O PULSE WIDTH TEST POINT — Output test point used for adjusting clock recoveryone–shot pulse width.UP*, DOWN* ECL/O PLL PHASE DETECTOR OUTPUTS — UP* and DOWN* are the pump–up andpump–down outputs, respectively, of the PLL digital phase detector. They are MECLlevels referenced to +5.0 volts and are used to drive inputs to an active filter or chargepump for the PLL.VCX I VCM CONTROL — The control voltage applied to the PLL voltage controlledmultivibrator.VCM–C1, VCM–C2 I VCM CAPACITOR — VCM capacitor inputs. VCM frequency is 4X RXCLK.JAB–RC I JABBER–INHIBIT RC — A resistor–capacitor network connected to this pin sets thejabber–inhibit time constant.XTAL,1 XTAL2 I CLOCK CRYSTAL — Oscillator circuit inputs may be used with a crystal or an externalclock source. Oscillator frequency is 4X data rate.VCC–VCMVCM POWER — 5.0 ± 5% volts for VCM.VCC–TXOUTTXOUT POWER — 5.0 ± 5% volts for TXOUT/TXOUT*.VCC–OSCOSCILLATOR POWER — 5.0 ± 5% volts for oscillator.VCC–RCVRECEIVER POWER — 5.0 ± 5% volts for receiver amplifier/limiter.VCCLOGIC POWER — 5.0 ± 5% volts for remaining logic.VCC–TTLTTL POWER — 5.0 ± 5% volts for TTL output buffers.GND–TTL, GND–VCM,GND–LOGIC, GND–OSC,GND–RCV, GND–SUBS, GNDGROUND — Reference voltage for TTL buffers, VCM, internal logic, oscillator, receiver/limiter, substrate respectively. Two additional grounds are used to isolate signals.http://onsemi.com443

MC68194SECTION 3TRANSMITTER3.1 OVERVIEWThe transmitter function includes the serial interfacedecoder, transmit modulator, transmit buffer, jabber inhibit,and clock generator. (Although the clock generator is notused exclusively by the transmit function, the generator willbe discussed here.) The MC68194 receives request channelsymbols on the TXSYMX pins which are synchronized toTXCLK. As is described in the Serial Interface discussion,MAC transmit symbols are input serially (CBM in MACmode), decoded, and used to modulate an output signal. TheSerial Interface Decoder is used both for MAC mode todecode data transmit commands (symbols) andmanagement mode to decode management commands. Thedecoded transmit commands or symbols are used by theTransmit Modulator to generate phase–coherent signalingas discussed in the CBM General Description. The transmitbuffer receives the modulated signal and drives differentialoutput signals.The clock generator provides TXCLK and internal clocksof 2 times (2X) and 4 times (4X) TXCLK. The 4X clock isactually the oscillator frequency. These clocks are used toreceive the TX symbols and generate the modulated signal.3.2 TRANSMIT BUFFERThe modulated transmit data stream drives the TXOUTand TXOUT* pins of the MC68194. These pins arecomplementary outputs with closely matched edgetransitions. This is useful in helping meet the IEEE 802.4carrierband requirement for a transmit jitter of less than1% of the data rate. TXOUT and TXOUT* are generallyused to drive a differential amplifier which is used to achievethe necessary output level at the cable and meet the rise/falltime window (or “eye” pattern) of the IEEE 802.4. A thirdoutput called TXDIS is available to gate the amplifiercircuitry on or off.The TXTOUT and TXTOUT* have ECL levelsreferenced to VCC (Figure 3–1). Levels are typically 4.11 Vfor a high and 3.25 for a low. Pulldown resistors are requiredwith the outputs specified to drive a maximum load of 220Ω to ground reference.Operation of the transmit outputs is controlled in thefollowing manner:6. Management mode — The TX outputs are alwaysdisabled while the CBM is in management mode. Whenleaving management mode the TX outputs remaindisabled if a RESET command has been issued and anENABLE TRANSMITTER and DISABLELOOPBACK commands have not been issued.Resetting the CBM enables internal loopback anddisables the transmitter.7. MAC (data) mode — After leaving management mode,the CBM can function in internal loopback (for test) withthe transmitter disabled, out of loopback with transmitterdisabled (receive only), or in standard data mode with theTX outputs controlled by the modulator.TXDISVCC–TXOUTTXOUTTXOUT*RPRPTX AMPFigure 3–1. Transmitter Outputs8. Jabber inhibit activated — If the jabber inhibit fires, itforces the CBM into management mode and disables theTX outputs. This condition can only be cleared by a resetcondition.The TXDIS output is an open collector switched currentsource. TXDIS sinks a nominal 0.5 mA when theTXOUT/TXOUT* outputs are enabled. TXDIS is off orhigh impedance when the transmitter is disabled.The signaling on the TX outputs and TXDIS is shown inFigure 3–2. The “off” or silence condition is both TXOUToutputs high and TXDIS also high. The figure shows anexample of the signal pattern for both leaving and enteringa silence condition.SILENCETXDISTXOUTTXOUT*OFF101 ND1 ND2Figure 3–2. Transmitter Output Signaling1OFFhttp://onsemi.com444

MC681943.3 JABBER INHIBITThe jabber inhibit function prevents the transmitter fromtransmitting indefinitely. An external resistor and capacitorpair tied to the CBM JAB–RC pin set the maximum time thatthe transmitter is allowed to transmit. When transmission isattempted for a period longer than the specified time, thejabber inhibit function forces the transmitter to shut downand alerts the system that this has been done by generatinga PHYSICAL ERROR indication on the serial interfaceindication channel. The error indication is removed onlyafter a reset has occurred on the RESET pin or after a RESETcommand has been received on the station managementinterface. The ENABLE TRANSMITTER and DISABLELOOPBACK commands can then be used to re–enable thetransmitter outputs. While the PHYSICAL ERRORindication is present, the normally–low JAB pin of theMC68194 will be high. This TTL output may be used to turnoff external transmitter circuitry or an isolation relay.A block diagram of the jabber inhibit function is shown inFigure 3–3. When edges are present on the TXDATA line,the jabber capacitor is allowed to charge. When thetransmitter stops transmitting, the capacitor is discharged.The circuit looks for any edges in the previous 16 TXCLKsbefore deciding whether to charge or discharge thecapacitor. When the capacitor voltage reaches the referencethreshold, the comparator switches and the jabber output islatched. The jabber output is fed back internally and disablesthe transmitter. This signal is also brought out to the JAB pinfor use in disabling external transmitter circuitry.For the IEEE 802.4 spec, the jabber timeout must be 0.5sec ± 25%. An RC time constant of 265 millisec. will giveabout a 0.5 sec timeout. The maximum resistor size is 125kΩ. Components should be 10% tolerance or better.Common values are R = 120 kΩ and C = 2.2 µF.3.4 CLOCK GENERATORThe clock generator is used to generate all of the transmittiming, TXCLK, and internal CBM timing for stationmanagement and loopback. The generator consists of acrystal oscillator/buffer that drives 2 and 4 stages. Theoscillator frequency must be four times (4X) the serial datarate. As an example, the IEEE 802.4 5 Mbps carrier band(TXCLK = 5.0 MHz) requires an oscillator frequency of 20MHz. The basic circuit is a single transistor Colpittsoscillator as shown in Figure 3–4.The oscillator is used in one of three modes depending onthe data rate and the application:1. With a parallel–resonant, fundamental mode crystal.2. With a parallel–resonant, overtone mode crystal.3. With an external clock source.The fundamental mode can typically be used up tofrequencies of about 20 MHz; this is crystal dependent andsome crystal types can be used as high as 40 MHz. Beyondthe fundamental mode upper limit, an overtone mode crystalis used. An alternative to a crystal is an external clock sourcesuch as an integrated crystal clock to drive the CBM.3.4.1 Parallel–Resonant, Fundamental Mode CrystalFigure 3–4 shows the external crystal and capacitors C1and C2 used for fundamental mode operation. The crystalmust be parallel resonant with a maximum series resistanceof 30 Ω.This configuration is normally used for the IEEE 802.45 Mbps carrierband standard. The required transmitfrequency stability is ± 100 ppm (0.01%). It is suggested thata crystal with a total frequency tolerance (calibrationtolerance, temperature variation, plus aging) of ± 50 ppm to± 60 ppm be used. The remaining frequency budget isreserved for the CBM and other components overtemperature and power supply variation.The series combination of C1 and C2 should be equal tothe specified crystal load (typically 20 pF or 32 pF).Additionally, C1 and C2 should be large enough to swampout the CBM device capacitance. The XTAL1 inputcapacitance is typically 1.5 pF to 2.0 pF, and C1 should beat least an order of magnitude greater (C1 > 20 pF). Also, C1must be greater than the crystal load capacitance because ofthe series combination of C1 and C2. Generally the ratioC1:C2 is from 1:1 to 3:1.TXDATA+ 5 VDCLKRQVCCDCLKQR JABJAB RCPINC JAB+–+ 5VDCLKRQJAB PININTERNALJABBER INHIBITDELAYV REFPHYSICAL MANAGEMENTOR HARDWARE RESETTXCLK ONE OF 16Figure 3–3. Jabber Inhibit Block Diagramhttp://onsemi.com445

MC68194For a 20 pF crystal load:20 pF = C1C2/(C1 + C2)andC2 = 20 pF [C1/(C1 – 20 pF)]Typical values are C1 = 60 pF and C2 = 30 pF.It is suggested that best results will be had with closetolerance (5%) NPO ceramic capacitors — trimming shouldnot be required. If trimming is necessary, a third trimmingcapacitor C3 can be placed in series with the crystal.Capacitors C1 and C2 will have to be increased in valuebecause the crystal load now becomes C1 and C2 and C3 inseries. For help in designing the capacitor network the useris directed to Design of Crystal and Other HarmonicOscillators, B. Parzen, Wiley, 1983.3.4.2 Parallel–Resonant, Overtone Mode CrystalFigure 3–4 also shows the network used for overtonemode operation. The crystal is still parallel resonant, butmust be specified for overtone (harmonic) operation at thedesired frequency. A low series resistance of less than 30 Ωis recommended.OVERTONEXTALL1C3C1C2FUNDAMENTALFigure 3–4. Crystal Oscillator Schematic ShowsConfigurations For Both Overtone andFundamental ModesC1C2XTAL1XTAL2GND–OSCVCC–OSC20 kΩ20 kΩCBMQ1TOBUFFER800 µAoperating frequency the tank circuit impedance will appearcapacitive; therefore, the load to the crystal is C1 in serieswith the capacitive reactance of the tank circuit.This series combination should be equal to the desiredcrystal load. Typically, C2 will increase in value ascompared to the fundamental mode situation because of thecancelling effects of L1. Again the user is directed to theabove reference for optimum selection of components.3.4.3 External Clock SourceFigure 3–5 shows the connection used for a TTLcompatible external clock source. XTAL1 and XTAL2 aretied together defeating transistor Q1. External resistor R1 =2.0 kΩ assures a high level greater than 3.0 V at an inputcurrent of 800 µA. The TTL driver must be capable ofsinking 2.5 mA.TTLCLOCKOSC2.5 mAVCCR1 = 2 kΩXTAL1XTAL2GND–OSCVCC–OSC20 kΩ20 kΩTOBUFFERFigure 3–5. TTL Compatible Clock Source DrivingCBMQ1CBM800 µAThe IEEE 802.4 for 5 Mbps or 10 Mbps data rate carrierband requires a transmit frequency stability of ± 100 ppm(0.01%). The external clock source must be specified for thisstability over temperature.Inductor L1 and capacitor C2 form a tank circuit that isparallel resonant at a frequency lower than the desiredcrystal harmonic but above the next lower odd harmonic. C3= 0.01 µF is a dc blocking capacitor to ground. At thehttp://onsemi.com446

MC68194SECTION 4RECEIVER AMPLIFIER/LIMITER WITH CARRIER DETECT4.1 OVERVIEWThe IEEE 802.4 spec provides that the incoming signalrange for good signal is +10 dB (1.0 mV, 75 Ω) [dBmV] to+66 dB (1.0 mV, 75 Ω) [dBmV] available at the modemconnector. The IEEE 802.4 further specifies that the modemwill report silence for any signal below +4.0 dB (1.0 mV, 75Ω) [dBmV]. Therefore, the receiver function must amplifyany signal of +10 dBmV and above to limiting for good datarecovery, and the signal detect must switch within the +4.0dBmV to +10 dBmV window, that is, it must be “off” for+4.0 dBmV and below, and be “on” for +10 dBmV andabove. The MC68194 requires a pre–amplifier of about 12dB in front of the onboard amplifier and carrier detectfunction. Clock and data recovery are extracted from theamplified/limited incoming signal, and the carrier detect isused to control the clock and data recovery function basedon presence of good signal.4.2 AMPLIFIERFigure 4–1 shows a simple block diagram of the receiveramplifier. Internally, dc feedback is used to bias theamplifier, and connection points FDBK and FDBK* areprovided to ac bypass the feedback. With both receiverinputs RXIN and RXIN* available, the device can be wiredeither for differential or single–ended operation.Differential is preferred for low noise.FDBKRRGAINAn external preamplifier with gain of about 12 dB is usedwith the onboard amplifier. The pre–amp can drive the CBMeither single–ended or differentially. The onboard amplifieroutput signal is used in two ways. One path adds anadditional limiter stage and is used to drive the clock anddata recovery stages. The second path is used to developcarrier detect.In the signal window where carrier detect must be active,the internal amplifier remains in the linear (non–limiting)range. Its output is fullwave rectified, and the rectified signalis compared to an onboard threshold that is temperature andvoltage compensated. The rectified signal is also brought outto an external lead called CARDET. A capacitor can beadded at this pin which combines with the series 125 Ωresistor to form a low pass filter. This filtering is used toknock any high frequency noise off of the signal. The outputof the comparator is a series of pulses (when the signalamplitude is sufficiently large) which are digitallyintegrated in the internal squelch signal.4.3 CARRIER DETECTION THRESHOLDThe carrier detect threshold is internally generated andcompensated for power supply and temperature variation.The THRESHOLD pin is provided to adjust the thresholdvia an external resistor tied to VCC.ORNORTO RXMUXRXIN*RXINRR125 ΩVthCARDETCARDETSTO SQUELCHFDBK*R = 7.5 kΩ (ALL RESISTORS OF EQUAL VALUE).CARDETTHRESHOLDVCC(A) Receiver Used in Differential ModeGAINPRE–AMPFDBKRTRXIN*RXINRRRR125 ΩVthORNORCARDETCARDETSTO RXMUXTO SQUELCHFDBK*R = 7.5 kΩ (ALL RESISTORS OF EQUAL VALUE).CARDETTHRESHOLDVCC(B) Receiver Used in Single–Ended ModeFigure 4–1. Receiver Amplifier With Carrier Detecthttp://onsemi.com447

5.1 OVERVIEWThe clock recovery circuitry is a key part of the receivefunction providing RX clock, a 2 times (2X) RX clock, anda 4 times (4X) RX clock for data recovery and to sendreceive symbols to the MAC. Figure 5–1 is a simplifiedfunctional schematic of the clock recovery logic. The clockrecovery is fed by the output stage of the receive amplifier.The phase–coherent signal contains frequency componentsequal to 1X and 2X the serial data rate. Figure 5–2 shows anexample of timing for a 5 Mb/s serial data rate. The RXOUTsignal drives a one–shot with a time period of 75% of 1/2 bittime; this locks out edges caused by the higher frequencycomponent. The one–shot is non–retriggerable and istriggered on both positive and negative going edges. Thisproduces a pulse for every edge of the lower frequency.The output of the one–shot is divided by 2 to produce a50% duty cycle signal equal in frequency to the lowerfrequency of the phase–coherent signal. In turn, the 2flip–flop output runs through a multiplexer to aphase–locked loop (PLL) system. The multiplexer selectsthe RXOUT signal when carrier detect is present; otherwisethe local oscillator divided by 4 is selected.The PLL system consists of a digital phase detector, anactive loop filter, a voltage–controlled multivibrator(VCM), and a divide–by–4 feedback counter. When in phaselock, the output of the divide–by–4 feedback counter islocked to the reference clock. In turn, the VCM 4 times clockis also aligned with the reference clock as shown in Figure5–2.The 4 times clock from the VCM, the 2 times clock, andthe 1 times clock are all in phase (when the PLL isphase–locked) with the reference clock, and are used to dodata recovery. Note that the reference clock can be 180° outof phase with the bit time boundaries (Figure 5–2). This doesnot affect the 2X and 4X clocks which are used to sample thedata. However, RXCLK can be out of sync with the bit timeboundaries and special circuitry in the data recovery logicdetects and corrects this condition.When no valid input signal is available from the receiveamplifier (carrier detect is not asserted), the multiplexerselects the local clock as a reference. This has the advantagesof:1. Supply a RXCLK when no data is present.2. Holding the PLL in frequency lock so that onlyphase–lock must be achieved when switching to the RXsignal.3. Providing a smooth transition for RXCLK when movingfrom the local oscillator (at the beginning of a frame) andvice versa (at the end of a frame). The PLL acts as anintegrator.The IEEE 802.4 provides a PAD–IDLE or training signalat the beginning of any transmission. The PAD–IDLE forphase–coherent FSK is an alternating one and zero pattern,and the PLL is capable of being locked–in well within the 24MC68194SECTION 5 – CLOCK RECOVERYbit times (3 octets). The design goal is to be locked–in within12–16 bit times. Data recovered during this lockup time attheSELECTLOCALCBMOSC 4MUXRXOUT2X CLOCKRPWREXTDATARECOVERYONESHOT+ 5 VCPWCEXT2SET–PWPDD*4Figure 5–1. Clock Recovery LogicU*C1QVCM4X CLOCKVCM C2 VCXCVCMOPAMPACTIVE FILTERbeginning of a transmission can be invalid because the PLLclocks are not sync’ed. As a result the data recovery logicforces silence for 17–18 bit times after the carrier detectswitches the reference clock (via the multiplexer) at thebeginning of a received transmission.5.2 ONE–SHOTAs previously stated, the one–shot is used to lock out thetransitions due to the higher frequency component of thephase–coherent signal. The one–shot is non–retriggerableand fires off both edges of the incoming RXOUT signal. Thetime period should be set to 75% of half the bit time. As anexample, the 5 Mb/s data rate has a 200 nsec bit time and theone–shot period then has a period of 75 nsec.ND PAIRRXOUT75% OF 1/2BIT TIMEONE–SHOTREF CLK(2)*VCM(IN LOCK)(4X BIT RATE)“1”BIT TIME1/2“0” “1” “0” “ND1” “ND2”*NOTE: Ref clock can also be 180° out of phase with bit time.Figure 5–2. Clock Recovery Timing Signalshttp://onsemi.com448

MC68194Figure 5–3 shows the arrangement of the external timingcapacitor and resistor. The internal resistor RINT may beused with or without an external resistor. A test pin is alsoprovided (SET–PW) to monitor the pulse width.For 5 Mbps operation, typically RPW = 1.5 kΩ and CPW= 33 pF.NEEDEDONLYFORTESTCBMRINT = 300 ΩSET–PW(TP)PWRPWREXT600 mVCPWCEXTFigure 5–3. One–Shot Timing Components+ 5 V5.3 PHASE–LOCKED LOOP (PLL) COMPONENTSThe PLL consists of a digital phase detector (PD), anactive loop filter, a VCM, and a divide–by–4 feedback path.Figure 5–4 shows the fundamental elements of the PLL withtheir gain constants. The basic PLL allows the outputfrequency ƒo to be “locked–on” to the input frequency ƒiwith a fixed phase relationship and to track it in frequency.When “in lock” the inputs to the phase detector have zerophase error. The input frequency is referenced to ƒo/4.A PLL follows classic servo theory and equations. In thefollowing discussion a working knowledge of a PLL isassumed. For more background and applicationsinformation on PLL, the user is directed to MotorolaApplication Note AN535.∅i(s)∅o(s)/4ƒo /4PHASEDETECTORKp∅e(s)4KnFILTERKƒVCMKo∅o(s)∅e(s) = ( 1 / [ 1 + G(s) H(s)] ) ∅i(s)∅o(s) = ( G(s) / [ G(s) H(s)] ) ∅i(s)where:G(s) = Kp Kƒ Ko H(s) = Kn Kn = 1 / N = 1/4Reference: App Note AN535Figure 5–4. PLL Elements and Loop Equationsƒo5.3.1 Phase Detector (PD)The phase detector produces a voltage proportional to thephase difference between ∅i(s) and ∅o(s)/4. This voltageafter filtering is used as the control signal for the VCM. ThePD has pump–up UP* and pump–down DOWN* outputswith a typical 800 mV logic swing. UP* produces a low levelpulse equal in width to the amount of time the positive edgeof ∅i (REF CLOCK) leads the positive edge of ∅o/4(VCM/4). DOWN* produces a low level pulse equal inwidth to the amount of time the positive edge of ∅i lags∅o/4. Both pulses will not occur on the same clock cycle as∅o/4 must either lead or lag ∅i when the PLL is out of lock.When in–lock, both outputs produce a very narrow pulse ornegative spike.The gain of the phase detector is equal to (reference appnote AN532A):Kp = (Logic swing)/2π = 800 mV/2π = 0.127 V/radian5.3.2 Voltage Controlled Multivibrator (VCM)The operating frequency range of the VCM is determinedby the capacitor tied to pins VCM–C1 and VCM–C2. Thecapacitor should be selected to put the desired operatingfrequency in the center of the VCM tuning range.The transfer function of the VCM is given by:Ko = Kv/swhere Kv is the sensitivity in radians per second per volt. Kvis found by:[(Upper frequency limit) – (Lower frequency limit)]2K v (Control voltage tuning range)then= 2π (ƒ)/VCX rad/s/VKo = 2π (ƒ)/(VCX)s rad/s/V5.3.3 Loop FilterSince a Type 2 system is required (phase coherent output,see reference AN535), the loop transfer function of Figure5–4 takes the form:G(s) H(s) = [K (s+a)] / s2Writing the loop transfer function (from Figure 5–4) andrelating it to the above form:G(s) H(s) = [KpKvKnKƒ] / s = [K (s+a)] / s2Having determined Kp, Ko, and that Kn = 1/4 then Kƒ(filter transfer function) must take the form:Kƒ = (s+a) / sAn active filter of the form shown in Figure 5–5A givesthe desired results, where:Kƒ = (R2 C s+1) / R1 C s (for large A)The active filter can also be implemented as shown inFigure 5–5B using an alternate approach of a charge pump.The advantage of the charge pump design is that it can beimplemented using only a single 5.0 volt supply. Its transferfunction is:http://onsemi.com449

MC68194UP*DN*Kƒ = (RC s +1) / C sRPULLDOWNFigure 5–5A. Active Filter Using Op AmpVCCR1RPULLDOWNMPSH81R1FILTER23R2CUP*CLOWPASSRR2–A+CVDD74CVCX6RLOWPASSMPSH81MPS2369VCXCLOWPASSDN5.3.4 Loop CharacteristicsIf an active filter as shown with an op amp is used, thegeneral PLL loop transfer function now becomes:G(s) H(s) = Kp Kƒ Ko Kn= Kp [(R2 C s+1) / R1 C s] (Kv/s) (1 / N)Its characteristic equation is set to the form:C.E. = 1 + G(s) H(s) = 0= s2 + (Kp Kv R2) s / (R1 N) + Kp Kv) / (R1 C N)Relating to the standard form (s2 + 2ξωns + ωn2) andsolving:ωn 2 = (Kp Kv) / R1 C N 2ξωn = (Kp KvR2) / R1 Nwhereωn = Natural frequencyξ = damping factor.If a change pump loop filter is used, the general PLL looptransfer function alternately becomes:G(s) H(s) = Kƒ Ko Kn= Kp[(R C s + 1) / C s] (Kv / s) (1 / N)Its characteristics equation is set to the form:C.E. = 1 + (Gs) (Hs) = 0= s2 + (Kp Kv R) s / (N) + (Kp Kv) / (C N)Relating to the standard form (s2 + 2ξωns + ωn 2 ) andsolving:ωn 2 = (Kp Kv) / C N 2ξωn = (Kp Kv R) / NFigure 5–5B. Charge Pump/FilterSECTION 6 – DATA RECOVERY6.1 OVERVIEWThe RXOUT signal from the receive amplifier and clocksgenerated by the clock recovery logic are used by the datarecovery logic. The MC68194 recovers the data from theencoded receive signal by opening sampling windowsaround the 1/4 and 3/4 bit time positions and looking foredges in the received signal (refer to Figure 6–1 for theencoded data representations). A data ONE has transitionsonly at the 0 and 1/2 bit time positions. A data ZERO hastransitions at the 0, 1/4, 1/2, and 3/4 bit time positions. ANON–DATA symbol has transitions at the 0, 1/4, and 1/2 bittime positions (ND1) or at the 0, 1/2, and 3/4 bit timepositions (ND2). NON–DATA symbols should alwaysoccur in pairs; each pair is made up of one of each type ofNON–DATA encoded symbols as shown in Figure 6–2(ND1 followed by ND2).BIT TIME0.50 0.25 0.75ONEZEROND1ND2Figure 6–1. Encoded Data RepresentationONEs, ZEROs, and NON–DATA pairs can be easilydecoded by keeping track of the 1/4 and 3/4 bit time positiontransitions. The ONEs, ZEROs, and NON–DATA pairs arethen reported on the RXSYMX pins as described in the serialinterface discussion. Two other conditions can also bereported while receiving in MAC mode — BAD SIGNALand SILENCE. BAD SIGNAL is reported when a ND1symbol is not followed immediately by a ND2 symbol orwhen a ND2 symbol is received and not immediatelypreceded by a ND1 symbol.SILENCE is reported when one of four conditions occurs:1. When the amplitude of the received signal is not largeenough to trigger the on–chip carrier detect circuit.Reporting SILENCE when the carrier detect signal is notasserted prevents the chip from responding to low levelnoise.2. When in internal loopback mode and SILENCE is beingrequested on the TXSYMX pins, SILENCE will bereported on the RXSYMX pins. An internal digitalcarrier detect is used during loopback and this signal isnegated when SILENCE is requested on the requestchannel.3. During the PLL training period at the beginning of atransmission. When an incoming signal first triggers thehttp://onsemi.com450

MC68194carrier detect in the amplifier, the PLL must lock to thenew reference clock (generated from the data stream).During the lockup time, recovered data may not be valid.The data recovery logic forces SILENCE for a fixedperiod of time (17–18 bit times).4. During end–of–transmission blanking. See Section 6.2.The PAD–IDLE at the beginning of a transmission is usedas a training signal as described in the clock recoverysection. After the PLL has achieved lock, the recoveredclock at this point may be in phase or 180° out of phase withthe bit time clock at the sending end. This creates a problemfor RXCLK and the data recovery logic because symbolswould be decoded as the wrong combination of 1/2 bit timetransitions.Logic in the data recovery circuitry corrects for thissituation. If the clock is 180° out of phase, the PAD–IDLEsequence (ONE, ZERO, ONE, ZERO, ONE, ...) will bedecoded as a sequence of NON–DATA symbols. Refer toFigure 6–2. In normal data reception, NON–DATA symbolsoccur only in pairs; there are never three or more in a row.Therefore, three or more NON–DATA symbols occurring ina row indicate that the bit time clock is 180° out of phase andthe bit time clock (RXCLK) must be slipped as shown inFigure 6–3. The clock frequency and phase have now beenrecovered and symbol decode proceeds as described below.6.2 RECEIVER END–OF–TRANSMISSION BLANKINGThe IEEE 802.4 requires that the physical layer recognizethe end of a transmission and report silence to the MAC fora period thereafter. This period of silence is referred to asblanking and must meet the following conditions:1. Blanking must begin no later than 4 MAC–symbol timesafter the last MAC–symbol of the End Delimiter (i.e., thelast End Delimiter of the transmission).2. Blanking must continue to a point at least 24MAC–symbol times but not more than 32 MAC–symboltimes from the last MAC–symbol of the End Delimiter.The MC68194 provides this function by recognizing thelast End Delimiter of a transmission (I Bit = 0, see Section1.3). The CBM reports silence for 32 symbols after the lastsymbol of the End Delimiter.The blanking function can be disabled for test purposes ornon–IEEE 802.4 applications via the EOTDIS* input.GPAD–IDLESEQUENCEBIT TIMECLOCK INPHASEONEZEROONEZEROBIT TIMECLOCK 180°OUT OFPHASEND2ND1ND2Figure 6.2 Training Sequence Decoded WithIn–Phase and Out–Of Phase ClocksBIT TIMERECEIVEDSIGNALND2ND1 ND2 ND1 ZEROONEZEROONEZERONON DATAINDICATORDATACLOCKCLOCK SLIPPED1/2 BIT TIMEFigure 6–3. Clock Slip To Bring In Phase WithData Streamhttp://onsemi.com451

7.1 OVERVIEWThe serial interface is composed of the Physical DataRequest Channel and the Physical Data Indication Channel.The serial interface is used to pass commands and dataframes to and from the CBM.7.2 PHYSICAL DATA REQUEST CHANNELFive signals comprise the physical data request channel.Three of these signals (TXSYM2, TXSYM1 and TXSYM0)are multiplexed and have different meanings depending onthe mode of SMREQ*. When SMREQ* is equal to one, theMAC mode is selected. When SMREQ* is equal to zero, thephysical layer management mode is selected.7.2.1 TXCLK — Transmit ClockThe transmit clock can be from 1.0 to 10 MHz. TXSYM2,TXSYM1, TXSYM0 and SMREQ* are synchronized toTXCLK. The IEEE 802.4 standard for carrier band allowsfor 5.0 or 10 MHz clocks.7.2.2 SMREQ* — Station Management RequestSMREQ* directs the physical layer to be in MAC orphysical layer management mode. In MAC mode SMREQ*= 1 and in management mode SMREQ* = 0.7.2.3 TXSYM0, TXSYM1, and TXSYM2 — TransmitSymbolsIn physical layer management mode TXSYM2,TXSYM1 and TXSYM0 have the meanings shown inFigure 7–1.State TXSYM2 TXSYM1 TXSYM0RESETDISABLE LOOPBACKENABLE TRANSMITTERSERIAL SM DATA/IDLE1100MC68194SECTION 7 – SERIAL INTERFACE7.3 PHYSICAL DATA INDICATION CHANNEL10101110/1Figure 7–1. Request Channel Encoding for PhysicalManagement Mode (SMREQ* = 0)The CBM supports only four station managementcommands (RESET, LOOPBACK DISABLE, ENABLETRANSMITTER and IDLE) encoded on lines TXSYM2,TXSYM1 and TXSYM0. The CBM does not support theSMDATA commands, but responds with a “NACK”. InMAC mode, the encoding for TXSYM2, TXSYM1, andTXSYM0 are shown in Figure 7–2.Symbol TXSYM2 TXSYM1 TXSYM0ZEROONENON–DATAPAD–IDLESILENCEWhere:ZERO is binary zero.ONE is binary one.NON–DATA is a delimiter flag and is always present in pairs.PAD–IDLE is one symbol of preamble/interframe idle.SILENCE is silence or no signal.Figure 7–2. Request Channel Encoding For MAC Mode(SMREQ* = 1)001010001101XXXFive signals comprise the physical data indicationchannel. Three of these signals (RXSYM2, RXSYM1 andRXSYM0) are multiplexed and have different meaningsdepending on the state of SMIND*. When SMIND* is equalto one, the physical layer is in MAC mode and whenSMIND* is equal to zero, the physical layer is inmanagement mode or an error has occurred.7.3.1 RCXLK — Receive ClockThe receive clock can be from 1.0 to 10 MHz. RXSYM2,RXSYM1, RXSYM0, and SMIND* are synchronized toRXCLK. The IEEE 802.4 standard for carrier bandnetworks allows 5.0 or 10 MHz clocks.7.3.2 SMIND* — Station Management IndicationSMIND* indicates whether the physical layer is in MACmode (SMIND* = 1) or management mode (SMIND* = 0)of operation. When in MAC mode of operation, the physicallayer has RXSYM2, RXSYM1, and RXSYM0 encodedindicating data reception. When in management mode ofoperation, the physical layer RXSYM2, RXSYM1 andRXSYM0 are encoded to confirm response to receivedcommands or to indicate a physical error (jabber inhibit).7.3.3 RXSYM0, RXSYM1 and RXSYM2 — ReceiveSymbolsThe encoding for RXSYM2, RXSYM1, and RXSYM0 inphysical management mode is shown in Figure 7–3:State RXSYM2 RXSYM1 RXSYM0NACK (non–acknowledgement)ACK (acknowledgement)IDLEPhysical Layer Error*Indicates RXSYM0 contains the SM RX data when responding to a serialdata command.Figure 7–3. Indication Channel Encoding For PhysicalManagement Mode (SMIND* = 0)The encoding of RXSYM2, RXSYM1, and RXSYM0 inMAC mode is shown in Figure 7–4.Symbol RXSYM2 RXSYM1 RXSYM0ZEROONENON–DATASILENCEBAD SIGNALWhere:ZERO is the received data zero.ONE is the received data one.NON–DATA is a delimiter flag and is always present in pairs.SILENCE is silence or no signal.BAD SIGNAL is received bad signal.X = Don’t care.Figure 7–4. Indication Channel Encoding For MACMode (SMIND* = 1)001101001000110101**1101XXXhttp://onsemi.com452

MC68194SECTION 8PHYSICAL MANAGEMENT8.1 OVERVIEWThe MC68194 supports four physical managementcommands on the request channel: RESET, DISABLELOOPBACK, ENABLE TRANSMITTER, and IDLE. Theserial data station management commands are notimplemented in the MC68194. These unimplementedcommands are typically used to set up and read registers orcontrol bits within a more complex modem. The CBM doesnot have registers and does not require the SMDATAcommands. Upon reception of a SMDATA command, theCBM will respond with a NONACKNOWLEDGEMENT(NACK) and a response byte in accordance with the IEEEDTE–DCE Interface Standard. The data in the response byteis all ZEROs. Receipt of a RESET, DISABLE LOOPBACK,or ENABLE TRANSMITTER command will abort theSMDATA response.8.2 RESETThe RESET command performs the same function as theRESET pin; the internal loopback mode is enabled, thetransmitter outputs are disabled and TXDIS is enabled, andthe jabber inhibit timeout is cleared. In addition the RESETcommand will generate an ACKNOWLEDGEMENTresponse (ACK) on the RXSYMx pins.The RESET pin is an asynchronous function. When takenhigh it resets the CBM as described above leaving the CBMready to respond to the physical data request channel.NOTE: For the MC68194 to respond properly tocommands after a hardware reset, the request channel musteither be in MAC mode upon exiting the hardware reset orthe request channel must go to MAC mode briefly beforegoing to management mode. If the MC68194 is inmanagement mode upon exiting the hardware reset, itremains reset and does not recognize the command becauseit is waiting for a MAC mode to management modetransition. This situation can be corrected by either exitinghardware reset with the request channel in MAC mode orputting the request channel in MAC mode briefly beforeissuing any management commands. See Section 8.6 forcommand response timing.8.3 INTERNAL LOOPBACKThe internal loopback mode is provided for testing theCBM. In this mode a multiplexer selects the internaltransmitter signal to drive the clock recovery and datarecovery portions of the receive circuitry. This transmitsignal is taken just prior to the output buffer stages of thetransmitter circuit.The loopback mode can only be selected via RESET(management command or external pin). Loopback mode isexited upon receipt of the management commandDISABLE LOOPBACK. The CBM will respond with ACKto this command.A normal sequence of events to test the CBM then wouldbe:1. Initialize the CBM via a RESET command or hardwarereset.2. Return to MAC mode and send test data. The CBM is fullduplex.3. In management mode, send DISABLE LOOPBACKcommand to exit loopback.Following the test the modem can be setup for standardoperation.8.4 STANDARD OPERATIONStandard operation requires that the transmitter beenabled as well as disabling loopback. The transmitter isautomatically disabled on RESET. Three things musthappen after a RESET before transmissions can begin:1. Loopback mode must be exited with the DISABLELOOPBACK command. The MC68194 responds to thiscommand with the ACK management response.2. The transmitter must be activated with the ENABLETRANSMITTER command. The MC68194 responds tothis command with the ACK management response.3. The MC68194 must exit the management mode andenter the MAC data mode.The CBM is now ready to send and receive data, i.e., theCBM is in MAC or data mode, loopback is disabled, and thetransmitter is enabled.8.5 IDLEThe CBM provides the IDLE response when an IDLEmanagement command is received. In addition, the IDLEresponse is returned for all invalid, as opposed tounimple–mented (SMDATA) commands.8.6 COMMAND RESPONSE TIMINGThe MC68194’s management command/responseoperation is:1. ACK response to RESET, DISABLE LOOPBACK, andENABLE TRANSMITTER within 2 clock periods. Asshown in Figure 8–1, the precise response time dependson the relative phase of the TXCLK and the RXCLKsignals. If they are in phase, the response will beavailable at the RXSYMx pins 1.5 clocks after thecommand is latched. If the clocks are 180° out of phase,the delay will be 2 clocks. The command should be heldon the TXSYMX pins until the response is received onthe RXSYMX pins.2. The IDLE command and all invalid commands willproduce the IDLE response with the same delay asdescribed above.3. The SMDATA command response timing is shown inFigure 8–2. The NACK response to the SMDATAcommand is available on the RXSYMX pins in 2.5 or 3http://onsemi.com453

MC68194clock periods depending on the relative phases of theTXCLK and RXCLK signals. When NACK becomesvalid, RXSYM0 is low creating a start bit for theresponse byte. NACK is held for 9 clock periods withRXSYM0 low (start bit plus 8 ZERO data bits). NACKis held for one additional clock with RXSYM0 high. Thisis the stop bit and mark the end of the SMDATA responsebyte. 12.5 or 13 clock periods after receiving theSMDATA command the NACK response is removed.In management mode, RXCLK is always locked toTXCLK. These clocks may be in phase or 180° out of phaseas discussed above. This uncertainty exists because theclock recovery PLL can lock to either phase of the localclock. The response delays relative to TXCLK maytherefore differ by 1/2 clock period. The MC68194 mustleave management mode, enter MAC mode, and return tomanagement mode for a phase change to occur. The relativephase of the two clocks will not change while inmanagement mode.Because the clock recovery PLL requires a training periodwhen first entering management mode, the PLL must havesufficient time to lock to the new clock source (TXCLK)before being required to provide a response. To provideenough time for the PLL to lock up, the MC68194 delays16.5 to 17 clock periods before entering station managementmode (SMIND* = 0) after the station management mode isselected (SMREQ* = 0). Refer to Figure 8–3 for the timingdiagram. During this delay, the MAC mode SILENCEresponse will be present on the RXSYMX pins.Users must be aware that when first requestingmanagement mode there will be this added delay before themode is entered and a response is available. If a managementcommand is sent along with the station management moderequest (SMREQ* = 0) and held on the TXSYMX pins untilthe CBM enters station management mode, the properresponse will be available on the RXSYMX pinsimmediately except in the case of SMDATA commands.SMDATA commands must not be requested on theTXSYMX pins until after SMIND* indicates that stationmanagement mode has been entered.http://onsemi.com454

MC68194TXCLKTXSYMxVALID COMMANDRXCLK (1)IN PHASERESPONSE (1)RXSYMxRXCLK (2)OUT OF PHASERESPONSE (2)RXSYMxVALID RESPONSEVALID RESPONSEFigure 8–1. Parallel Command Response TimeTXCLKTXSYMxRXCLK (1)IN PHASERESPONSE (1)RXSYMxRXCLK (2)OUT OF PHASESTARTBITVALID SMDATA COMMANDVALID SMDATA RESPONSE8 ZERO DATA BITSSTOPBITRESPONSE (2)RXSYMxSTARTBITVALID SMDATA RESPONSE8 ZERO DATA BITSSTOPBITFigure 8–2. SMDATA Command Response TimeTXCLKSMREQ*RXCLK (1)IN PHASESMIND* (1)RXCLK (2)OUT OF PHASESMIND* (2)Figure 8–3. Station Management RequestResponse Timehttp://onsemi.com455

MC68194SECTION 9MC68194 CARRIER BAND MODEMELECTRICAL SPECIFICATIONSMAXIMUM RATINGS (Limits Beyond Which Device Life May Be Impaired)Characteristic Symbol Value UnitSupply Voltage VCC 0 to +7.0 VdcTTL Input Voltage VIN 0 to +5.5 VdcTTL Output Voltage (Applied to output HIGH) VOUT 0 to +5.5 VdcECL Output Source Current Iout 50 mAdcStorage TemperatureTstg –55 to +165 °CCerquadJunction TemperatureCerquadTJ 165 °CGUARANTEED OPERATING RANGESValueCharacteristic Symbol Min Typ Max UnitSupply Voltage VCC 4.75 5.0 5.25 VdcOperating Temperature (Cerquad in still air) TA 0 25 70 °CDC ELECTRICAL CHARACTERISTICSLimitsCharacteristic Symbol Min Typ Max Unit Test ConditionsTTL INPUTS (TXSYM0–TXSYM2, SMREQ*, RESET, EOTDIS)†(TA = 0–70°C, VCC = 5.0 Vdc 5%)Input HIGH Voltage VIH 2.0 VdcInput LOW Voltage VIL 0.8 VdcInput HIGH Current IIH 20 µA VCC = MAX, VIN = 2.7 VdcInput LOW Current IIL –0.7 mA VCC = MAX, VIN = 0.4 Vdc†All TTL inputs include a 15 k–ohm pullup resistor to V CC .TTL OUTPUTS (TXCLK, RXSYM0–RXSYM2, SMIND*, RXCLK, JAB)(TA = 0–70°C, VCC = 5.0 Vdc 5%)Output HIGH Voltage VOH 2.7 Vdc VCC = MIN, IOH = MAXOutput LOW Voltage VOL 0.5 Vdc VCC = MIN, IOL = MAXOutput HIGH Current IOH –0.4 mAOutput LOW Current IOL 8.0 mAECL OUTPUTS (TXOUT, TXOUT*)(TA = 25°C, VCC = 5.0 Vdc)Output HIGH Voltage VOH 4.10 Vdc Rpulldown = 220 ΩOutput LOW Voltage VOL 3.28 Vdc Rpulldown = 220 ΩOPEN COLLECTOR OUTPUT (TXDIS)(TA = 25°C, VCC = 5.0 Vdc)Output LOW Current IOL 450 550 µA VOL = 3.0 VdcOutput HIGH Leakage Current IOH 50 µA VOH = 5.0 VdcRECEIVER (SINGLE–ENDED OPERATION)GAIN Output Voltage HIGH GVOH 4.2 Vdc IOH = 5.0 mAGAIN Output Voltage LOW GVOL 3.6 Vdc IOL = 5.0 mAInput Signal (for limiting) RVIN +17 dBmV GAIN output = 600 mVDetected Threshold Vthres +18 dBmV RTHRES = 120 kΩ to VCCPHASE DETECTOR OUTPUTS (UP*, DOWN*)Phase Detector Output Voltage HIGH PDVOH 4.0 Vdc IOH = 10 mAPhase Detector Output Voltage LOW PDVOL 3.3 Vdc IOL = 10 mAhttp://onsemi.com456

MC68194DC ELECTRICAL CHARACTERISTICS (cont.)– OTHER PARAMETERS – (TA = 25°C, VCC = 5.0 Vdc)POWER SUPPLY DRAIN CURRENTLimitsCharacteristic Symbol Min Typ Max Unit Test ConditionsPower Supply Drain Current ICC 220 270 mA No outputs loaded, TTL inputsopen.VCMVCM Oscillator Fosc1 40 MHz Cvcm = 24 pF, RXCLK = 5.0 MHz,VCX = 3.6 VdcFrequency Fosc2 20 MHz Cvcm = 68 pF, RXCLK = 10 MHz,VCX = 3.6 VdcVCM Tuning Ratio TR 4.0VCX Tuning RangeVCX 2.6 4.6 VdcVCXONE–SHOTSET–PW Output Voltage HIGH PWVOH 4.2 Vdc IOH = 5.0 mASET–PW Output Voltage LOW PWVOL 3.6 Vdc IOL = 5.0 mATiming Current IT 0.8 4.0 mAInternal Resistor Rint 300 OhmsTiming Reference VoltageVref 1.2 1.3 1.4 Vdc IT = 0.8 mA(measured at RPW pin)External Timing Resistor REXT 1.5 kΩ For 5.0 Mb/s data rate.External Timing Capacitor CEXT 33 pF For 5.0 Mb/s data rate.JABBER TIMERRC Threshold High JABVIH 4.25 Vdc IIN = 5.0 µA MaxRC Output VOL JABVOL 0.4 Vdc IOL = 10 mAJabber Resistor RJAB 120 125 kΩ For 0.5 sec timingJabber Capacitor CJAB 2.2 µF For 0.5 sec timingCRYSTAL OSCILLATORInput HIGH Voltage VIH 3.0 Vdc XTAL1 & XTAL2 tied togetherInput LOW Voltage VIL 2.0 Vdc XTAL1 & XTAL2 tied togetherAC ELECTRICAL CHARACTERISTICS††(TA = 0–70°C, VCC = 5.0 Vdc 5%)LimitsCharacteristic Symbol Min Typ Max Unit Test ConditionsTXCLK Period tTXperiod 180 200 220 @ 5.0 MHz, Figure 9–1A.RXCLK Period tRXperiod 180 200 220 @ 5.0 MHz, PLL locked to TXCLK,Figure 9–1B.TTL Rise/Fall Time tTTL 4.0 ns Figure 9–1A.TXSYMX, SMREQ* Setup Time(to TXCLK)TXSYMX, SMREQ* Hold Time(to TXCLK)RXSYMX, SMIND* Delay Time(to RXCLK)tsetup 15 25 ns Figure 9–1A.thold –9.0 0 ns Figure 9–1A.tRXSYM delay 0 2.5 5.0 ns Figure 9–1B.XTAL1,2 to TXCLK Delay tTXCLK delay 18 ns Figure 9–1C. XTAL1 and XTAL2 tiedtogether and driven with externalsource.TXOUT, TXOUT* Rise/Fall Time tTXOUT 1.5 ns Rpulldown = 500 ΩUP*, DOWN* Rise/Fall Time tPD 1.5 ns Rpulldown = 500 ΩTXDIS Rise/Fall Time tTXDIS 35 ns 2.0 kΩ pullup to VCC. Do not useFigure 9–2 test load.†† See Figure 9–2 for AC test load.http://onsemi.com457

MC68194RXSYM0–RXSYM2,SMREQ*1.5 V 1.5 VtsetuptholdtTTL–tTTL+2.5 VTXCLK1.5 V0.5 V1.5 VtTX period(A) TXSYMX, SMREQ* Setup and Hold Timing to TXCLKRXSYM0–RXSYM2,SMIND*1.5 VtRXSYM delayRXCLK1.5 V1.5 VtRX period(B) RXSYMX, SMIND* Delay Timing to RXCLKXTAL1, XTAL22.5 V2.5 VtTXCLK delayTXCLK1.5 V(C) TXCLK Delay Timing to XTAL1, XTAL2Figure 9–1. AC Test WaveformsCBMTEST POINT15 pFINCLUDES JIG AND PROBECAPACITANCE500 ΩFigure 9–2. TTL, TXOUT, TXOUT*, Up* & Down* AC Test Loadhttp://onsemi.com458

MC681948002000860015006ns4002001000500RESISTORRXCLK FREQUENCY (MHz)42VCM FREQ(MHZ)Figure 9–3. One Shot Pulse Width versus Rext/Cext1000100001011100200CAP pF10 100CAPACITANCE (pF)3004.6 Vdc3.6 VdcFigure 9–5. VCM Frequency versus Capacitance8002.6 Vdc0400 11000THRESHOLD (dBmV)Figure 9–4. VCM Frequency versus Control Voltage(VCC = 5.0 Vdc & C = 68 pF)242322212019181716204023 4 5 6VCX (VOLTS)60 80 100 120 140 160 180RESISTOR (Kohm)200 220Figure 9–6. Detected Threshold versusThreshold Resistor600ms400R = 120 kΩ200001234TIMING CAP (µF)Figure 9–7. Jabber Time Constant versus Capacitancehttp://onsemi.com459

http://onsemi.com460CHAPTER 5Ordering Information

ON SemiconductorCircuit IdentifierTemperature Range• 10 = 10K (–30 to +85°C)• 10H = 10H (0 to +75°C)• 100H = 100K Compatible (0 to +85°C)MECL 10K, MECL 10H/100HMC WWW XXX YYPackage Type• P for Plastic• L for Ceramic• FN for PLCCFunction TypeON SemiconductorCircuit IdentifierMECL IIIMC XXXX YPackage Type• P for Plastic• L for Ceramic• D for Narrow SOIC• FN for PLCCFunction Typehttp://onsemi.com461

A letter suffix to the MECL logic function part number is used to specify the package style (see drawings below).See appropriate selector guide for specific packaging available for a given device type. SO–8D SUFFIXPLASTIC SOIC PACKAGECASE 751-05ISSUE M851 4-A--B-4X P0.25 (0.010) M B MNOTES:1. DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.-T-8X DKCSEATINGPLANE0.25 (0.010) M T B S A SMR X 45JFDIMABCDFGJKMPRMILLIMETERSMIN MAX4.80 5.003.80 4.001.35 1.750.35 0.490.40 1.25INCHESMIN MAX0.189 0.1960.150 0.1570.054 0.0680.014 0.0190.016 0.0491.27 BSC 0.050 BSC0.180.100°5.800.250.250.257°6.200.500.0070.0040°0.2290.0100.0090.0097°0.2440.019 -B--T-SEATINGPLANE14 81 7-A-CKCDIP–14L SUFFIXCERAMIC PACKAGECASE 632–08ISSUE YF G NMD 14 PLJ 14 PL0.25 (0.010) M T A S 0.25 (0.010) M T BLSNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4. DIMESNION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.DIMABCDFGJKLMNINCHESMIN MAX0.750 0.7850.245 0.2800.155 0.2000.015 0.0200.055 0.0650.100 BSC0.008 0.0150.125 0.1700.300 BSC0°0.02015°0.040MILLIMETERSMIN MAX19.05 19.946.23 7.113.94 5.080.39 0.501.40 1.652.54 BSC0.21 0.383.18 4.317.62 BSC0° 15°0.51 1.01http://onsemi.com462

(continued)14 81 7BPDIP–14P SUFFIXPLASTIC PACKAGECASE 646–06ISSUE LNOTES:1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUEPOSITION AT SEATING PLANE AT MAXIMUMMATERIAL CONDITION.2. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.3. DIMENSION B DOES NOT INCLUDE MOLDFLASH.4. ROUNDED CORNERS OPTIONAL.AFH G DNSEATINGPLANECKLMJDIMABCDFGHJKLMNINCHESMAX0.7700.2600.1850.0210.0700.100 BSCMIN0.7150.2400.1450.0150.0400.0520.0080.1150.0950.0150.1350.300 BSC0°0.01510°0.039MILLIMETERSMIN18.166.103.690.381.022.54 BSC1.320.202.927.62 BSC0°0.39MAX19.566.604.690.531.782.410.383.4310°1.01 –T–SEATINGPLANEFE–A–16 91 8GD 16 PL0.25 (0.010) M TN–B–ASCCDIP–16L SUFFIXCERAMIC DIP PACKAGECASE 620–10ISSUE VKLMJ 16 PL0.25 (0.010) M TBSNOTES:1. DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4. DIMENSION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.750 0.785 19.05 19.93B 0.240 0.295 6.10 7.49C ––– 0.200 ––– 5.08D 0.015 0.020 0.39 0.50E 0.050 BSC 1.27 BSCF 0.055 0.065 1.40 1.65G 0.100 BSC 2.54 BSCH 0.008 0.015 0.21 0.38K 0.125 0.170 3.18 4.31L 0.300 BSC 7.62 BSCM 0 15 0 15N 0.020 0.040 0.51 1.01http://onsemi.com463

(continued)PDIP–16P SUFFIXPLASTIC DIP PACKAGECASE 648–08ISSUE R16H–A–1 8GF9D 16 PLBSCK0.25 (0.010) M TSEATING–T– PLANEAMJLMNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.740 0.770 18.80 19.55B 0.250 0.270 6.35 6.85C 0.145 0.175 3.69 4.44D 0.015 0.021 0.39 0.53F 0.040 0.70 1.02 1.77G 0.100 BSC 2.54 BSCH 0.050 BSC 1.27 BSCJ 0.008 0.015 0.21 0.38K 0.110 0.130 2.80 3.30L 0.295 0.305 7.50 7.74M 0 10 0 10S 0.020 0.040 0.51 1.01SO–16D SUFFIXPLASTIC SOIC PACKAGECASE 751B–05ISSUE J–T–SEATINGPLANE16 91 8G–A–K–B–D 16 PL0.25 (0.010) M T B S A SP 8 PL0.25 (0.010) M B SCMR X 45JFNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERS INCHESDIM MIN MAX MIN MAXA 9.80 10.00 0.386 0.393B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7P 5.80 6.20 0.229 0.244R 0.25 0.50 0.010 0.019http://onsemi.com464

CDIP–20L SUFFIXCERAMIC DIP PACKAGECASE 732–03ISSUE EH201 10FDASEATINGPLANE11GBCNKJLMNOTES:1. LEADS WITHIN 0.010 DIAMETER, TRUEPOSITION AT SEATING PLANE, AT MAXIMUMMATERIAL CONDITION.2. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.3. DIMENSIONS A AND B INCLUDE MENISCUS.INCHESDIM MIN MAXA 0.940 0.990B 0.260 0.295C 0.150 0.200D 0.015 0.022F 0.055 0.065G 0.100 BSCH 0.020 0.050J 0.008 0.012K 0.125 0.160L 0.300 BSCM 0 15N 0.010 0.040PDIP–20P SUFFIXPLASTIC DIP PACKAGECASE 738–03ISSUE E–T–SEATINGPLANE201GE–A–F1110NBKCD 20 PL0.25 (0.010) M T AMLMJ 20 PL0.25 (0.010) M TBMNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLDFLASH.INCHES MILLIMETERSDIM MIN MAX MIN MAXA 1.010 1.070 25.66 27.17B 0.240 0.260 6.10 6.60C 0.150 0.180 3.81 4.57D 0.015 0.022 0.39 0.55E 0.050 BSC 1.27 BSCF 0.050 0.070 1.27 1.77G 0.100 BSC 2.54 BSCJ 0.008 0.015 0.21 0.38K 0.110 0.140 2.80 3.55L 0.300 BSC 7.62 BSCM 0 15 0 15N 0.020 0.040 0.51 1.01http://onsemi.com465

(continued)PLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CB0.007 (0.180) M T L–M S N S–N–Y BRKU0.007 (0.180) M T L–M S N SD–L––M–ZW20 1DXG10.010 (0.250) S T L–M S N SVVIEW D–DA0.007 (0.180) M T L–M S N SZR0.007 (0.180) M T L–M S N SH0.007 (0.180) M T L–M S N SCEK1GG10.010 (0.250) S T L–M S N S0.004 (0.100)J –T– SEATINGPLANEVIEW SKVIEW SF0.007 (0.180) M T L–M S N SNOTES:1. DATUMS –L–, –M–, AND –N– DETERMINEDWHERE TOP OF LEAD SHOULDER EXITS PLASTICBODY AT MOLD PARTING LINE.2. DIMENSION G1, TRUE POSITION TO BEMEASURED AT DATUM –T–, SEATING PLANE.3. DIMENSIONS R AND U DO NOT INCLUDE MOLDFLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)PER SIDE.4. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.5. CONTROLLING DIMENSION: INCH.6. THE PACKAGE TOP MAY BE SMALLER THAN THEPACKAGE BOTTOM BY UP TO 0.012 (0.300).DIMENSIONS R AND U ARE DETERMINED AT THEOUTERMOST EXTREMES OF THE PLASTIC BODYEXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,GATE BURRS AND INTERLEAD FLASH, BUTINCLUDING ANY MISMATCH BETWEEN THE TOPAND BOTTOM OF THE PLASTIC BODY.7. DIMENSION H DOES NOT INCLUDE DAMBARPROTRUSION OR INTRUSION. THE DAMBARPROTRUSION(S) SHALL NOT CAUSE THE HDIMENSION TO BE GREATER THAN 0.037 (0.940).THE DAMBAR INTRUSION(S) SHALL NOT CAUSETHE H DIMENSION TO BE SMALLER THAN 0.025(0.635).INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.385 0.395 9.78 10.03B 0.385 0.395 9.78 10.03C 0.165 0.180 4.20 4.57E 0.090 0.110 2.29 2.79F 0.013 0.019 0.33 0.48G 0.050 BSC 1.27 BSCH 0.026 0.032 0.66 0.81J 0.020 ––– 0.51 –––K 0.025 ––– 0.64 –––R 0.350 0.356 8.89 9.04U 0.350 0.356 8.89 9.04V 0.042 0.048 1.07 1.21W 0.042 0.048 1.07 1.21X 0.042 0.056 1.07 1.42Y ––– 0.020 ––– 0.50Z 2 10 2 10G1 0.310 0.330 7.88 8.38K1 0.040 ––– 1.02 –––http://onsemi.com466

CDIP–24L SUFFIXCERAMIC DIP PACKAGECASE 758–02ISSUE ABLPD 24 PL241–A–GF1312NKC–T–JSEATINGPLANENOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.INCHES MILLIMETERSDIM MIN MAX MIN MAXA 1.240 1.285 31.50 32.64B 0.285 0.305 7.24 7.75C 0.160 0.200 4.07 5.08D 0.015 0.021 0.38 0.53F 0.045 0.062 1.14 1.57G 0.100 BSC 2.54 BSCJ 0.008 0.013 0.20 0.33K 0.100 0.165 2.54 4.19L 0.300 0.310 7.62 7.87N 0.020 0.050 0.51 1.27P 0.360 0.400 9.14 10.160.25 (0.010) M T A MPDIP–24P SUFFIXPLASTIC DIP PACKAGECASE 724–03ISSUE D–A–24 13112–B–NOTES:1. CHAMFERED CONTOUR OPTIONAL.2. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.3. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.4. CONTROLLING DIMENSION: INCH.–T–SEATINGPLANEGEFD 24 PLNKC0.25 (0.010) M TAMLJ 24 PLNOTE 1M0.25 (0.010) M TBMINCHES MILLIMETERSDIM MIN MAX MIN MAXA 1.230 1.265 31.25 32.13B 0.250 0.270 6.35 6.85C 0.145 0.175 3.69 4.44D 0.015 0.020 0.38 0.51E 0.050 BSC 1.27 BSCF 0.040 0.060 1.02 1.52G 0.100 BSC 2.54 BSCJ 0.007 0.012 0.18 0.30K 0.110 0.140 2.80 3.55L 0.300 BSC 7.62 BSCM 0 15 0 15N 0.020 0.040 0.51 1.01http://onsemi.com467

PLCC–28FN SUFFIXPLASTIC PLCC PACKAGECASE 776–02ISSUE D–N–Y BRKB0.007 (0.180) M T L–M S N SU 0.007 (0.180) M T L–M S N S–L–28 1V–M–WDDZXVIEW D–DG10.010 (0.250) S T L–M S N SZAR0.007 (0.180) M T L–M S N S0.007 (0.180) M T L–M S N SH0.007 (0.180) M T L–M S N SCEK1GG1JVIEW S0.004 (0.100)–T– SEATINGPLANEKF0.007 (0.180) M T L–M S N S0.010 (0.250) S T L–M S N SVIEW SNOTES:1. DATUMS –L–, –M–, AND –N– DETERMINEDWHERE TOP OF LEAD SHOULDER EXITSPLASTIC BODY AT MOLD PARTING LINE.2. DIMENSION G1, TRUE POSITION TO BEMEASURED AT DATUM –T–, SEATING PLANE.3. DIMENSIONS R AND U DO NOT INCLUDEMOLD FLASH. ALLOWABLE MOLD FLASH IS0.010 (0.250) PER SIDE.4. DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.5. CONTROLLING DIMENSION: INCH.6. THE PACKAGE TOP MAY BE SMALLER THANTHE PACKAGE BOTTOM BY UP TO 0.012(0.300). DIMENSIONS R AND U AREDETERMINED AT THE OUTERMOSTEXTREMES OF THE PLASTIC BODYEXCLUSIVE OF MOLD FLASH, TIE BARBURRS, GATE BURRS AND INTERLEADFLASH, BUT INCLUDING ANY MISMATCHBETWEEN THE TOP AND BOTTOM OF THEPLASTIC BODY.7. DIMENSION H DOES NOT INCLUDE DAMBARPROTRUSION OR INTRUSION. THE DAMBARPROTRUSION(S) SHALL NOT CAUSE THE HDIMENSION TO BE GREATER THAN 0.037(0.940). THE DAMBAR INTRUSION(S) SHALLNOT CAUSE THE H DIMENSION TO BESMALLER THAN 0.025 (0.635).INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.485 0.495 12.32 12.57B 0.485 0.495 12.32 12.57C 0.165 0.180 4.20 4.57E 0.090 0.110 2.29 2.79F 0.013 0.019 0.33 0.48G 0.050 BSC 1.27 BSCH 0.026 0.032 0.66 0.81J 0.020 ––– 0.51 –––K 0.025 ––– 0.64 –––R 0.450 0.456 11.43 11.58U 0.450 0.456 11.43 11.58V 0.042 0.048 1.07 1.21W 0.042 0.048 1.07 1.21X 0.042 0.056 1.07 1.42Y ––– 0.020 ––– 0.50Z 2 10 2 10G1 0.410 0.430 10.42 10.92K1 0.040 ––– 1.02 –––http://onsemi.com468

FJ SUFFIXJ–LEAD CERQUAD PACKAGECASE 778B–01ISSUE O–A–R0.51 (0.020) M T A SB SNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION R AND N DO NOT INCLUDE GLASSPROTRUSION. GLASS PROTRUSION TO BE 0.25(0.010) MAXIMUM.4. ALL DIMENSIONS AND TOLERANCES INCLUDELEAD TRIM OFFSET AND LEAD FINISH.0.51 (0.020) M T A SNB S–B–INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.785 0.795 19.94 20.19B 0.785 0.795 19.94 20.19C 0.165 0.200 4.20 5.08D 0.017 0.021 0.44 0.53F 0.026 0.032 0.67 0.81G 0.050 BSC 1.27 BSCH 0.090 0.130 2.29 3.30J 0.006 0.010 0.16 0.25K 0.035 0.045 0.89 1.14N 0.735 0.756 18.67 19.20R 0.735 0.756 18.67 19.20S 0.690 0.730 17.53 18.54FKHCJGS0.15 (0.006)–T– SEATINGPLANED 52 PL0.18 (0.007) M T A SB Shttp://onsemi.com469

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