An Improved VLSI Test Economics Analysis System - Laboratory for ...

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1.1 Economic ModelsIn the economic models, the prot can be estimated by anumber of circuit parameters suchas the number of gates, nets, and I/Os, and the sequential depth, routing ratio, physicaldesign rule, netlist, layout, etc. However, not all of these circuit parameters are availablein early design cycle, therefore the circuit parameters of our models must be available oreasy to estimate early in the design phase. In our study, we propose a set of such circuitparameters. Besides, some models are developed to estimate the parameters if they can notbe obtained directly in the early design stage.The prot is equal to the revenue subtracted by cost. The revenue comes from market.Thus, a Market Life Model is proposed to estimate the revenue. This model use generalproduction life cycle model to gure out relation between revenue and time to market. Thetime to market will be estimated in the Time Model. Then, we can obtain the revenue ofthe project under consideration.Cost includes capital, labor and raw material. Capital is dened as long-term investmentsuch as land, buildings, machines and tools. Labor includes man-power and management.There are dierence between capital cost and the other two costs. The labor and raw materialcosts are purchased only for immediate or current use, but capital cost is generally purchasedfor use over a long period. Thus, the reasonable capital cost is the depreciation value duringthe current project. In our study, we propose three types of cost equation: one for labor andraw material cost and the other two for capital cost.Most of our cost equations are functions of the time. For example, the salary of designman-power is proportional to the design time and the cost of tester, and the cost of testeris estimated as the depreciation during the test execution time. Some of these time relatedparameters are hard to estimate directly. We propose a Time Model to estimate theseparameters.Cost Model is proposed to estimate total cost of a project. The project is divided intothree stages: design, manufacture and test. Our model estimate each stage cost hierarchically.Each stage cost continuously divided into more and more detail item cost, then theproposed three type cost equations are selected to model each item cost. Finally, all the item2
costs are summed as the total cost.Moreover, a Quality Model is proposed to estimate some test related parameters such asfault coverage, test length, yield and defect level. Those parameters is also hard to estimatedirectly. Some parameters, such as fault coverage and test length, are dependent. Our modeldescribes the dependent relation condition of these parameters, so user can decide the valueof parameters by this model. Besides, this model estimates defect level as our test quality.Although this factor also can map to the cost, the eect of this factor need to consider over along period. We suggest user to decide a threshold defect level. If the estimated defect levelhigher than the threshold, other test methodologies should be applied to lower the defectlevel.Finally, these four models can evaluate prot form those proposed parameters. If we canknow how these parameters will be aected by various test methodologies, we can comparethe prot of these test methodologies. This is one future work. For now, we only considerscan test to obtain the changes of parameters such as test generation time, test length, chiparea, etc.1.2 Analysis SystemWe develop a software system, call ESTEEM, for the following two purposes. First, thissystem is used to implement our economic models. Second, this system can help us collectdata for future works. For these purposes, our system have the following features: theweb-based program can be accessed from any place of the world via the Internet. Securityis provided to protect data of each user. A database is integrated to handle user's data.Friendly graphic user interface (GUI) and exible analysis engine makes it easy to handleproject les and modify equations in the models.1.3 Previous WorksA knowledge based system to aid in creating easily testable VLSI chips, called TDES(Testable Design Expert System), was developed at the University of Southern California [1].It was implemented in Lisp. The aim of TDES was to create a framework for methodol-3
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7: Chapter 1IntroductionFrom business
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60:
Table 4.12: Cost of dierent volume.
Page 61 and 62:
in Figure 4.4 for 2K volume and Fig
Page 63 and 64:
circuits were translated to Verilog
Page 65 and 66:
Design space cost for rent building
Page 67 and 68:
Revenue with DFT design:R dft = 1 2
Page 69 and 70:
1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72:
Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74:
Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76:
1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78:
Kd mp : user-dened man-power cost .
Page 79:
[13] R. G. Bennetts, C. M. Maunder,
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