12.07.2015 Views

An Improved VLSI Test Economics Analysis System - Laboratory for ...

An Improved VLSI Test Economics Analysis System - Laboratory for ...

An Improved VLSI Test Economics Analysis System - Laboratory for ...

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

[13] R. G. Bennetts, C. M. Maunder, and G. D. Robinson, \CAMELOT: a computer-aidedmeasure <strong>for</strong> logic testability," IEE Proc. Pt. E, vol. 128, no. 5, pp. 177{189, 1981.[14] C. Chen and P. Menon, \<strong>An</strong> approach to functional level testabilty analysis," in Proc.Int. <strong>Test</strong> Conf. (ITC), pp. 373{380, 1989.[15] C.-H. Chen and S. Daniel G, \A novel behavioral testability measure," IEEE Tran.on Computer-Aided Design on Integrated Circuits and <strong>System</strong>s, vol. 12, pp. 1960{1970,Dec. 1993.[16] T. W. Williams and N. C. Brown, \Defect level as a function of fault coverage," IEEETrans. Comput., vol. C-30, pp. 987{988, Dec. 1981.[17] J. T. de Sousa, F. M. Goncalves, C. M. J. Paulo Teixeira, F. Corsi, and T. W. Williams,\Defect level evaluation in an ic design environment," IEEE Trans. Circuits and <strong>System</strong>s,vol. 15, pp. 1286{1293, Oct. 1996.[18] J. Cunningham, \The use and evaluation of yield modelsin integrated circuit manufacturing,"IEEE Trans. Semiconductor Manufacturing, vol. 3, pp. 60{71, May 1990.[19] S. Domer, S. Foertsch, and G. Raskin, \Model <strong>for</strong> yield and manufacturing prediction on<strong>VLSI</strong> designs <strong>for</strong> advanced technologies, mixed circuitry, and memories," IEEE Journalof Solid-State Circuit, vol. 30, pp. 286{294, Mar. 1995.[20] V. Kim, M. Tegetho, and T. Chen, \ASIC yield estimation at early design cycle," inProc. Int. <strong>Test</strong> Conf. (ITC), pp. 590{594, 1996.[21] S. C. Ma, P. Franco, and E. J. McCluskey, \<strong>An</strong> experimental chip to evaluate testtechniques experiment results," in Proc. Int. <strong>Test</strong> Conf. (ITC), pp. 663{672, 1995.[22] P. Goel, \<strong>Test</strong> generation costs analysis and projections," in Proc. IEEE/ACM DesignAutomation Conf. (DAC), pp. 77{84, 1980.[23] K.-T. Cheng and W. D. Agrawal, \A partical scan method <strong>for</strong> sequential circuits withfeedback," IEEE trans. comput., vol. 39, pp. 544{548, Apr. 1990.[24] T. J. Moore, \A test process optimization and cost modeling tool," in Proc. Int. <strong>Test</strong>Conf. (ITC), pp. 103{110, 1994.[25] F. Brglez, D. Bryan, and K. Kozminski, \Combinational proles of sequential benchmarkcircuits," in Proc. IEEE Int. Symp. Circuits and <strong>System</strong>s (ISCAS), pp. 1929{1934,1989.73

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!