An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
Bibliography[1] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and TestableDesign. New York: Computer Science Press, 1990.[2] M. S. Abadir, \TIGER: Testability insertion guidance expert system," in Proc. IEEEInt. Conf. Computer-Aided Design (ICCAD), pp. 562{565, 1989.[3] B. Davis, The Economics of Automatic Testing. London: McGraw-Hill, second ed.,1994.[4] I. D. Dear, C. Dislis, A. P. Ambler, and J. Dick, \Economic eects in design and test,"IEEE Design & Test of Computers, vol. 8, no. 4, pp. 64{77, 1991.[5] V.-K. Kim, T. Chen, and M. Tegetho, \ASIC manufacturing test cost prediction atearly design stage," in Proc. Int. Test Conf. (ITC), 1997.[6] S. Wei, P. K. Nag, R. D. Blanton, A. Gattiker, and W. Maly, \To DFT or not to DFT?,"in Proc. Int. Test Conf. (ITC), 1997.[7] C.-C. Wei, \A WWW-based VLSI test strategy analysis system," Master's Thesis, Departmentof Elec. Eng., National Tsing Hua Univ., Hsinchu, Taiwan, June 1997.[8] C.-C. Cheng, \An economic analysis system for VLSI test strategy planning," Master'sThesis, Department of Electrical Engineering, National Tsing Hua University, Hsinchu,Taiwan, June 1996.[9] C.-H. Tsai, \IEEE Std 1149.5 MTM-Bus Slave module chip design and its applicationto hierarchical system test," Master's Thesis, Department of Electrical Engineerig,National Tsing Hua University, Hsinchu, Taiwan, June 1996.[10] S. DasGupta, \Design for Test (DFT) Workshop, Methods and Cost Parameters Report,"Tech. Transfer 95113029B-TR, SEMATECH, 2706 Montoplis Drive, Austin, TX7841, Sept. 1996. http://www.sematech.org.[11] J. Grason, \TMEAS|a testability measurement program," in Proc. IEEE/ACM DesignAutomation Conf. (DAC), pp. 156{161, 1979.[12] L. H. Goldstein, \Controllability/observability analysis for digital circuits," IEEE Trans.Circuits and Systems, vol. 26, pp. 685{693, Sept. 1979.72
[13] R. G. Bennetts, C. M. Maunder, and G. D. Robinson, \CAMELOT: a computer-aidedmeasure for logic testability," IEE Proc. Pt. E, vol. 128, no. 5, pp. 177{189, 1981.[14] C. Chen and P. Menon, \An approach to functional level testabilty analysis," in Proc.Int. Test Conf. (ITC), pp. 373{380, 1989.[15] C.-H. Chen and S. Daniel G, \A novel behavioral testability measure," IEEE Tran.on Computer-Aided Design on Integrated Circuits and Systems, vol. 12, pp. 1960{1970,Dec. 1993.[16] T. W. Williams and N. C. Brown, \Defect level as a function of fault coverage," IEEETrans. Comput., vol. C-30, pp. 987{988, Dec. 1981.[17] J. T. de Sousa, F. M. Goncalves, C. M. J. Paulo Teixeira, F. Corsi, and T. W. Williams,\Defect level evaluation in an ic design environment," IEEE Trans. Circuits and Systems,vol. 15, pp. 1286{1293, Oct. 1996.[18] J. Cunningham, \The use and evaluation of yield modelsin integrated circuit manufacturing,"IEEE Trans. Semiconductor Manufacturing, vol. 3, pp. 60{71, May 1990.[19] S. Domer, S. Foertsch, and G. Raskin, \Model for yield and manufacturing prediction onVLSI designs for advanced technologies, mixed circuitry, and memories," IEEE Journalof Solid-State Circuit, vol. 30, pp. 286{294, Mar. 1995.[20] V. Kim, M. Tegetho, and T. Chen, \ASIC yield estimation at early design cycle," inProc. Int. Test Conf. (ITC), pp. 590{594, 1996.[21] S. C. Ma, P. Franco, and E. J. McCluskey, \An experimental chip to evaluate testtechniques experiment results," in Proc. Int. Test Conf. (ITC), pp. 663{672, 1995.[22] P. Goel, \Test generation costs analysis and projections," in Proc. IEEE/ACM DesignAutomation Conf. (DAC), pp. 77{84, 1980.[23] K.-T. Cheng and W. D. Agrawal, \A partical scan method for sequential circuits withfeedback," IEEE trans. comput., vol. 39, pp. 544{548, Apr. 1990.[24] T. J. Moore, \A test process optimization and cost modeling tool," in Proc. Int. TestConf. (ITC), pp. 103{110, 1994.[25] F. Brglez, D. Bryan, and K. Kozminski, \Combinational proles of sequential benchmarkcircuits," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 1929{1934,1989.73
- Page 27 and 28: where K dsgn is user dened design c
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65 and 66: Design space cost for rent building
- Page 67 and 68: Revenue with DFT design:R dft = 1 2
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
- Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
- Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
- Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
- Page 77: Kd mp : user-dened man-power cost .
Bibliography[1] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital <strong>System</strong>s <strong>Test</strong>ing and <strong>Test</strong>ableDesign. New York: Computer Science Press, 1990.[2] M. S. Abadir, \TIGER: <strong>Test</strong>ability insertion guidance expert system," in Proc. IEEEInt. Conf. Computer-Aided Design (ICCAD), pp. 562{565, 1989.[3] B. Davis, The <strong>Economics</strong> of Automatic <strong>Test</strong>ing. London: McGraw-Hill, second ed.,1994.[4] I. D. Dear, C. Dislis, A. P. Ambler, and J. Dick, \Economic eects in design and test,"IEEE Design & <strong>Test</strong> of Computers, vol. 8, no. 4, pp. 64{77, 1991.[5] V.-K. Kim, T. Chen, and M. Tegetho, \ASIC manufacturing test cost prediction atearly design stage," in Proc. Int. <strong>Test</strong> Conf. (ITC), 1997.[6] S. Wei, P. K. Nag, R. D. Blanton, A. Gattiker, and W. Maly, \To DFT or not to DFT?,"in Proc. Int. <strong>Test</strong> Conf. (ITC), 1997.[7] C.-C. Wei, \A WWW-based <strong>VLSI</strong> test strategy analysis system," Master's Thesis, Departmentof Elec. Eng., National Tsing Hua Univ., Hsinchu, Taiwan, June 1997.[8] C.-C. Cheng, \<strong>An</strong> economic analysis system <strong>for</strong> <strong>VLSI</strong> test strategy planning," Master'sThesis, Department of Electrical Engineering, National Tsing Hua University, Hsinchu,Taiwan, June 1996.[9] C.-H. Tsai, \IEEE Std 1149.5 MTM-Bus Slave module chip design and its applicationto hierarchical system test," Master's Thesis, Department of Electrical Engineerig,National Tsing Hua University, Hsinchu, Taiwan, June 1996.[10] S. DasGupta, \Design <strong>for</strong> <strong>Test</strong> (DFT) Workshop, Methods and Cost Parameters Report,"Tech. Transfer 95113029B-TR, SEMATECH, 2706 Montoplis Drive, Austin, TX7841, Sept. 1996. http://www.sematech.org.[11] J. Grason, \TMEAS|a testability measurement program," in Proc. IEEE/ACM DesignAutomation Conf. (DAC), pp. 156{161, 1979.[12] L. H. Goldstein, \Controllability/observability analysis <strong>for</strong> digital circuits," IEEE Trans.Circuits and <strong>System</strong>s, vol. 26, pp. 685{693, Sept. 1979.72
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