An Improved VLSI Test Economics Analysis System - Laboratory for ...

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List of Parameters,: chip complexity.....................11 p : package cost parameter . ...........24 as0 : total sensivitve parameter 0 ......29 as1 : total sensivitve parameter 1 ......29 as2 : total sensivitve parameter 2 ......29 fc : fault coverage estimation parameter32 pp : package cost parameter ...........24 td G :chip development time parameter27 td g : block development time parameter27 tf : nal test time and length ratio . . . . 27 tp : pre-burn-in test time and length ratio27 tw : wafer test time and length ratio . . . 27 util : utilization of wafer . ..............24: block complexity....................13: block reusability....................13 d : defect density......................29A: chip area ...........................12a: block area. . . ........................11A p : area per pad.......................12A s : total sensitive area.................29C: total cost .......................15, 16C dsgn : design cost . . . ...................20C hw train : trainning cost of designhardware ......................22C mask : mask cost ......................24C proto : prototype cost . . . ...........20, 23C space : design space cost ...............22C sw train : trainning cost of design software................................22Cd: development cost . . ............16, 20Cd equip : design equipment cost . ....20, 22Cd mang : design management cost . . . 20, 23Cd mp : design man-power cost ......20, 21Cd space : design space cost ..............20Cm: manufacturing cost . . .........16, 24Ct: testing cost . ...................16, 24Ct f : burn-in test cost ..................25Ct f : nal test cost .....................24Ct p : pre-burn-in test cost ..........24, 25Ct w : wafer test cost................24, 25Ct f eq : price of nal test equipment....25Ct f mt : maintenance cost of nal testequipment.....................25Ct p eq : price of pre-burn-in test equipment25Ct p mt : maintenance cost of pre-burn-intest equipment.................25Ct w eq : price of wafer test equipment...25Ct w mt : maintenance cost of wafer testequipment.....................25d: wafer diameter . .....................24DL f : nal test defect level.............28DL p : pre-burn-in test defect level......28DL w : wafer test defect level............28f dp : depreciative dierence ratio function22FC f : nal test fault coverage. . . ....28, 32FC p : pre-burn-in test fault coverage28, 32FC w : wafer test fault coverage . ....28, 32G: gate count of chip..................11g: gate count of block..................10gar: gate area ratio of block...........10K: user dened total cost ..............16K dsgn : user dened design cost . . . . .....20K proto : user dened prototype cost .....23K space : user-dened space cost .........22Kd: user dened development cost .....20Kd mang : user dened mangement cost. .2370
Kd mp : user-dened man-power cost . . . . 21Km: user dened manufacturing cost . . 24Kt: user dened testing cost...........24Kt f : user dened nal test time .......25Kt p : user dened pre-burn-in test time.25Kt w : user dened wafer test time . .....25n: number of nets in block.............10N B :number of blocks in chip...........9N proto : number of prototyping rounds . . 23nar: net area ratio of block............11Nd eng :number of design engineers . ....21P :chip pins. .......................12, 24p: number of I/Os of block.............10Prof: prot . ..........................15Pt f eq :number of test pins of nal testequipment.....................25Pt p eq : number of test pins of pre-burn-intest equipment.................25Pt w eq :number of test pins of wafer testequipment.....................25R: revenue.........................15, 32R hw dp : depreciative rate of designhardware ......................22R mang : management man-power timeratio . ..........................23R pf : pre-burn-in and nal test lengthratio . ..........................31R space : design department space ratio . . 22R sw dp : depreciative rate of designsoftware . .....................22R wf : wafer and nal test length ratio . . 31Rd sp ap : appreciative rate of space .....22Rt f eq : depreciative ratio of nal testequipment.....................25Rt p eq : depreciative ratio of pre-burn-intest equipment.................25Rt w eq : depreciative ratio of wafer testequipment.....................25tb: block testability....................13Td save : DFT saving development time. .33tm: test methodologies of block........10TMM decl : market declining period . 32, 33TMM grow : market growing period. .32, 33TMM matu : market maturity period 32, 33TMM rev : maximal revenue.........32, 33Tt f : nal test time . ................25, 27Tt p : pre-burn-in test time . . . .......25, 27Tt w :wafer test time. ...............25, 27U die : cost per die.......................24U hw mt : maintainence cost of designhardware......................22U hw : price of design hardware..........22U mang : salary of manager ..............23U pack : package cost of each chip........24U proto : prototyping cost per round. . . . . .23U rent : annual rent......................22U sw mt : maintainence cost of designsoftware.......................22U sw : price of design software...........22U wafer : cost per wafer..................24Ud eng : average salary of engineers . . ....21V f : nal test length of chip.....14, 31, 32v f : nal test length of block...........14V p : pre-burn-in test length of chip . 14, 31,32v p : pre-burn-in test length of block.....14V w :wafer test length of chip....14, 31, 32v w : wafer test length of block..........14Y : yield . .......................24, 28, 29t: type of block.........................9T d : development time . .................27T dsgn : design time. .....................21TB:chip testability....................1471
Page 1 and 2:
An Improved VLSI Test Economics Ana
Page 3 and 4:
Contents1 Introduction 11.1 Economi
Page 5 and 6:
List of Figures2.1 Area relation be
Page 7 and 8:
Chapter 1IntroductionFrom business
Page 9 and 10:
costs are summed as the total cost.
Page 11 and 12:
TEEM)" for VLSI test strategy plann
Page 13 and 14:
Chapter 2Economic ModelsIn this cha
Page 15 and 16:
2.2 Circuit DescriptionThis section
Page 17 and 18:
Gate Area Ratio (gar): Average gate
Page 19 and 20:
(a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22:
The proposed economic models consis
Page 23 and 24:
However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75: 1*s38584.10.90.80.7Fault Coverage (
Page 79: [13] R. G. Bennetts, C. M. Maunder,
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