An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ...
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List of Parameters,: chip complexity.....................11 p : package cost parameter . ...........24 as0 : total sensivitve parameter 0 ......29 as1 : total sensivitve parameter 1 ......29 as2 : total sensivitve parameter 2 ......29 fc : fault coverage estimation parameter32 pp : package cost parameter ...........24 td G :chip development time parameter27 td g : block development time parameter27 tf : nal test time and length ratio . . . . 27 tp : pre-burn-in test time and length ratio27 tw : wafer test time and length ratio . . . 27 util : utilization of wafer . ..............24: block complexity....................13: block reusability....................13 d : defect density......................29A: chip area ...........................12a: block area. . . ........................11A p : area per pad.......................12A s : total sensitive area.................29C: total cost .......................15, 16C dsgn : design cost . . . ...................20C hw train : trainning cost of designhardware ......................22C mask : mask cost ......................24C proto : prototype cost . . . ...........20, 23C space : design space cost ...............22C sw train : trainning cost of design software................................22Cd: development cost . . ............16, 20Cd equip : design equipment cost . ....20, 22Cd mang : design management cost . . . 20, 23Cd mp : design man-power cost ......20, 21Cd space : design space cost ..............20Cm: manufacturing cost . . .........16, 24Ct: testing cost . ...................16, 24Ct f : burn-in test cost ..................25Ct f : nal test cost .....................24Ct p : pre-burn-in test cost ..........24, 25Ct w : wafer test cost................24, 25Ct f eq : price of nal test equipment....25Ct f mt : maintenance cost of nal testequipment.....................25Ct p eq : price of pre-burn-in test equipment25Ct p mt : maintenance cost of pre-burn-intest equipment.................25Ct w eq : price of wafer test equipment...25Ct w mt : maintenance cost of wafer testequipment.....................25d: wafer diameter . .....................24DL f : nal test defect level.............28DL p : pre-burn-in test defect level......28DL w : wafer test defect level............28f dp : depreciative dierence ratio function22FC f : nal test fault coverage. . . ....28, 32FC p : pre-burn-in test fault coverage28, 32FC w : wafer test fault coverage . ....28, 32G: gate count of chip..................11g: gate count of block..................10gar: gate area ratio of block...........10K: user dened total cost ..............16K dsgn : user dened design cost . . . . .....20K proto : user dened prototype cost .....23K space : user-dened space cost .........22Kd: user dened development cost .....20Kd mang : user dened mangement cost. .2370