An Improved VLSI Test Economics Analysis System - Laboratory for ...

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1*s13207.11*s15850.10.90.90.80.80.70.7Fault Coverage (FC)0.60.50.4Fault Coverage (FC)0.60.50.40.30.30.20.20.10.100 50 100 150 200 250Test Vector Length (V)PIs 31 Max. Vec 5989POs 121 Max. FC 0.54FFs 669 fc 0.0047Gates 7951 Err Sqrt 3.0e-200 500 1000 1500 2000 2500 3000 3500Test Vector Length (V)PIs 14 Max. Vec 3561POs 87 Max. FC 0.45FFs 597 fc 0.00026Gates 9772 Err Sqrt 1.2e-2Fault Coverage (FC)10.90.80.70.60.50.40.30.20.1s3593200 50 100 150 200 250Test Vector Length (V)PIs 35 Vectors 374POs 320 fc 0.0622FFs 1728 Err Sqrt 1.7e-4Gates 16065Depth 35Fault Coverage (FC)10.90.80.70.60.50.40.30.20.1*s3858400 200 400 600 800 1000 1200 1400 1600 1800 2000Test Vector Length (V)PIs 12 Max. Vec 2079POs 278 Max. FC 0.30FFs 1452 fc 0.00024Gates 19253 Err Sqrt 8.7e-368
1*s38584.10.90.80.7Fault Coverage (FC)0.60.50.40.30.20.100 1000 2000 3000 4000 5000 6000 7000Test Vector Length (V)PIs 12 Max. Vec 7914POs 278 Max. FC 0.72FFs 1452 fc 0.00026Gates 19253 Err Sqrt 2.5e-169
Page 1 and 2:
An Improved VLSI Test Economics Ana
Page 3 and 4:
Contents1 Introduction 11.1 Economi
Page 5 and 6:
List of Figures2.1 Area relation be
Page 7 and 8:
Chapter 1IntroductionFrom business
Page 9 and 10:
costs are summed as the total cost.
Page 11 and 12:
TEEM)" for VLSI test strategy plann
Page 13 and 14:
Chapter 2Economic ModelsIn this cha
Page 15 and 16:
2.2 Circuit DescriptionThis section
Page 17 and 18:
Gate Area Ratio (gar): Average gate
Page 19 and 20:
(a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22:
The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73: Fault Coverage (FC)10.90.80.70.60.5
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,
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