An Improved VLSI Test Economics Analysis System - Laboratory for ...

Chapter 1IntroductionFrom business perspective, the goal for designing a chip is to gain maximal prot frommarket. There are three key factors aecting the prot: cost, time, and quality. The costincludes design cost, manufacturing cost and testing cost. The time includes design time,test generation time, test executing time, etc. Quality includes defect level, performance andreliability. Generally, these three factors are conict to each other. For example, low defectlevel chip needs long test generation time, test executing time and high test cost. TraditionalVLSI economics only need to balance the cost of those factors to gain maximal prot.However, VLSI technology has a rapid growth of integration, which results in millionsof transistors integrated in a single chip. Such a chip is almost impossible to test withoutdesign-for-testability (DFT) consideration. By including DFT methodologies to our teststrategies, we can change the conicting situation of the three prot factors. For example,scan will reduce test generation time and increase fault coverage simultaneously, but it scanincreases chip area, i.e., it increases manufacturing cost. DFT thus results in a situationwhich is more complex than before. Selecting the best test strategy for a VLSI circuit byperforming an economic analysis becomes more and more important.In our study, we propose a set of economic models to estimate prot changes resultingfrom dierent test strategies. A new version of the analysis system which we have workedon since more than two years ago is developed. This system can help the user make DFTdecision in the early stage of the design.1