An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
A.2 Time ModelDevelop time:T d = e td GG,(1,TB) +Xper blocke td gg(1,)(1,tb) :(Eq.2.44, pp.27)Testing time:Tt w = tw V w ;Tt p = tp V p ;Tt f = tb V f ;(Eq.2.45, pp.27)A.3 Quality ModelDefect level:DL w =1, Y 1,FCwDL p =1, Y 1,FCpDL f =1, Y 1,FC f;(Eq.2.47, pp.28)Total sensitive area:A s = as0 + as1 g 2 + as2p n(Eq.2.49, pp.29)Yield:Y = e , dA s(Eq.2.50, pp.29)Test length:V w = R wf V fV p = R pf V p ;(Eq.2.54, pp.31)Fault coverage:FC w =1, e , fcV wFC p =1, e , fcV p(Eq.2.55, pp.32)A.4 Market Life ModelRevenue of no-DFT design:FC f =1, e , fcV fR = 1 2 (TMM grow +2TMM matu + TMM decl ) TMM rev(Eq.2.56, pp.32)60
Revenue with DFT design:R dft = 1 22 (TMM grow +2TMM matu ) TMM rev Tdsave + TMM grow + TMM matuTMM grow + TMM matu+ 1 2 TMM decl TMM rev Td save + TMM grow + TMM matuTMM grow + TMM matu;(Eq.2.57, pp.33)61
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
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- Page 25 and 26: Type II: C = UR f N tThis equation
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- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
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- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
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- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
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Revenue with DFT design:R dft = 1 22 (TMM grow +2TMM matu ) TMM rev Tdsave + TMM grow + TMM matuTMM grow + TMM matu+ 1 2 TMM decl TMM rev Td save + TMM grow + TMM matuTMM grow + TMM matu;(Eq.2.57, pp.33)61