An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
A.2 Time ModelDevelop time:T d = e td GG,(1,TB) +Xper blocke td gg(1,)(1,tb) :(Eq.2.44, pp.27)Testing time:Tt w = tw V w ;Tt p = tp V p ;Tt f = tb V f ;(Eq.2.45, pp.27)A.3 Quality ModelDefect level:DL w =1, Y 1,FCwDL p =1, Y 1,FCpDL f =1, Y 1,FC f;(Eq.2.47, pp.28)Total sensitive area:A s = as0 + as1 g 2 + as2p n(Eq.2.49, pp.29)Yield:Y = e , dA s(Eq.2.50, pp.29)Test length:V w = R wf V fV p = R pf V p ;(Eq.2.54, pp.31)Fault coverage:FC w =1, e , fcV wFC p =1, e , fcV p(Eq.2.55, pp.32)A.4 Market Life ModelRevenue of no-DFT design:FC f =1, e , fcV fR = 1 2 (TMM grow +2TMM matu + TMM decl ) TMM rev(Eq.2.56, pp.32)60
Revenue with DFT design:R dft = 1 22 (TMM grow +2TMM matu ) TMM rev Tdsave + TMM grow + TMM matuTMM grow + TMM matu+ 1 2 TMM decl TMM rev Td save + TMM grow + TMM matuTMM grow + TMM matu;(Eq.2.57, pp.33)61
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27 and 28: where K dsgn is user dened design c
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65: Design space cost for rent building
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
- Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
- Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
- Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
- Page 77 and 78: Kd mp : user-dened man-power cost .
- Page 79: [13] R. G. Bennetts, C. M. Maunder,
A.2 Time ModelDevelop time:T d = e td GG,(1,TB) +Xper blocke td gg(1,)(1,tb) :(Eq.2.44, pp.27)<strong>Test</strong>ing time:Tt w = tw V w ;Tt p = tp V p ;Tt f = tb V f ;(Eq.2.45, pp.27)A.3 Quality ModelDefect level:DL w =1, Y 1,FCwDL p =1, Y 1,FCpDL f =1, Y 1,FC f;(Eq.2.47, pp.28)Total sensitive area:A s = as0 + as1 g 2 + as2p n(Eq.2.49, pp.29)Yield:Y = e , dA s(Eq.2.50, pp.29)<strong>Test</strong> length:V w = R wf V fV p = R pf V p ;(Eq.2.54, pp.31)Fault coverage:FC w =1, e , fcV wFC p =1, e , fcV p(Eq.2.55, pp.32)A.4 Market Life ModelRevenue of no-DFT design:FC f =1, e , fcV fR = 1 2 (TMM grow +2TMM matu + TMM decl ) TMM rev(Eq.2.56, pp.32)60
Change language