An Improved VLSI Test Economics Analysis System - Laboratory for ...

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Appendix ASummary of All ModelA.1 Cost ModelC = Cd + Cm + Ct + K(Eq.2.9, pp.16)A.1.1Developmental costCd = C dsgn + Cd mang + Kd(Eq.2.23, pp.20)Design CostC dsgn = Cd mp + Cd equip + Cd space + C proto + K dsgn(Eq.2.24, pp.20)Design man-power cost:Cd mp = Ud eng Nd eng T dsgn + Kd mp(Eq.2.25, pp.21)Design equipment cost:Cd equip =Xf dp (R dp )=1, (1 , R dp ) T d(Eq.2.27, pp.22)U hw f dp (R hw dp )+U hw mt T d + C hw traineach Xhw (Eq.2.28, pp.22)+U sw f dp (R sw dp )+U sw mt ) T d + C sw traineach swOr use Type II cost model:XCd equip =(U hw R hw dp + U hw mt ) T d + C hw traineach Xhw (Eq.2.29, pp.22)+(U sw R sw dp + U sw mt ) T d + C sw traineach sw58
Design space cost for rent building companies:Cd space = Rd space U rent T d + K space(Eq.2.30, pp.22)For buy building companies:Cd space = Rd space U space [(1 + R int ) T d, (1 + R sp ap ) T d]+K space(Eq.2.31, pp.22)Prototypes cost for fab prototyping:C proto = N proto U mask + K proto(Eq.2.33, pp.23)For FPGA and emulator prototyping, cost implied in equipment cost.Management CostCd mang =Xper manager(U mang R mang T d )+Kd mang (Eq.2.34, pp.23)A.1.2Manufacturing CostCm = C mask =N v + U die + U pack + Km(Eq.2.35, pp.24)Cost per die:Package cost per chip:U die = U wafer =n g = 4AU wafer util d 2 YU pack = p + pp P(Eq.2.37, pp.24)(Eq.2.38, pp.24)A.1.3Testing CostWafer test cost:Ct w = Xper tw eqPre-burn-in test cost:Ct p =Final test cost:Ct f = Xper tp eq Xper tf eqCt = Ct w + Ct p + Ct f + Kt;Ct w eq Rt w eq + Ct w mtP Tt w =Y + Kt w ;Pt w eqCt p eq Rt p eq + Ct p mtP Tt p + Kt p ;Pt p eqCt f eq Rt f eq + Ct f mtP Tt f + Kt f ;Pt f eq(Eq.2.39, pp.24)(Eq.2.41, pp.25)(Eq.2.42, pp.25)(Eq.2.43, pp.25)59
Page 1 and 2:
An Improved VLSI Test Economics Ana
Page 3 and 4:
Contents1 Introduction 11.1 Economi
Page 5 and 6:
List of Figures2.1 Area relation be
Page 7 and 8:
Chapter 1IntroductionFrom business
Page 9 and 10:
costs are summed as the total cost.
Page 11 and 12:
TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63: circuits were translated to Verilog
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,
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