An Improved VLSI Test Economics Analysis System - Laboratory for ...

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Chapter 5ConclusionsWe have shown that if we select suitable test strategy for the design, the prot will greatlyincrease. Economic models had been developed to help nd the optimal test strategy. Weproposed four economic models, a set of circuit parameters, and a test methodologies library.Base on the previous works, a quality model had been added to provide more accurateestimation value of test related parameters, such as fault coverage, yield and defect level.The whole system now includes four models: Cost Model, Time Model, Quality Model andMarket Life Model. Cost Model estimates the total cost and Market Life Model estimatesthe revenue. Moreover, Time Model estimate the time related parameters. Besides, in thecircuit description, many suggestion and heuristics have been proposed to help estimatecircuit parameters which are hard to obtain.In the system, the new version of ESTEEM provides more security for users data. Thesystem uses Perl, Java and Javascript languages and integrates web server, SQL server, andCGI programs. This system provides more friendly users interface, such as le manager,model editor, and result display. Besides, a more powerful analysis engine had been developed,so user can easily add new equations or modify proposed models to t the conditionof their companies.In addition, we had done some experiments to obtain eects of scan design. The ISCAS'89benchmark circuits were applied to sequential ATPG and random pattern fault simulatorto nd the relation between fault coverage and test length. Then, ISCAS'89 SCAN circuitswere applied to combinational ATPG to obtain similar relation. The relation of three designmethods: sequential ATPG, random pattern, and scan were compared. Moreover, ISCAS'8956
circuits were translated to Verilog format for synthesis. The synthesized area of ISCAS'89and its scan version were compared, too.Finally, an IEEE 1149.5 MTM-Bus slave module chip is analyzed by our system. Theresult shows that the DFT prot will greatly increase if DFT is used, since it saves thedevelopment time and shortens time to market. Besides, by comparing dierent volumes forthe same case, we found a threshold volume. The total cost with DFT is lower than thatwithout DFT under this threshold volume.This is an on-going project, where modeling the eect of more test methodologies, performanceimpact of DFT, more realist models developed from the collected data will be donein the future. Beside, optimization and auto learning capability will be investigated.57
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An Improved VLSI Test Economics Ana
Page 3 and 4:
Contents1 Introduction 11.1 Economi
Page 5 and 6:
List of Figures2.1 Area relation be
Page 7 and 8:
Chapter 1IntroductionFrom business
Page 9 and 10:
costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61: in Figure 4.4 for 2K volume and Fig
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,
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