An Improved VLSI Test Economics Analysis System - Laboratory for ...

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List of Tables2.1 Examples of notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2 Type and notation of parameters in models. . . . . . . . . . . . . . . . . . . 82.3 Parameters of circuit description. . . . . . . . . . . . . . . . . . . . . . . . . 92.4 Types of block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.5 Test methodologies for each type of block. . . . . . . . . . . . . . . . . . . . 102.6 N pass and N v ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.1 ISCAS'89 benchmark circuit characteristics. . . . . . . . . . . . . . . . . . . 434.2 Fault coverage parameter approximation. . . . . . . . . . . . . . . . . . . . . 454.3 Fault coverage and test length of random pattern. . . . . . . . . . . . . . . . 474.4 Circuit area of benchmarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.5 Parameters of chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.6 Parameters of each block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.7 Parameters in cost model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.8 Parameters of time model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.9 Parameters of market life model. . . . . . . . . . . . . . . . . . . . . . . . . 514.10 Parameters of quality model. . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.11 Result of analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.12 Cost of dierent volume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.13 Cost of dierent volume in larger area case. . . . . . . . . . . . . . . . . . . 53iv
Chapter 1IntroductionFrom business perspective, the goal for designing a chip is to gain maximal prot frommarket. There are three key factors aecting the prot: cost, time, and quality. The costincludes design cost, manufacturing cost and testing cost. The time includes design time,test generation time, test executing time, etc. Quality includes defect level, performance andreliability. Generally, these three factors are conict to each other. For example, low defectlevel chip needs long test generation time, test executing time and high test cost. TraditionalVLSI economics only need to balance the cost of those factors to gain maximal prot.However, VLSI technology has a rapid growth of integration, which results in millionsof transistors integrated in a single chip. Such a chip is almost impossible to test withoutdesign-for-testability (DFT) consideration. By including DFT methodologies to our teststrategies, we can change the conicting situation of the three prot factors. For example,scan will reduce test generation time and increase fault coverage simultaneously, but it scanincreases chip area, i.e., it increases manufacturing cost. DFT thus results in a situationwhich is more complex than before. Selecting the best test strategy for a VLSI circuit byperforming an economic analysis becomes more and more important.In our study, we propose a set of economic models to estimate prot changes resultingfrom dierent test strategies. A new version of the analysis system which we have workedon since more than two years ago is developed. This system can help the user make DFTdecision in the early stage of the design.1
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5: List of Figures2.1 Area relation be
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58:
Table 4.8: Parameters of time model
Page 59 and 60:
Table 4.12: Cost of dierent volume.
Page 61 and 62:
in Figure 4.4 for 2K volume and Fig
Page 63 and 64:
circuits were translated to Verilog
Page 65 and 66:
Design space cost for rent building
Page 67 and 68:
Revenue with DFT design:R dft = 1 2
Page 69 and 70:
1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72:
Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74:
Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76:
1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78:
Kd mp : user-dened man-power cost .
Page 79:
[13] R. G. Bennetts, C. M. Maunder,
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