An Improved VLSI Test Economics Analysis System - Laboratory for ...

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Table 4.11: Result of analysis.Analysis result Notation no-DFT DFTprot prof 29.7M 38.8M nttotal cost cost 6.33M 6.26M nttotal cost per chip C 551 546 ntdevelopment cost Cd 370 361 ntmanufacturing cost Cm 153 158 nttesting cost Ct 27 27 ntdevelopment time Td 14 12 monthwafer test time Ttw 72 64 secondpre-burn-in test time Ttp 76 68 secondnal test time Ttb 80 72 secondrevenue R 36M 45M ntyield Y 0.9987 0.9851fault coverage FC 0.982 0.999defect level DL 227 11 DPMin this table, DFT will reduce the development time by 2 months, so the revenue increasesfrom 36M to 45M. The prot increases from 29.7M to 38.8M. Moreover, DFT increases area,so the yield reduces from 0.9987 to 0.9851. However, DFT increases fault coverage from0.982 to 0.999. The defect level reduces from 277 to 11 DPM. In this case, DFT increaseboth prot and quality.After that, we analysis the cost of dierent volume. As shown in Table 4.12, we comparecost for volume from 10k to 320k. Cd, Cm, and Ct are development, manufacturing, andtesting cost of no-DFT. C is total cost without DFT. Cd dft , Cm dft , Ct dft , and C dft are thecost with DFT. By comparing value of each stage cost with and without DFT, we can ndthat DFT decreases development and testing cost, but it increases manufacturing cost. Thus,as shown in last two column, DFT may not reduce the total cost when the volume is high.To analysis the case of larger chip, we multiply gate count of each block by ten. The costof this case is shown in Table 4.13. As shown in last two column, the total cost with DFTis higher than design without DFT, when the volume is high.Figure 4.3 shows the bar chart of cost and volume. By this chart, we can nd thethreshold volume 80K. We get benet form DFT, if the volume lower this threshold.To see why cost of DFT will not get benet any more, the cost ratio of each stage is shown52
Table 4.12: Cost of dierent volume.Nv Cd Cd dft Cm Cm dft Ct Ct dft C C dft10K 370 361 153 158 109 106 633 62620K 185 180 103 108 109 106 398 39530K 123 120 87 91 109 106 319 31840K 92 90 78 83 109 106 280 28060K 61 60 70 74 109 106 241 241Table 4.13: Cost of dierent volume in larger area case.Nv Cd Cd dft Cm Cm dft Ct Ct dft C C dft10K 1711 1199 594 655 256 253 2562 211720K 855 599 544 615 256 253 1656 146740K 427 299 519 590 256 253 1203 114280K 213 149 506 577 256 253 976 980160K 106 74 500 571 256 253 863 898320K 53 37 497 568 256 253 807 858Cost26002400220020001800NoDFTDFT160014001200100080060010K 20K 40K 80K 160K320KVolumeFigure 4.3: Relation between cost and volume.53
Page 1 and 2:
An Improved VLSI Test Economics Ana
Page 3 and 4:
Contents1 Introduction 11.1 Economi
Page 5 and 6:
List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57: Table 4.8: Parameters of time model
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,
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