An Improved VLSI Test Economics Analysis System - Laboratory for ...

Table 4.11: Result of analysis.Analysis result Notation no-DFT DFTprot prof 29.7M 38.8M nttotal cost cost 6.33M 6.26M nttotal cost per chip C 551 546 ntdevelopment cost Cd 370 361 ntmanufacturing cost Cm 153 158 nttesting cost Ct 27 27 ntdevelopment time Td 14 12 monthwafer test time Ttw 72 64 secondpre-burn-in test time Ttp 76 68 secondnal test time Ttb 80 72 secondrevenue R 36M 45M ntyield Y 0.9987 0.9851fault coverage FC 0.982 0.999defect level DL 227 11 DPMin this table, DFT will reduce the development time by 2 months, so the revenue increasesfrom 36M to 45M. The prot increases from 29.7M to 38.8M. Moreover, DFT increases area,so the yield reduces from 0.9987 to 0.9851. However, DFT increases fault coverage from0.982 to 0.999. The defect level reduces from 277 to 11 DPM. In this case, DFT increaseboth prot and quality.After that, we analysis the cost of dierent volume. As shown in Table 4.12, we comparecost for volume from 10k to 320k. Cd, Cm, and Ct are development, manufacturing, andtesting cost of no-DFT. C is total cost without DFT. Cd dft , Cm dft , Ct dft , and C dft are thecost with DFT. By comparing value of each stage cost with and without DFT, we can ndthat DFT decreases development and testing cost, but it increases manufacturing cost. Thus,as shown in last two column, DFT may not reduce the total cost when the volume is high.To analysis the case of larger chip, we multiply gate count of each block by ten. The costof this case is shown in Table 4.13. As shown in last two column, the total cost with DFTis higher than design without DFT, when the volume is high.Figure 4.3 shows the bar chart of cost and volume. By this chart, we can nd thethreshold volume 80K. We get benet form DFT, if the volume lower this threshold.To see why cost of DFT will not get benet any more, the cost ratio of each stage is shown52