An Improved VLSI Test Economics Analysis System - Laboratory for ...

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Table 4.6: Parameters of each block.block type gates nets I/Os gar nar tb1 logic 659 742 84 0.8 0.1 1e-3 3e-5 0.32 logic 624 924 10 0.8 0.1 1e-3 3e-5 0.33 logic 2192 2802 19 0.8 0.1 1e-3 3e-5 0.34 logic 2731 4021 17 0.8 0.1 1e-3 3e-5 0.35 logic 1512 2202 73 0.8 0.1 1e-3 3e-5 0.36 logic 2053 3803 14 0.8 0.1 1e-3 3e-5 0.37 logic 1365 1820 49 0.8 0.1 1e-3 3e-5 0.3Table 4.7: Parameters in cost model.Cost Model parameters notation valuesalary of Manager Ud mang 120000 ntmanagement time ratio Rd mang 0.2salary of each engineer Ud eng 40000 ntnumber of engineers Nd eng 1design hardware cost Cd hw 200000 ntdesign hardware depreciative rate Rd hw 0.02design software cost Cd sw 100000 ntdesign software depreciative rate Rd sw 0.02cost per prototyping C proto 1000000 ntnumber of prototyping N proto 3cost per wafer U wafer 100000 ntwafer radius R w 150 mmutilization of wafer R wutil 0.9cost of mask C mask 1000000 ntpackage cost parameter U p 10package cost parameter U pp 0.08wafer test equipment cost Ctw eq 200M ntequipment depreciative rate Rtw eq 0.4equipment maintenance cost Ctw mt 500K ntnumber of equipment test pins Ptw eq 256pre-burn-in test equipment cost Ctp eq 200M ntequipment depreciative rate Rtp eq 0.4equipment maintenance cost Ctp mt 100K ntnumber of equipment test pins Ptp eq 256nal test equipment cost Ctb eq 200M ntequipment depreciative rate Rtb eq 0.4equipment maintenance cost Ctb mt 1M ntnumber of equipment test pins Ptb eq 25650
Table 4.8: Parameters of time model.Time model parameters Notation Valuechip development time dG 0.0003block development time dg 0.0001wafer testing time tw 0.0006pre-burn-in testing time tw 0.0002nal testing time tw 0.0002Table 4.9: Parameters of market life model.market life model parameters Notation Valuemaximal revenue per month M r 3000000 ntmarket growing period M g 6 monthmarket maturity period M m 8 monthmarket decline period M d 2 monthTable 4.10: Parameters of quality model.Quality model parameters Notation Valuesensitive area as0 0.01sensitive area as1 5e-8sensitive area as2 8e-10defect density d 0.002 pots=mm 2wafer and nal test length ratio Rwb 0.3pre-burn-in and nal test length ratio Rpb 0.3fault coverage fc 1e-5burn-in test length Vb 400K51
Page 1 and 2:
An Improved VLSI Test Economics Ana
Page 3 and 4:
Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55: 4.3 Case StudyIn this section, a re
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,
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