An Improved VLSI Test Economics Analysis System - Laboratory for ...

Table 4.6: Parameters of each block.block type gates nets I/Os gar nar tb1 logic 659 742 84 0.8 0.1 1e-3 3e-5 0.32 logic 624 924 10 0.8 0.1 1e-3 3e-5 0.33 logic 2192 2802 19 0.8 0.1 1e-3 3e-5 0.34 logic 2731 4021 17 0.8 0.1 1e-3 3e-5 0.35 logic 1512 2202 73 0.8 0.1 1e-3 3e-5 0.36 logic 2053 3803 14 0.8 0.1 1e-3 3e-5 0.37 logic 1365 1820 49 0.8 0.1 1e-3 3e-5 0.3Table 4.7: Parameters in cost model.Cost Model parameters notation valuesalary of Manager Ud mang 120000 ntmanagement time ratio Rd mang 0.2salary of each engineer Ud eng 40000 ntnumber of engineers Nd eng 1design hardware cost Cd hw 200000 ntdesign hardware depreciative rate Rd hw 0.02design software cost Cd sw 100000 ntdesign software depreciative rate Rd sw 0.02cost per prototyping C proto 1000000 ntnumber of prototyping N proto 3cost per wafer U wafer 100000 ntwafer radius R w 150 mmutilization of wafer R wutil 0.9cost of mask C mask 1000000 ntpackage cost parameter U p 10package cost parameter U pp 0.08wafer test equipment cost Ctw eq 200M ntequipment depreciative rate Rtw eq 0.4equipment maintenance cost Ctw mt 500K ntnumber of equipment test pins Ptw eq 256pre-burn-in test equipment cost Ctp eq 200M ntequipment depreciative rate Rtp eq 0.4equipment maintenance cost Ctp mt 100K ntnumber of equipment test pins Ptp eq 256nal test equipment cost Ctb eq 200M ntequipment depreciative rate Rtb eq 0.4equipment maintenance cost Ctb mt 1M ntnumber of equipment test pins Ptb eq 25650