An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
Table 4.4: Circuit area of benchmarks.Name PIs POs FFs Gates Area A/G A Scan A diff A diff /FFss27 4 1 3 10 30 3.00 36 6 2.0s298 3 6 14 119 187 1.57 215 27 1.9s344 9 11 15 160 216 1.35 246 30 2.0s349 9 11 15 161 219 1.36 249 30 2.0s382 3 6 21 158 267 1.68 309 42 2.0s386 7 7 6 159 145 0.91 157 12 2.0s400 3 6 21 162 265 1.63 308 43 2.0s420 19 2 16 196 236 1.20 269 12 2.1s444 3 6 21 181 265 1.46 307 43 2.0s510 19 7 6 211 257 1.21 269 12 2.0s526n 3 6 21 194 304 1.56 346 42 2.0s526 3 6 21 193 297 1.54 340 43 2.0s641 35 24 19 379 255 0.67 293 38 2.0s713 35 23 19 393 253 0.64 292 39 2.1s820 18 19 5 289 283 0.98 293 10 2.0s832 18 19 5 287 284 0.99 294 10 2.0s838 35 2 32 390 480 1.23 545 65 2.0s953 16 23 29 395 526 1.33 584 58 2.0s1196 14 14 18 259 572 2.21 608 32 2.0s1238 14 14 18 508 580 1.14 616 36 2.0s1423 17 5 74 657 992 1.51 1141 149 2.0s1488 8 19 6 653 567 0.86 579 12 2.0s1494 8 19 6 647 569 0.88 581 12 2.0s5378 35 49 179 2779 2305 0.83 2665 360 2.0s9234 19 22 228 5597 2961 0.53 3385 1424 2.1s13207 31 121 669 7951 6545 0.82 7829 1284 1.9s15850 14 87 597 9772 6561 0.67 7635 1074 1.8s35932 35 320 1728 16065 21038 1.31 24517 3479 2.1s38417 28 106 1636 22179 19733 0.88 23028 3295 2.0s38584 12 278 1452 19253 20421 1.06 23292 2871 2.048
4.3 Case StudyIn this section, a real case of IEEE 1149.5 MTM-bus slave module [9] is used to analysis.Figure 4.2 shows the overall architecture of this chip. We describe the parameters requiredBlock 1 Block 2 Block 3 Block 4AddressComparatorCommandDecoderPacketCounterIEEE 1149.5ReceiverAddressPacketAddress 8 2 Command 7 1216ModeControlNumber1IPCMCLKMCTLMMD1MSD_sysMSD16411117Echo DataIEEE 1149.5Transmitter5511ControlSignalRegister&ControllerBlock 616SignatureModuleRegister39 Status16TMS Data&Test PatternIEEE1149.1Data TransferPort44144TCKTMSTRSTTDITDOBlock 5Block 7Figure 4.2: Architecture of IEEE 1149.5 MTM-bus slave module.by our analysis from Table 4.5 to 4.10.Table 4.5: Parameters of chip.Chip level parameters Notation no-DFT DFTchip area A 11.2 12.3 mm 2chip gates G 11136 12249chip nets N 16314 17945chip pins P 48 52chip testability TB 0.3 0.55chip complexity , 0.8 0.96After applying all parameters to the system, we invoke the analysis engine and get resultswhich is shown in Table 4.11. The results include value of with and without DFT. As shown49
- Page 3 and 4: Contents1 Introduction 11.1 Economi
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9 and 10: costs are summed as the total cost.
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- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27 and 28: where K dsgn is user dened design c
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
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- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53: Table 4.3: Fault coverage and test
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65 and 66: Design space cost for rent building
- Page 67 and 68: Revenue with DFT design:R dft = 1 2
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
- Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
- Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
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- Page 77 and 78: Kd mp : user-dened man-power cost .
- Page 79: [13] R. G. Bennetts, C. M. Maunder,
4.3 Case StudyIn this section, a real case of IEEE 1149.5 MTM-bus slave module [9] is used to analysis.Figure 4.2 shows the overall architecture of this chip. We describe the parameters requiredBlock 1 Block 2 Block 3 Block 4AddressComparatorCommandDecoderPacketCounterIEEE 1149.5ReceiverAddressPacketAddress 8 2 Command 7 1216ModeControlNumber1IPCMCLKMCTLMMD1MSD_sysMSD16411117Echo DataIEEE 1149.5Transmitter5511ControlSignalRegister&ControllerBlock 616SignatureModuleRegister39 Status16TMS Data&<strong>Test</strong> PatternIEEE1149.1Data TransferPort44144TCKTMSTRSTTDITDOBlock 5Block 7Figure 4.2: Architecture of IEEE 1149.5 MTM-bus slave module.by our analysis from Table 4.5 to 4.10.Table 4.5: Parameters of chip.Chip level parameters Notation no-DFT DFTchip area A 11.2 12.3 mm 2chip gates G 11136 12249chip nets N 16314 17945chip pins P 48 52chip testability TB 0.3 0.55chip complexity , 0.8 0.96After applying all parameters to the system, we invoke the analysis engine and get resultswhich is shown in Table 4.11. The results include value of with and without DFT. As shown49
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