An Improved VLSI Test Economics Analysis System - Laboratory for ...

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patterns into ip-ops, the test length (V ) should be estimated as(N FF V comb if N FF < 100;V =100 V comb if N FF > 100;(4.2)where V comb is number of test vectors generated by ATALANTA, and N FF is number ofip-ops of circuits. It is assumed that multiple scan chains are used to guarantee the lengthof each scan chain never exceed 100. Thus, the number of shifts per vector is 100 insteadof N FF , if N FF> 100. Then, similar process as no scan circuit fc estimation is used tocalculate fc scan . The results are also shown in the same table. Additionally, this table liststest generation time of both scan and no scan circuits.From this table, we nd two things:☞ Scan greatly reduces test generation time. As shown in the table, circuit with no scanmay need even weeks to generate high fault coverage patterns. However, this time isreduced to almost zero in scan-added circuits.☞ Similar circuits have close fc . This result can be obtained by comparing fc of thepairs of circuits: (s382, s400), (s641, s713), (s820, s832), (s1196, s1238), and (s1488,s1494). They are synthesized from the same function as listed in Table 4.1.<strong>An</strong>other experiment is comparing random pattern and scan design. Random pattern donot need test generation time, and scan design use almost zero time to generation pattern.As shown in Table4.3, the test length of random pattern is much longer than scan design.4.2.2 AreaThe synthesized results of both scan and no scan benchmark circuits are listed in Table 4.4.This table also include evaluated result of gate area ratio (A/G). The target process isTSMC.6 DPDM process.Result of this table shows that gate area ratio is a value typically between 0.8 to 106.Moreover, scan circuit area is proportional to number of ip-ops in the circuit. The totalarea, after scan insertion, can be expressed asA scan = A +2N FF ; (4.3)where A is original circuit area, and N FF is number of ip-ops in the circuit.46
Table 4.3: Fault coverage and test length of random pattern.Name Vectors max fc scan clockss27 88 1 18s208.1 1000 1 280s298 1e7 0.93 420s344 1000 1 330s349 2000 1 345s382 1e8 0.21 210s386 1e8 0.98 483s400 1e8 0.21 651s444 1e8 0.20 672s526 1e8 0.14 1344s641 1e5 0.99 1007s713 1e5 0.99 989s820 1e8 0.56 570s832 1e8 0.57 555s953 100 1 2581s1196 1e7 1 2484s1238 1e7 1 2794s1488 1e8 0.98 744s1494 1e8 0.98 762s35932 1e5 0.97 670047
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51: Table 4.2: Fault coverage parameter
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,

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