An Improved VLSI Test Economics Analysis System - Laboratory for ...

patterns into ip-ops, the test length (V ) should be estimated as(N FF V comb if N FF < 100;V =100 V comb if N FF > 100;(4.2)where V comb is number of test vectors generated by ATALANTA, and N FF is number ofip-ops of circuits. It is assumed that multiple scan chains are used to guarantee the lengthof each scan chain never exceed 100. Thus, the number of shifts per vector is 100 insteadof N FF , if N FF> 100. Then, similar process as no scan circuit fc estimation is used tocalculate fc scan . The results are also shown in the same table. Additionally, this table liststest generation time of both scan and no scan circuits.From this table, we nd two things:☞ Scan greatly reduces test generation time. As shown in the table, circuit with no scanmay need even weeks to generate high fault coverage patterns. However, this time isreduced to almost zero in scan-added circuits.☞ Similar circuits have close fc . This result can be obtained by comparing fc of thepairs of circuits: (s382, s400), (s641, s713), (s820, s832), (s1196, s1238), and (s1488,s1494). They are synthesized from the same function as listed in Table 4.1.Another experiment is comparing random pattern and scan design. Random pattern donot need test generation time, and scan design use almost zero time to generation pattern.As shown in Table4.3, the test length of random pattern is much longer than scan design.4.2.2 AreaThe synthesized results of both scan and no scan benchmark circuits are listed in Table 4.4.This table also include evaluated result of gate area ratio (A/G). The target process isTSMC.6 DPDM process.Result of this table shows that gate area ratio is a value typically between 0.8 to 106.Moreover, scan circuit area is proportional to number of ip-ops in the circuit. The totalarea, after scan insertion, can be expressed asA scan = A +2N FF ; (4.3)where A is original circuit area, and N FF is number of ip-ops in the circuit.46