An Improved VLSI Test Economics Analysis System - Laboratory for ...

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4.2.1 Fault CoverageFault coverage is a function of test length as discussion in Section 2.6. Now, we try to ndparameter of this function.0.90.80.7Fault Coverage (FC)0.60.50.40.30.20.10−0.10 20 40 60 80 100 120 140 160 180 200<strong>Test</strong> Vector Length (V)Figure 4.1: Experimental and approximated result of fault coverage.In our experiment, ISCAS'89 benchmark circuits are applied to a sequential ATPG, called"HITEC". The fault coverage of each test length is obtained, as shown in Figure 4.1. Then,equationFC(V )=1, e , fcV(4.1)is used to t the experimental results. This tting curve is also shown in the same gure.Least square tting algorithm are adopted to evaluate fc of the function. Because we generallyuse only high fault coverage results, our tting process eliminates those data which faultcoverage fewer than 0.7. All experimental and evaluated results are included in Appendix B,and summarized in Table 4.2.Moreover, we consider that scan is added into the circuits. ISCAS'89 SCAN circuits areapplied to a combinational ATPG tool, called "ATALANTA". Because scan test need shift44
Table 4.2: Fault coverage parameter approximation.Name PIs POs D-FFs Gates Depth fc Tt gen fc scan Tt gen scans27 4 1 3 10 - 0.1204 0 1.9800 0s208.1 11 2 8 96 - 0.2404 10640 1.0201 0.03s298 3 6 14 119 8 0.0045 3718 0.0177 0.03s344 9 11 15 160 6 0.0408 11650 0.1633 0.05s349 9 11 15 161 6 0.0536 51082 0.0309 0.02s382 3 6 21 158 11 0.0016 570781 0.0080 0.03s386 7 7 6 159 5 0.0173 19 0.0098 0.07s400 3 6 21 162 11 0.0013 77953 0.0088 0.03s444 3 6 21 181 11 0.0010 57739 0.0143 0.03s526 3 6 21 193 11 0.0009 57739 0.0037 0.08s641 35 24 19 379 6 0.0285 13 0.0054 0.11s713 35 23 19 393 6 0.0378 18 0.0054 0.18s820 18 19 5 289 4 0.0044 543 0.0070 0.15s832 18 19 5 287 4 0.0037 789 0.0068 0.20s953 16 23 29 395 - 0.2814 155 0.0020 2.03s1196 14 14 18 259 4 0.0074 2 0.0019 0.35s1238 14 14 18 508 4 0.0069 8 0.0018 0.62s1488 8 19 6 653 5 0.0075 1318 0.0056 0.28s1494 8 19 6 647 5 0.0076 678 0.0058 0.33s35932 35 320 1728 16065 35 0.0620 12669 0.0016 7245
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49: Table 4.1: ISCAS'89 benchmark circu
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,

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