An Improved VLSI Test Economics Analysis System - Laboratory for ...

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3 System Development 353.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.2 Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.3 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.4 Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Experimental Result 424.1 ISCAS89 Benchmark Overview . . . . . . . . . . . . . . . . . . . . . . . . . 424.2 Model Parameters Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 424.2.1 Fault Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.2.2 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.3 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 Conclusions 56A Summary of All Model 58A.1 Cost Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58A.1.1 Developmental cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58A.1.2 Manufacturing Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59A.1.3 Testing Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59A.2 Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60A.3 Quality Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60A.4 Market Life Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60B Fault Coverage Approximation of ISCAS'89 Benchmark 62ii
List of Figures2.1 Area relation between core and pads: (a) maximal utilization, (b) core bounded,(c) pads bounded. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Relation of models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3 Hierarchical structure of Cost Model. . . . . . . . . . . . . . . . . . . . . . . 162.4 How is cost impacted by time? . . . . . . . . . . . . . . . . . . . . . . . . . . 172.5 Continuous cost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.6 General develop process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.7 (a) Empirical result of FC v.s V, (b) Goel's estimation. . . . . . . . . . . . . 292.8 The market life cycle model. . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.9 DFT impact on parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.1 Architecture of ESTEEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.2 Analysis ow of ESTEEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.3 File Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.4 Model Editor: (a) block parameters, (b) fault coverage and test length. . . . 393.5 Result Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.1 Experimental and approximated result of fault coverage. . . . . . . . . . . . 444.2 Architecture of IEEE 1149.5 MTM-bus slave module. . . . . . . . . . . . . . 494.3 Relation between cost and volume. . . . . . . . . . . . . . . . . . . . . . . . 534.4 Stage cost ratio of 2k volume: (a) Original, (b) DFT. . . . . . . . . . . . . . 544.5 Stage cost ratio of 320k volume: (a) Original, (b) DFT. . . . . . . . . . . . . 54iii
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3: Contents1 Introduction 11.1 Economi
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56:
4.3 Case StudyIn this section, a re
Page 57 and 58:
Table 4.8: Parameters of time model
Page 59 and 60:
Table 4.12: Cost of dierent volume.
Page 61 and 62:
in Figure 4.4 for 2K volume and Fig
Page 63 and 64:
circuits were translated to Verilog
Page 65 and 66:
Design space cost for rent building
Page 67 and 68:
Revenue with DFT design:R dft = 1 2
Page 69 and 70:
1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72:
Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74:
Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76:
1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78:
Kd mp : user-dened man-power cost .
Page 79:
[13] R. G. Bennetts, C. M. Maunder,
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