An Improved VLSI Test Economics Analysis System - Laboratory for ...

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Figure 3.3: File Manager.3.3 User InterfaceThe user interface includes three programs: File Manager, Model Editor and Result Display.File Manager help user manage their projects as general les. Figure 3.3 shows the FileManager. In this program, users can create, remove, copy and open their own les anddirectories. Its operation is similar to general le managers. This program is written by Perland Javascript, because Perl is excellent in handling WWW data and Javascript can easilyproduce dynamic homepages.Once a le is opened, model editor will be invoked to read data from selected project.Thus, user can modify parameters and equations of models to match their design. Ourprevious version is written by pure Java. But, Java is restricted by it's low per<strong>for</strong>mance andstability. Too large Java applet will slow down the speed of browser and may lead to crash.This version is written by Perl, Java, and Javascript. Java is only used to handle someactive display that Javascript is not powerful enough to do. Figure 3.4(a) shows the appletof block parameters. It uses card layout. User can indicate how many blocks in the chip,and modify parameters of each block easily. Figure 3.4(b) shows the applet of quality model.38
(a)(b)Figure 3.4: Model Editor: (a) block parameters, (b) fault coverage and testlength.39
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
Page 41 and 42: Chapter 3System DevelopmentIn our s
Page 43: the browser.3.2 Analysis FlowConnec
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,

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