An Improved VLSI Test Economics Analysis System - Laboratory for ...

More documents

Recommendations

Info

future work is to quantify those eects. In Chapter 4, we will shown our experiment of fullscan design, and obtain the change of parameters in scan design.34
Chapter 3System DevelopmentIn our study, a software system, called "Evaluation System for TEst Engineering (ES-TEEM)", has been developed. The goal of this system is to nd maximal prot test strategyin the early stage of the design.This system is intended for use by industry, because we try to collect design data fromthem for more precise models in the future. Thus, the hole system is designed to be accessedfrom Internet. User can connect to our system form arbitrary computer via web browser.Besides, the system also provide security to protect data of each user.Because the cost strongly depends on the design ow of each company, the users mustmodify equations and parameters in our models to match the condition of their companies.The design of the user interface needs to be more exible that user can easily modify theequations and parameters on line. Moreover, user can customize their own default modelequations and parameters for convenience.In the rest of this chapter, we describe details of the ESTEEM system. The systemarchitecture will be introduced in the rst section. Then, we shows the analyze ow of oursystem in the second section. The third section demos the user interface and the last sectionexplains the algorithm of the analyze engine program in our system.3.1 System ArchitectureThe architecture of the whole system is shown in Figure 3.1. Our system includes programsin server and client. Some of those programs are well-developed packages, so we just needto custom them to t our system.35
Page 1 and 2: An Improved VLSI Test Economics Ana
Page 3 and 4: Contents1 Introduction 11.1 Economi
Page 5 and 6: List of Figures2.1 Area relation be
Page 7 and 8: Chapter 1IntroductionFrom business
Page 9 and 10: costs are summed as the total cost.
Page 11 and 12: TEEM)" for VLSI test strategy plann
Page 13 and 14: Chapter 2Economic ModelsIn this cha
Page 15 and 16: 2.2 Circuit DescriptionThis section
Page 17 and 18: Gate Area Ratio (gar): Average gate
Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
Page 21 and 22: The proposed economic models consis
Page 23 and 24: However, cost is greatly impacted b
Page 25 and 26: Type II: C = UR f N tThis equation
Page 27 and 28: where K dsgn is user dened design c
Page 29 and 30: where U space is price of the build
Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
Page 33 and 34: is aected by gate count, complexity
Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
Page 37 and 38: In our study, we run ATPG for ISCAS
Page 39: asR dft = 1 2 (TMM grow +2TMM matu
Page 43 and 44: the browser.3.2 Analysis FlowConnec
Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
Page 47 and 48: If this equation is a function, for
Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
Page 51 and 52: Table 4.2: Fault coverage parameter
Page 53 and 54: Table 4.3: Fault coverage and test
Page 55 and 56: 4.3 Case StudyIn this section, a re
Page 57 and 58: Table 4.8: Parameters of time model
Page 59 and 60: Table 4.12: Cost of dierent volume.
Page 61 and 62: in Figure 4.4 for 2K volume and Fig
Page 63 and 64: circuits were translated to Verilog
Page 65 and 66: Design space cost for rent building
Page 67 and 68: Revenue with DFT design:R dft = 1 2
Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
Page 77 and 78: Kd mp : user-dened man-power cost .
Page 79: [13] R. G. Bennetts, C. M. Maunder,

An Improved VLSI Test Economics Analysis System - Laboratory for ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?