An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
ure 2.7(a). An equation is proposed to model the result asFC =1, e ,V (2.51)where V is test length and is equation parameter for tting various circuits. This equationis rational because fault coverage raise fast in the beginning but very slow while it near 100percent. In addition, if redundant faults are regardless, fault coverage must reach 100%whentest length go to innity.Goel proposed another method to model empirical results [22]. He use two piece ofcurve to t the results, as shown in Figure 2.7(b) one is exponential and another is linear.A threshold test length V th divides test generation into two phase. In phase I, The sameequation as our model is used for estimation. When test generation enters phase II, faultcoverage is modeled as a liner equation:FC = FC 0 + kV (2.52)Besides, Kim proposed a more exible model [5]:FC = FC 0 + ke ,V ; (2.53)and estimated value is limited between upper bound (UB) and lower bound (LB).All these models have the same problem: How to determine the parameters , k andFC 0 for our circuit when the netlist still not available? Goel proved that k is a constantform four experience, but it is obviously irrational. In fact these parameters are stronglydepend on the structure of circuit. They indicate how ease the faults to be detected. Thus,user can estimate their value from chip testability (TB). For example, we can assume theyall proportional to TB.Cheng proved that it takes at most D 2 L test length to detect a single stuck-at faultwhere D is sequential depth and L is interval loop length [23]. Although this is a upperbound of each fault. It implies that how hard the fault in circuit can be detected since testlength mainly aected by these hard to detected faults. Thus, if user have rational value ofD and L for their circuit, our parameters also can be estimated from this upper bound. Forexample, we can assume they are all inverse proportional to D 2 L .30
In our study, we run ATPG for ISCAS89 benchmark circuits to obtain relation of FCand V in Section 4.2.1. We choose (2.52) to t curve of our experience because that equationuse only one parameter . This can simple our comparison among the circuits. Then, ofthese circuit were estimated using least square curve tting algorithm.After the relation between fault coverage and test length is established, we must decidethe value of them to archive minimal cost. Kim [5] proposed to set test length at a thresholddF C=dV value [5], but fault coverage in this threshold is usually not enough. Thus, we onlysupport the procedure: User may decide test length, estimate FC, then check if DL satisfyspec, recursively.Once the test length is decided, it will be sent to time model to estimate test time. Then,test cost will be evaluated according to test time.Now, there is another problem: how to balance test length of three test stages to achieveminimal total cost. As previous discussion, the earlier defect chips are eliminated, the fewerpenalty cost of those chips is needed. Lower defect level of each test stage will reduce chipmanufacturing cost. For example, we assume wafer cost can eliminate almost all defect dies,so we don't need to pay any package cost, pre-burn-in testing cost and nal testing cost forthose defect dies. The total cost is therefore reduced. However, lower defect level meanshigher testing cost since longer test length for higher fault coverage is needed.Moore proposed a program to model testing cost of the whole system manufactured inDEC production process [24]. Then, this program determine the most economic test processwithout sacricing defect level. Their experience result shows when defects per unit (DPU)is low, the optimal test process is system test only. But in high DPU, optimal process iscompound of chip test and system test. The same idea can be used in our three test stages.When yield is high, we can reduce test length in early test stages to reduce the test cost. Incontract, while low yield, wafer test needs higher fault coverage to reduce cost of defect dies.In addition, two parameters (R wf , R pf ) are proposed as the ratio of the test length ofeach test stage. It is expressed asV w = R wf V f ;V p = R pf V p ;(2.54)where V w , V p , and V f is test length of the wafer, pre-burn-in, and nal test. As above31
- Page 1 and 2: An Improved VLSI Test Economics Ana
- Page 3 and 4: Contents1 Introduction 11.1 Economi
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9 and 10: costs are summed as the total cost.
- Page 11 and 12: TEEM)" for VLSI test strategy plann
- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27 and 28: where K dsgn is user dened design c
- Page 29 and 30: where U space is price of the build
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65 and 66: Design space cost for rent building
- Page 67 and 68: Revenue with DFT design:R dft = 1 2
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
- Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
- Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
- Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
- Page 77 and 78: Kd mp : user-dened man-power cost .
- Page 79: [13] R. G. Bennetts, C. M. Maunder,
In our study, we run ATPG <strong>for</strong> ISCAS89 benchmark circuits to obtain relation of FCand V in Section 4.2.1. We choose (2.52) to t curve of our experience because that equationuse only one parameter . This can simple our comparison among the circuits. Then, ofthese circuit were estimated using least square curve tting algorithm.After the relation between fault coverage and test length is established, we must decidethe value of them to archive minimal cost. Kim [5] proposed to set test length at a thresholddF C=dV value [5], but fault coverage in this threshold is usually not enough. Thus, we onlysupport the procedure: User may decide test length, estimate FC, then check if DL satisfyspec, recursively.Once the test length is decided, it will be sent to time model to estimate test time. Then,test cost will be evaluated according to test time.Now, there is another problem: how to balance test length of three test stages to achieveminimal total cost. As previous discussion, the earlier defect chips are eliminated, the fewerpenalty cost of those chips is needed. Lower defect level of each test stage will reduce chipmanufacturing cost. For example, we assume wafer cost can eliminate almost all defect dies,so we don't need to pay any package cost, pre-burn-in testing cost and nal testing cost <strong>for</strong>those defect dies. The total cost is there<strong>for</strong>e reduced. However, lower defect level meanshigher testing cost since longer test length <strong>for</strong> higher fault coverage is needed.Moore proposed a program to model testing cost of the whole system manufactured inDEC production process [24]. Then, this program determine the most economic test processwithout sacricing defect level. Their experience result shows when defects per unit (DPU)is low, the optimal test process is system test only. But in high DPU, optimal process iscompound of chip test and system test. The same idea can be used in our three test stages.When yield is high, we can reduce test length in early test stages to reduce the test cost. Incontract, while low yield, wafer test needs higher fault coverage to reduce cost of defect dies.In addition, two parameters (R wf , R pf ) are proposed as the ratio of the test length ofeach test stage. It is expressed asV w = R wf V f ;V p = R pf V p ;(2.54)where V w , V p , and V f is test length of the wafer, pre-burn-in, and nal test. As above31
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