An Improved VLSI Test Economics Analysis System - Laboratory for ...

ure 2.7(a). An equation is proposed to model the result asFC =1, e ,V (2.51)where V is test length and is equation parameter for tting various circuits. This equationis rational because fault coverage raise fast in the beginning but very slow while it near 100percent. In addition, if redundant faults are regardless, fault coverage must reach 100%whentest length go to innity.Goel proposed another method to model empirical results [22]. He use two piece ofcurve to t the results, as shown in Figure 2.7(b) one is exponential and another is linear.A threshold test length V th divides test generation into two phase. In phase I, The sameequation as our model is used for estimation. When test generation enters phase II, faultcoverage is modeled as a liner equation:FC = FC 0 + kV (2.52)Besides, Kim proposed a more exible model [5]:FC = FC 0 + ke ,V ; (2.53)and estimated value is limited between upper bound (UB) and lower bound (LB).All these models have the same problem: How to determine the parameters , k andFC 0 for our circuit when the netlist still not available? Goel proved that k is a constantform four experience, but it is obviously irrational. In fact these parameters are stronglydepend on the structure of circuit. They indicate how ease the faults to be detected. Thus,user can estimate their value from chip testability (TB). For example, we can assume theyall proportional to TB.Cheng proved that it takes at most D 2 L test length to detect a single stuck-at faultwhere D is sequential depth and L is interval loop length [23]. Although this is a upperbound of each fault. It implies that how hard the fault in circuit can be detected since testlength mainly aected by these hard to detected faults. Thus, if user have rational value ofD and L for their circuit, our parameters also can be estimated from this upper bound. Forexample, we can assume they are all inverse proportional to D 2 L .30