An Improved VLSI Test Economics Analysis System - Laboratory for ...

is aected by gate count, complexity and reusability of circuit. The test generation time isaected by testability and verication time depends on gate count and testability. Thus, theproposed development time isT d = e td GG,(1,TB) +Xper blocke td gg(1,)(1,tb) : (2.44)The rst term of this equation indicates the time needed to integrate blocks into the chip. Inthis term, G is total gate count, , is chip complexity, and TM is chip testability. The secondterm sums development time of each block where g is block gate count, is block complexity, is block complexity, and tm is block testability. The idea of exponential function is gotfrom Wei [6], and the impact of engineers and tools are implied in td G and Td g .Subsequently, we discuss testing time of each test stage. The testing time is proportionalto test length of each stage, so testing time can be expressed asTt w = tw V w ;Tt p = tp V p ;(2.45)Tt f = tb V f ;where Tt w , Tt p , Tt f are the test time of wafer, pre-burn-in, and nal test. V w , V p , and V fare the test length of each test stage, they will be estimated in Quality Model. tw , tp ,and tb are ratio of testing time and test length. This three parameters are depend on testequipment and chip frequency.2.6 Quality ModelQuality includes performance, reliability and defect level. Some test methodologies willlead to performance lose because the DFT circuit may cause extra delay on critical path.However, this is too complex for us to model it in early design stage. We only estimatedefect level as quality of testing process in our study.Defect level can be converted to revenue/cost. Low defect level means high quality. Hightquality implies high price, and few penalty cost in system integration. However, this analysisneed to pass multiple projects in a long time, so we just only estimate defect level in ourstudy. User may regard defect level as a constrain, then, chooses a testing strategy to meetit.27