An Improved VLSI Test Economics Analysis System - Laboratory for ...

where Ct f eq is price, Rt f eq is depreciative rate, Ct p mt is maintenance cost, and Pt p eqis number of test pins of each package test equipment. Similarly, Ct f eq is price, Rt f eqis depreciative rate, Ct f mt is maintenance cost, and Pt f eq is number of test pins of eachburn-in test equipment. Tt p is average package test time and Tt f is average burn-in testtime of each chip. Finally, Kt p and Kt f is user dened wafer test and package test cost.2.5 Time ModelIn this model, we estimate time of development and each test stage. The development timewill impact two cost. Development cost is aected by the development time because mostof the item cost in development depends on this time. Another impact is revenue. If thedevelopment time is reduce, it implies shorter time to market. As discussed in Market LifeModel, reduce time to market will increase revenue.However, it's a critical problem to estimate development time. This parameter is affectedby not only circuit itself but also engineers and tools. The ability of engineers andfacility of tools strongly depend on each company. Moreover, the number of engineers alsoeect development time. More engineers will reduce development time, but this impact hasmarginal eect. Beside, more engineers needs more salary each month. All those conditionsare too complex to model in detail, so we leave the trade-o of those conditions to managers.Therefore, the proposed model may use some abstract parameters to t the conditions ofthe companies.Design CycleVerify CycleFloor Plain Circuit Design Test Generation Prototyping Verification Tape OutFigure 2.6: General develop process.General development process is shown in Figure 2.6. The development time has to modelthe time complexity ofeach development stage and iterations of each loop. The design time26