An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
2.4.4 Manufacturing CostManufacturing cost means cost per chip during manufacturing phase. This cost consists ofnon-recurring part and recurring part. As shown in Section 2.4.2, the manufacturing costcan be estimated as (2.22). For simplicity, it is assumed that our company is a design house.Designs are sent to foundry for manufacturing. Therefore, we don't need to consider detailedcost in factory. Manufacturing cost can be express asCm = C mask =N v + U die + U pack + Km; (2.35)where C mask is mask cost, U die is cost per die, U pack is package cost of each chip, and Km isuser dened manufacturing cost.Die cost can be estimated from wafer cost (U wafer ) and number of good dies per wafer(n g ).Let Y be the estimated yield, d be the wafer diameter, and util be the utilization of wafer,then, number of good dies per wafer can be calculated as util (d=2) 2n g = Y : (2.36)AThus, die cost can be estimated asU die = U wafer =n g = 4AU wafer util d 2 Y(2.37)Although package cost primary depends on the package type, the more chip pins thehigher pin density package type is needed. Therefore, the package cost can be modeled asU pack = p + pp P; (2.38)where p and pp need to be estimated from exact cost and pins per package type.2.4.5 Testing CostGeneral test process includes wafer test, pre-burn-in test, and nal test. Thus, our testingcost is estimated asCt = Ct w + Ct p + Ct f + Kt; (2.39)where Ct w , Ct p , and Ct ftesting cost.is cost of wafer, pre-burn-in , and nal test. Kt is user dened24
Table 2.6: N pass and N v ratio.Before Test Wafer Test Pre-burn-in Test Final TestN pass N N w = N(Y + DL w ) N p = N(Y + DL p ) N f = N(Y + DL f )Y +DL fY +DL f11Y +DLN pass =N wv Y +DL fY +DL fSimplied 1=Y 1 1 1As shown in Table 2.6, N is total manufacturing chips. N w , N p and N f is number ofchips pass wafer, pre-burn-in, and nal test. N v is number of chips delivered to market.DL w , DL p and DL f is defect level after this three test stages. It is assumed that Y DL f ,thus,N v = N f = N(Y + DL f )=NY: (2.40)Only the chips delivered to market can gain revenue, so the cost of eliminated chips musttransfer to the passed chips.Therefore cost of each stage needs to multiply the factorN pass =N v to include the eliminated chips cost. As shown in the same table, this factor issimplied to 1=Y , 1, and 1 for this three test stages.If we use type II cost model, and eliminate training cost of equipment, wafer test costcan be estimated asCt w = Xper tw eqCt w eq Rt w eq + Ct w mtP Tt w =Y + Kt w ; (2.41)Pt w eqwhere Ct w eq is price of wafer test equipment. Rt w eq is depreciative rate, Ct w mt is maintenancecost, and Pt w eq is number of test pins of the test equipment. Moreover, P is chippins and Y is yield. Tt w is average wafer test time of each chip. This time will be estimatedin Time Model. Finally, Kt w is user dened wafer test cost.Similar equations are used to estimate the pre-burn-in and nal cost asCt p = Xper tp eqCt p eq Rt p eq + Ct p mtPt p eqP Tt p + Kt p ; (2.42)and XCt f =per tf eqCt f eq Rt f eq + Ct f mtP Tt f + Kt f ; (2.43)Pt f eq25
- Page 1 and 2: An Improved VLSI Test Economics Ana
- Page 3 and 4: Contents1 Introduction 11.1 Economi
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9 and 10: costs are summed as the total cost.
- Page 11 and 12: TEEM)" for VLSI test strategy plann
- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27 and 28: where K dsgn is user dened design c
- Page 29: where U space is price of the build
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65 and 66: Design space cost for rent building
- Page 67 and 68: Revenue with DFT design:R dft = 1 2
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
- Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
- Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
- Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
- Page 77 and 78: Kd mp : user-dened man-power cost .
- Page 79: [13] R. G. Bennetts, C. M. Maunder,
Table 2.6: N pass and N v ratio.Be<strong>for</strong>e <strong>Test</strong> Wafer <strong>Test</strong> Pre-burn-in <strong>Test</strong> Final <strong>Test</strong>N pass N N w = N(Y + DL w ) N p = N(Y + DL p ) N f = N(Y + DL f )Y +DL fY +DL f11Y +DLN pass =N wv Y +DL fY +DL fSimplied 1=Y 1 1 1As shown in Table 2.6, N is total manufacturing chips. N w , N p and N f is number ofchips pass wafer, pre-burn-in, and nal test. N v is number of chips delivered to market.DL w , DL p and DL f is defect level after this three test stages. It is assumed that Y DL f ,thus,N v = N f = N(Y + DL f )=NY: (2.40)Only the chips delivered to market can gain revenue, so the cost of eliminated chips musttransfer to the passed chips.There<strong>for</strong>e cost of each stage needs to multiply the factorN pass =N v to include the eliminated chips cost. As shown in the same table, this factor issimplied to 1=Y , 1, and 1 <strong>for</strong> this three test stages.If we use type II cost model, and eliminate training cost of equipment, wafer test costcan be estimated asCt w = Xper tw eqCt w eq Rt w eq + Ct w mtP Tt w =Y + Kt w ; (2.41)Pt w eqwhere Ct w eq is price of wafer test equipment. Rt w eq is depreciative rate, Ct w mt is maintenancecost, and Pt w eq is number of test pins of the test equipment. Moreover, P is chippins and Y is yield. Tt w is average wafer test time of each chip. This time will be estimatedin Time Model. Finally, Kt w is user dened wafer test cost.Similar equations are used to estimate the pre-burn-in and nal cost asCt p = Xper tp eqCt p eq Rt p eq + Ct p mtPt p eqP Tt p + Kt p ; (2.42)and XCt f =per tf eqCt f eq Rt f eq + Ct f mtP Tt f + Kt f ; (2.43)Pt f eq25
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