An Improved VLSI Test Economics Analysis System - Laboratory for ...
An Improved VLSI Test Economics Analysis System - Laboratory for ... An Improved VLSI Test Economics Analysis System - Laboratory for ...
Let R dp be depreciative rate, the depreciation dierence ratio function can be estimatedasf dp (R dp )=1, (1 , R dp ) T d: (2.27)Then, equipment cost (C equip ) can be estimated asXCd equip =U hw f dp (R hw dp )+U hw mt T d + C hw traineach Xhw+U sw f dp (R sw dp )+U sw mt ) T d + C sw train ;each sw(2.28)where U hw is price, R hw dp is depreciative rate, U hw mt is maintenance cost andC sw train is training cost of the hardware. Similarly, U sw is price, R sw dp is depreciativerate, U sw mt is maintenance cost and C sw train is training cost of the software.Moreover, if we use type II cost model for price cost to eliminate exponential term,the estimation equation can be given byXCd equip =(U hw R hw dp + U hw mt ) T d + C hw traineach Xhw+(U sw R sw dp + U sw mt ) T d + C sw train ;each sw(2.29)Design Space (Cd space ): Some companies rent the departments of their oce, but some buyit. Thus, two equations are developed for these situations. For the companies whichrent the departments, let Rd space be the design department space ratio of the wholerented space, U rent be annual rent, and T d be the development time. The space costis then given bywhere K space is user-dened space cost.Cd space = Rd space U rent T d + K space ; (2.30)If the companies buy the buildings of their oce, the interest and the appreciationof land should be taken into account. As our type III cost model, the space cost canbe expressed asCd space = Rd space U space [(1 + R int ) T d, (1 + R sp ap ) T d]+K space ; (2.31)22
where U space is price of the building, R int is the interest ratio, and R sp ap is appreciativerate of the space.Prototypes (C proto ): There are three kinds of prototypes: FPGA, Emulator and Fab. Prototypingmay repeat many rounds until the design is well veried. For FPGA andemulator prototyping, each round needs only time to recongure hardware. If thistwo methods are used for prototyping, design equipment cost have to include cost ofFPGA or emulator. But for fab prototyping, each round needs vary large productioncost. Let N proto be the number of prototyping rounds, and U proto be the cost perround. Then, the prototype cost is given byC proto = N proto U proto + K proto ; (2.32)where K proto denotes user dened prototype cost.Cost per round of fab prototyping includes general chip cost, such as mask, wafer, andpackage cost. Non-recurring cost dominates this cost because manufacturing volumeper round is very small. We can eliminate the wafer cost and the package cost ofprototypes. Moreover, main non-recurring cost is the mask cost. The prototypescost can be estimated asC proto = N proto U mask + K proto ; (2.33)where U mask is the mask cost per round.Management CostManagers always manage several projects in the same time. A time ratio, denoted as R mang ,is used to represent the eorts that the manager involves in this project. Therefore, themanagement cost in the development phase is modeled asCd mang =Xper manager(U mang R mang T d )+Kd mang ; (2.34)where R mang is the time ratio of management man-power which the manager involved in thisproject and U mang is the salary of the manager.Based on above description, the development cost (Cd) can be calculated according to(2.23).23
- Page 1 and 2: An Improved VLSI Test Economics Ana
- Page 3 and 4: Contents1 Introduction 11.1 Economi
- Page 5 and 6: List of Figures2.1 Area relation be
- Page 7 and 8: Chapter 1IntroductionFrom business
- Page 9 and 10: costs are summed as the total cost.
- Page 11 and 12: TEEM)" for VLSI test strategy plann
- Page 13 and 14: Chapter 2Economic ModelsIn this cha
- Page 15 and 16: 2.2 Circuit DescriptionThis section
- Page 17 and 18: Gate Area Ratio (gar): Average gate
- Page 19 and 20: (a) (b) (c)Figure 2.1: Area relatio
- Page 21 and 22: The proposed economic models consis
- Page 23 and 24: However, cost is greatly impacted b
- Page 25 and 26: Type II: C = UR f N tThis equation
- Page 27: where K dsgn is user dened design c
- Page 31 and 32: Table 2.6: N pass and N v ratio.Bef
- Page 33 and 34: is aected by gate count, complexity
- Page 35 and 36: FC100%FC100%Phase IPhase IIVV(a)(b)
- Page 37 and 38: In our study, we run ATPG for ISCAS
- Page 39 and 40: asR dft = 1 2 (TMM grow +2TMM matu
- Page 41 and 42: Chapter 3System DevelopmentIn our s
- Page 43 and 44: the browser.3.2 Analysis FlowConnec
- Page 45 and 46: (a)(b)Figure 3.4: Model Editor: (a)
- Page 47 and 48: If this equation is a function, for
- Page 49 and 50: Table 4.1: ISCAS'89 benchmark circu
- Page 51 and 52: Table 4.2: Fault coverage parameter
- Page 53 and 54: Table 4.3: Fault coverage and test
- Page 55 and 56: 4.3 Case StudyIn this section, a re
- Page 57 and 58: Table 4.8: Parameters of time model
- Page 59 and 60: Table 4.12: Cost of dierent volume.
- Page 61 and 62: in Figure 4.4 for 2K volume and Fig
- Page 63 and 64: circuits were translated to Verilog
- Page 65 and 66: Design space cost for rent building
- Page 67 and 68: Revenue with DFT design:R dft = 1 2
- Page 69 and 70: 1s298s344Fault Coverage (FC)0.90.80
- Page 71 and 72: Fault Coverage (FC)10.90.80.70.60.5
- Page 73 and 74: Fault Coverage (FC)10.90.80.70.60.5
- Page 75 and 76: 1*s38584.10.90.80.7Fault Coverage (
- Page 77 and 78: Kd mp : user-dened man-power cost .
where U space is price of the building, R int is the interest ratio, and R sp ap is appreciativerate of the space.Prototypes (C proto ): There are three kinds of prototypes: FPGA, Emulator and Fab. Prototypingmay repeat many rounds until the design is well veried. For FPGA andemulator prototyping, each round needs only time to recongure hardware. If thistwo methods are used <strong>for</strong> prototyping, design equipment cost have to include cost ofFPGA or emulator. But <strong>for</strong> fab prototyping, each round needs vary large productioncost. Let N proto be the number of prototyping rounds, and U proto be the cost perround. Then, the prototype cost is given byC proto = N proto U proto + K proto ; (2.32)where K proto denotes user dened prototype cost.Cost per round of fab prototyping includes general chip cost, such as mask, wafer, andpackage cost. Non-recurring cost dominates this cost because manufacturing volumeper round is very small. We can eliminate the wafer cost and the package cost ofprototypes. Moreover, main non-recurring cost is the mask cost. The prototypescost can be estimated asC proto = N proto U mask + K proto ; (2.33)where U mask is the mask cost per round.Management CostManagers always manage several projects in the same time. A time ratio, denoted as R mang ,is used to represent the eorts that the manager involves in this project. There<strong>for</strong>e, themanagement cost in the development phase is modeled asCd mang =Xper manager(U mang R mang T d )+Kd mang ; (2.34)where R mang is the time ratio of management man-power which the manager involved in thisproject and U mang is the salary of the manager.Based on above description, the development cost (Cd) can be calculated according to(2.23).23
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